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Commit | Line | Data |
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0d75590d | 1 | #include "qemu/osdep.h" |
da34e65c | 2 | #include "qapi/error.h" |
b3946626 | 3 | #include "sysemu/hw_accel.h" |
9c17d615 | 4 | #include "sysemu/sysemu.h" |
03dd024f | 5 | #include "qemu/log.h" |
0b0b8310 | 6 | #include "qemu/error-report.h" |
9fdf0c29 | 7 | #include "cpu.h" |
63c91552 | 8 | #include "exec/exec-all.h" |
ed120055 | 9 | #include "helper_regs.h" |
0d09e41a | 10 | #include "hw/ppc/spapr.h" |
d5aea6f3 | 11 | #include "mmu-hash64.h" |
3794d548 AK |
12 | #include "cpu-models.h" |
13 | #include "trace.h" | |
14 | #include "kvm_ppc.h" | |
facdb8b6 | 15 | #include "hw/ppc/spapr_ovec.h" |
b4db5413 SJS |
16 | #include "qemu/error-report.h" |
17 | #include "mmu-book3s-v3.h" | |
f43e3525 | 18 | |
a46622fd | 19 | struct SPRSyncState { |
a46622fd AK |
20 | int spr; |
21 | target_ulong value; | |
22 | target_ulong mask; | |
23 | }; | |
24 | ||
14e6fe12 | 25 | static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) |
a46622fd | 26 | { |
14e6fe12 | 27 | struct SPRSyncState *s = arg.host_ptr; |
e0eeb4a2 | 28 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
a46622fd AK |
29 | CPUPPCState *env = &cpu->env; |
30 | ||
e0eeb4a2 | 31 | cpu_synchronize_state(cs); |
a46622fd AK |
32 | env->spr[s->spr] &= ~s->mask; |
33 | env->spr[s->spr] |= s->value; | |
34 | } | |
35 | ||
36 | static void set_spr(CPUState *cs, int spr, target_ulong value, | |
37 | target_ulong mask) | |
38 | { | |
39 | struct SPRSyncState s = { | |
a46622fd AK |
40 | .spr = spr, |
41 | .value = value, | |
42 | .mask = mask | |
43 | }; | |
14e6fe12 | 44 | run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); |
a46622fd AK |
45 | } |
46 | ||
af08a58f TH |
47 | static bool has_spr(PowerPCCPU *cpu, int spr) |
48 | { | |
49 | /* We can test whether the SPR is defined by checking for a valid name */ | |
50 | return cpu->env.spr_cb[spr].name != NULL; | |
51 | } | |
52 | ||
c6404ade | 53 | static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) |
f3c75d42 AK |
54 | { |
55 | /* | |
36778660 | 56 | * hash value/pteg group index is normalized by HPT mask |
f3c75d42 | 57 | */ |
36778660 | 58 | if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { |
f3c75d42 AK |
59 | return false; |
60 | } | |
61 | return true; | |
62 | } | |
63 | ||
ecbc25fa DG |
64 | static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) |
65 | { | |
66 | MachineState *machine = MACHINE(spapr); | |
67 | MemoryHotplugState *hpms = &spapr->hotplug_memory; | |
68 | ||
69 | if (addr < machine->ram_size) { | |
70 | return true; | |
71 | } | |
72 | if ((addr >= hpms->base) | |
73 | && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { | |
74 | return true; | |
75 | } | |
76 | ||
77 | return false; | |
78 | } | |
79 | ||
28e02042 | 80 | static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
f43e3525 DG |
81 | target_ulong opcode, target_ulong *args) |
82 | { | |
83 | target_ulong flags = args[0]; | |
c6404ade | 84 | target_ulong ptex = args[1]; |
f43e3525 DG |
85 | target_ulong pteh = args[2]; |
86 | target_ulong ptel = args[3]; | |
1f0252e6 | 87 | unsigned apshift; |
f73a2575 | 88 | target_ulong raddr; |
c6404ade | 89 | target_ulong slot; |
7222b94a | 90 | const ppc_hash_pte64_t *hptes; |
f43e3525 | 91 | |
1f0252e6 | 92 | apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); |
1114e712 DG |
93 | if (!apshift) { |
94 | /* Bad page size encoding */ | |
95 | return H_PARAMETER; | |
f43e3525 DG |
96 | } |
97 | ||
1114e712 | 98 | raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); |
f43e3525 | 99 | |
ecbc25fa | 100 | if (is_ram_address(spapr, raddr)) { |
f73a2575 | 101 | /* Regular RAM - should have WIMG=0010 */ |
d5aea6f3 | 102 | if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { |
f73a2575 DG |
103 | return H_PARAMETER; |
104 | } | |
105 | } else { | |
c1175907 | 106 | target_ulong wimg_flags; |
f73a2575 DG |
107 | /* Looks like an IO address */ |
108 | /* FIXME: What WIMG combinations could be sensible for IO? | |
109 | * For now we allow WIMG=010x, but are there others? */ | |
110 | /* FIXME: Should we check against registered IO addresses? */ | |
c1175907 AK |
111 | wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); |
112 | ||
113 | if (wimg_flags != HPTE64_R_I && | |
114 | wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { | |
f73a2575 DG |
115 | return H_PARAMETER; |
116 | } | |
f43e3525 | 117 | } |
f73a2575 | 118 | |
f43e3525 DG |
119 | pteh &= ~0x60ULL; |
120 | ||
c6404ade | 121 | if (!valid_ptex(cpu, ptex)) { |
f43e3525 DG |
122 | return H_PARAMETER; |
123 | } | |
7c43bca0 | 124 | |
c6404ade DG |
125 | slot = ptex & 7ULL; |
126 | ptex = ptex & ~7ULL; | |
127 | ||
f43e3525 | 128 | if (likely((flags & H_EXACT) == 0)) { |
7222b94a | 129 | hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); |
c6404ade | 130 | for (slot = 0; slot < 8; slot++) { |
7222b94a | 131 | if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { |
f43e3525 DG |
132 | break; |
133 | } | |
7aaf4957 | 134 | } |
7222b94a | 135 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); |
c6404ade | 136 | if (slot == 8) { |
7aaf4957 AK |
137 | return H_PTEG_FULL; |
138 | } | |
f43e3525 | 139 | } else { |
7222b94a DG |
140 | hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); |
141 | if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { | |
142 | ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); | |
f43e3525 DG |
143 | return H_PTEG_FULL; |
144 | } | |
7222b94a | 145 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); |
f43e3525 | 146 | } |
7c43bca0 | 147 | |
c6404ade | 148 | ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); |
f43e3525 | 149 | |
c6404ade | 150 | args[0] = ptex + slot; |
f43e3525 DG |
151 | return H_SUCCESS; |
152 | } | |
153 | ||
a3801402 | 154 | typedef enum { |
a3d0abae DG |
155 | REMOVE_SUCCESS = 0, |
156 | REMOVE_NOT_FOUND = 1, | |
157 | REMOVE_PARM = 2, | |
158 | REMOVE_HW = 3, | |
a3801402 | 159 | } RemoveResult; |
a3d0abae | 160 | |
7ef23068 | 161 | static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, |
a3d0abae DG |
162 | target_ulong avpn, |
163 | target_ulong flags, | |
164 | target_ulong *vp, target_ulong *rp) | |
f43e3525 | 165 | { |
7222b94a | 166 | const ppc_hash_pte64_t *hptes; |
61a36c9b | 167 | target_ulong v, r; |
f43e3525 | 168 | |
c6404ade | 169 | if (!valid_ptex(cpu, ptex)) { |
a3d0abae | 170 | return REMOVE_PARM; |
f43e3525 DG |
171 | } |
172 | ||
7222b94a DG |
173 | hptes = ppc_hash64_map_hptes(cpu, ptex, 1); |
174 | v = ppc_hash64_hpte0(cpu, hptes, 0); | |
175 | r = ppc_hash64_hpte1(cpu, hptes, 0); | |
176 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); | |
f43e3525 | 177 | |
d5aea6f3 | 178 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 DG |
179 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || |
180 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { | |
a3d0abae | 181 | return REMOVE_NOT_FOUND; |
f43e3525 | 182 | } |
35f9304d | 183 | *vp = v; |
a3d0abae | 184 | *rp = r; |
7ef23068 | 185 | ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); |
61a36c9b | 186 | ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); |
a3d0abae DG |
187 | return REMOVE_SUCCESS; |
188 | } | |
189 | ||
28e02042 | 190 | static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a3d0abae DG |
191 | target_ulong opcode, target_ulong *args) |
192 | { | |
cd0c6f47 | 193 | CPUPPCState *env = &cpu->env; |
a3d0abae | 194 | target_ulong flags = args[0]; |
c6404ade | 195 | target_ulong ptex = args[1]; |
a3d0abae | 196 | target_ulong avpn = args[2]; |
a3801402 | 197 | RemoveResult ret; |
a3d0abae | 198 | |
c6404ade | 199 | ret = remove_hpte(cpu, ptex, avpn, flags, |
a3d0abae DG |
200 | &args[0], &args[1]); |
201 | ||
202 | switch (ret) { | |
203 | case REMOVE_SUCCESS: | |
e3cffe6f | 204 | check_tlb_flush(env, true); |
a3d0abae DG |
205 | return H_SUCCESS; |
206 | ||
207 | case REMOVE_NOT_FOUND: | |
208 | return H_NOT_FOUND; | |
209 | ||
210 | case REMOVE_PARM: | |
211 | return H_PARAMETER; | |
212 | ||
213 | case REMOVE_HW: | |
214 | return H_HARDWARE; | |
215 | } | |
216 | ||
9a39970d | 217 | g_assert_not_reached(); |
a3d0abae DG |
218 | } |
219 | ||
220 | #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL | |
221 | #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL | |
222 | #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL | |
223 | #define H_BULK_REMOVE_END 0xc000000000000000ULL | |
224 | #define H_BULK_REMOVE_CODE 0x3000000000000000ULL | |
225 | #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL | |
226 | #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL | |
227 | #define H_BULK_REMOVE_PARM 0x2000000000000000ULL | |
228 | #define H_BULK_REMOVE_HW 0x3000000000000000ULL | |
229 | #define H_BULK_REMOVE_RC 0x0c00000000000000ULL | |
230 | #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL | |
231 | #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL | |
232 | #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL | |
233 | #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL | |
234 | #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL | |
235 | ||
236 | #define H_BULK_REMOVE_MAX_BATCH 4 | |
237 | ||
28e02042 | 238 | static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a3d0abae DG |
239 | target_ulong opcode, target_ulong *args) |
240 | { | |
cd0c6f47 | 241 | CPUPPCState *env = &cpu->env; |
a3d0abae | 242 | int i; |
cd0c6f47 | 243 | target_ulong rc = H_SUCCESS; |
a3d0abae DG |
244 | |
245 | for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { | |
246 | target_ulong *tsh = &args[i*2]; | |
247 | target_ulong tsl = args[i*2 + 1]; | |
248 | target_ulong v, r, ret; | |
249 | ||
250 | if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { | |
251 | break; | |
252 | } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { | |
253 | return H_PARAMETER; | |
254 | } | |
255 | ||
256 | *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; | |
257 | *tsh |= H_BULK_REMOVE_RESPONSE; | |
258 | ||
259 | if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { | |
260 | *tsh |= H_BULK_REMOVE_PARM; | |
261 | return H_PARAMETER; | |
262 | } | |
263 | ||
7ef23068 | 264 | ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, |
a3d0abae DG |
265 | (*tsh & H_BULK_REMOVE_FLAGS) >> 26, |
266 | &v, &r); | |
267 | ||
268 | *tsh |= ret << 60; | |
269 | ||
270 | switch (ret) { | |
271 | case REMOVE_SUCCESS: | |
d5aea6f3 | 272 | *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; |
a3d0abae DG |
273 | break; |
274 | ||
275 | case REMOVE_PARM: | |
cd0c6f47 BH |
276 | rc = H_PARAMETER; |
277 | goto exit; | |
a3d0abae DG |
278 | |
279 | case REMOVE_HW: | |
cd0c6f47 BH |
280 | rc = H_HARDWARE; |
281 | goto exit; | |
a3d0abae DG |
282 | } |
283 | } | |
cd0c6f47 | 284 | exit: |
e3cffe6f | 285 | check_tlb_flush(env, true); |
a3d0abae | 286 | |
cd0c6f47 | 287 | return rc; |
f43e3525 DG |
288 | } |
289 | ||
28e02042 | 290 | static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
f43e3525 DG |
291 | target_ulong opcode, target_ulong *args) |
292 | { | |
b13ce26d | 293 | CPUPPCState *env = &cpu->env; |
f43e3525 | 294 | target_ulong flags = args[0]; |
c6404ade | 295 | target_ulong ptex = args[1]; |
f43e3525 | 296 | target_ulong avpn = args[2]; |
7222b94a | 297 | const ppc_hash_pte64_t *hptes; |
61a36c9b | 298 | target_ulong v, r; |
f43e3525 | 299 | |
c6404ade | 300 | if (!valid_ptex(cpu, ptex)) { |
f43e3525 DG |
301 | return H_PARAMETER; |
302 | } | |
303 | ||
7222b94a DG |
304 | hptes = ppc_hash64_map_hptes(cpu, ptex, 1); |
305 | v = ppc_hash64_hpte0(cpu, hptes, 0); | |
306 | r = ppc_hash64_hpte1(cpu, hptes, 0); | |
307 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); | |
f43e3525 | 308 | |
d5aea6f3 | 309 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 | 310 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { |
f43e3525 DG |
311 | return H_NOT_FOUND; |
312 | } | |
313 | ||
d5aea6f3 DG |
314 | r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | |
315 | HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); | |
316 | r |= (flags << 55) & HPTE64_R_PP0; | |
317 | r |= (flags << 48) & HPTE64_R_KEY_HI; | |
318 | r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); | |
c6404ade | 319 | ppc_hash64_store_hpte(cpu, ptex, |
3f94170b | 320 | (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); |
c6404ade | 321 | ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); |
d76ab5e1 ND |
322 | /* Flush the tlb */ |
323 | check_tlb_flush(env, true); | |
f43e3525 | 324 | /* Don't need a memory barrier, due to qemu's global lock */ |
c6404ade | 325 | ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); |
f43e3525 DG |
326 | return H_SUCCESS; |
327 | } | |
328 | ||
28e02042 | 329 | static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
6bbd5dde EC |
330 | target_ulong opcode, target_ulong *args) |
331 | { | |
6bbd5dde | 332 | target_ulong flags = args[0]; |
c6404ade | 333 | target_ulong ptex = args[1]; |
6bbd5dde EC |
334 | uint8_t *hpte; |
335 | int i, ridx, n_entries = 1; | |
336 | ||
c6404ade | 337 | if (!valid_ptex(cpu, ptex)) { |
6bbd5dde EC |
338 | return H_PARAMETER; |
339 | } | |
340 | ||
341 | if (flags & H_READ_4) { | |
342 | /* Clear the two low order bits */ | |
c6404ade | 343 | ptex &= ~(3ULL); |
6bbd5dde EC |
344 | n_entries = 4; |
345 | } | |
346 | ||
e57ca75c | 347 | hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); |
6bbd5dde EC |
348 | |
349 | for (i = 0, ridx = 0; i < n_entries; i++) { | |
350 | args[ridx++] = ldq_p(hpte); | |
351 | args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
352 | hpte += HASH_PTE_SIZE_64; | |
353 | } | |
354 | ||
355 | return H_SUCCESS; | |
356 | } | |
357 | ||
0b0b8310 DG |
358 | struct sPAPRPendingHPT { |
359 | /* These fields are read-only after initialization */ | |
360 | int shift; | |
361 | QemuThread thread; | |
362 | ||
363 | /* These fields are protected by the BQL */ | |
364 | bool complete; | |
365 | ||
366 | /* These fields are private to the preparation thread if | |
367 | * !complete, otherwise protected by the BQL */ | |
368 | int ret; | |
369 | void *hpt; | |
370 | }; | |
371 | ||
372 | static void free_pending_hpt(sPAPRPendingHPT *pending) | |
373 | { | |
374 | if (pending->hpt) { | |
375 | qemu_vfree(pending->hpt); | |
376 | } | |
377 | ||
378 | g_free(pending); | |
379 | } | |
380 | ||
381 | static void *hpt_prepare_thread(void *opaque) | |
382 | { | |
383 | sPAPRPendingHPT *pending = opaque; | |
384 | size_t size = 1ULL << pending->shift; | |
385 | ||
386 | pending->hpt = qemu_memalign(size, size); | |
387 | if (pending->hpt) { | |
388 | memset(pending->hpt, 0, size); | |
389 | pending->ret = H_SUCCESS; | |
390 | } else { | |
391 | pending->ret = H_NO_MEM; | |
392 | } | |
393 | ||
394 | qemu_mutex_lock_iothread(); | |
395 | ||
396 | if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { | |
397 | /* Ready to go */ | |
398 | pending->complete = true; | |
399 | } else { | |
400 | /* We've been cancelled, clean ourselves up */ | |
401 | free_pending_hpt(pending); | |
402 | } | |
403 | ||
404 | qemu_mutex_unlock_iothread(); | |
405 | return NULL; | |
406 | } | |
407 | ||
408 | /* Must be called with BQL held */ | |
409 | static void cancel_hpt_prepare(sPAPRMachineState *spapr) | |
410 | { | |
411 | sPAPRPendingHPT *pending = spapr->pending_hpt; | |
412 | ||
413 | /* Let the thread know it's cancelled */ | |
414 | spapr->pending_hpt = NULL; | |
415 | ||
416 | if (!pending) { | |
417 | /* Nothing to do */ | |
418 | return; | |
419 | } | |
420 | ||
421 | if (!pending->complete) { | |
422 | /* thread will clean itself up */ | |
423 | return; | |
424 | } | |
425 | ||
426 | free_pending_hpt(pending); | |
427 | } | |
428 | ||
b55d295e DG |
429 | /* Convert a return code from the KVM ioctl()s implementing resize HPT |
430 | * into a PAPR hypercall return code */ | |
431 | static target_ulong resize_hpt_convert_rc(int ret) | |
432 | { | |
433 | if (ret >= 100000) { | |
434 | return H_LONG_BUSY_ORDER_100_SEC; | |
435 | } else if (ret >= 10000) { | |
436 | return H_LONG_BUSY_ORDER_10_SEC; | |
437 | } else if (ret >= 1000) { | |
438 | return H_LONG_BUSY_ORDER_1_SEC; | |
439 | } else if (ret >= 100) { | |
440 | return H_LONG_BUSY_ORDER_100_MSEC; | |
441 | } else if (ret >= 10) { | |
442 | return H_LONG_BUSY_ORDER_10_MSEC; | |
443 | } else if (ret > 0) { | |
444 | return H_LONG_BUSY_ORDER_1_MSEC; | |
445 | } | |
446 | ||
447 | switch (ret) { | |
448 | case 0: | |
449 | return H_SUCCESS; | |
450 | case -EPERM: | |
451 | return H_AUTHORITY; | |
452 | case -EINVAL: | |
453 | return H_PARAMETER; | |
454 | case -ENXIO: | |
455 | return H_CLOSED; | |
456 | case -ENOSPC: | |
457 | return H_PTEG_FULL; | |
458 | case -EBUSY: | |
459 | return H_BUSY; | |
460 | case -ENOMEM: | |
461 | return H_NO_MEM; | |
462 | default: | |
463 | return H_HARDWARE; | |
464 | } | |
465 | } | |
466 | ||
30f4b05b DG |
467 | static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, |
468 | sPAPRMachineState *spapr, | |
469 | target_ulong opcode, | |
470 | target_ulong *args) | |
471 | { | |
472 | target_ulong flags = args[0]; | |
0b0b8310 DG |
473 | int shift = args[1]; |
474 | sPAPRPendingHPT *pending = spapr->pending_hpt; | |
475 | uint64_t current_ram_size = MACHINE(spapr)->ram_size; | |
b55d295e | 476 | int rc; |
30f4b05b DG |
477 | |
478 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { | |
479 | return H_AUTHORITY; | |
480 | } | |
481 | ||
0b0b8310 DG |
482 | if (!spapr->htab_shift) { |
483 | /* Radix guest, no HPT */ | |
484 | return H_NOT_AVAILABLE; | |
485 | } | |
486 | ||
30f4b05b | 487 | trace_spapr_h_resize_hpt_prepare(flags, shift); |
0b0b8310 DG |
488 | |
489 | if (flags != 0) { | |
490 | return H_PARAMETER; | |
491 | } | |
492 | ||
493 | if (shift && ((shift < 18) || (shift > 46))) { | |
494 | return H_PARAMETER; | |
495 | } | |
496 | ||
497 | current_ram_size = pc_existing_dimms_capacity(&error_fatal); | |
498 | ||
499 | /* We only allow the guest to allocate an HPT one order above what | |
500 | * we'd normally give them (to stop a small guest claiming a huge | |
501 | * chunk of resources in the HPT */ | |
502 | if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { | |
503 | return H_RESOURCE; | |
504 | } | |
505 | ||
b55d295e DG |
506 | rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); |
507 | if (rc != -ENOSYS) { | |
508 | return resize_hpt_convert_rc(rc); | |
509 | } | |
510 | ||
0b0b8310 DG |
511 | if (pending) { |
512 | /* something already in progress */ | |
513 | if (pending->shift == shift) { | |
514 | /* and it's suitable */ | |
515 | if (pending->complete) { | |
516 | return pending->ret; | |
517 | } else { | |
518 | return H_LONG_BUSY_ORDER_100_MSEC; | |
519 | } | |
520 | } | |
521 | ||
522 | /* not suitable, cancel and replace */ | |
523 | cancel_hpt_prepare(spapr); | |
524 | } | |
525 | ||
526 | if (!shift) { | |
527 | /* nothing to do */ | |
528 | return H_SUCCESS; | |
529 | } | |
530 | ||
531 | /* start new prepare */ | |
532 | ||
533 | pending = g_new0(sPAPRPendingHPT, 1); | |
534 | pending->shift = shift; | |
535 | pending->ret = H_HARDWARE; | |
536 | ||
537 | qemu_thread_create(&pending->thread, "sPAPR HPT prepare", | |
538 | hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); | |
539 | ||
540 | spapr->pending_hpt = pending; | |
541 | ||
542 | /* In theory we could estimate the time more accurately based on | |
543 | * the new size, but there's not much point */ | |
544 | return H_LONG_BUSY_ORDER_100_MSEC; | |
545 | } | |
546 | ||
547 | static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) | |
548 | { | |
549 | uint8_t *addr = htab; | |
550 | ||
551 | addr += pteg * HASH_PTEG_SIZE_64; | |
552 | addr += slot * HASH_PTE_SIZE_64; | |
553 | return ldq_p(addr); | |
554 | } | |
555 | ||
556 | static void new_hpte_store(void *htab, uint64_t pteg, int slot, | |
557 | uint64_t pte0, uint64_t pte1) | |
558 | { | |
559 | uint8_t *addr = htab; | |
560 | ||
561 | addr += pteg * HASH_PTEG_SIZE_64; | |
562 | addr += slot * HASH_PTE_SIZE_64; | |
563 | ||
564 | stq_p(addr, pte0); | |
565 | stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); | |
566 | } | |
567 | ||
568 | static int rehash_hpte(PowerPCCPU *cpu, | |
569 | const ppc_hash_pte64_t *hptes, | |
570 | void *old_hpt, uint64_t oldsize, | |
571 | void *new_hpt, uint64_t newsize, | |
572 | uint64_t pteg, int slot) | |
573 | { | |
574 | uint64_t old_hash_mask = (oldsize >> 7) - 1; | |
575 | uint64_t new_hash_mask = (newsize >> 7) - 1; | |
576 | target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); | |
577 | target_ulong pte1; | |
578 | uint64_t avpn; | |
579 | unsigned base_pg_shift; | |
580 | uint64_t hash, new_pteg, replace_pte0; | |
581 | ||
582 | if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { | |
583 | return H_SUCCESS; | |
584 | } | |
585 | ||
586 | pte1 = ppc_hash64_hpte1(cpu, hptes, slot); | |
587 | ||
588 | base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); | |
589 | assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ | |
590 | avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); | |
591 | ||
592 | if (pte0 & HPTE64_V_SECONDARY) { | |
593 | pteg = ~pteg; | |
594 | } | |
595 | ||
596 | if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { | |
597 | uint64_t offset, vsid; | |
598 | ||
599 | /* We only have 28 - 23 bits of offset in avpn */ | |
600 | offset = (avpn & 0x1f) << 23; | |
601 | vsid = avpn >> 5; | |
602 | /* We can find more bits from the pteg value */ | |
603 | if (base_pg_shift < 23) { | |
604 | offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; | |
605 | } | |
606 | ||
607 | hash = vsid ^ (offset >> base_pg_shift); | |
608 | } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { | |
609 | uint64_t offset, vsid; | |
610 | ||
611 | /* We only have 40 - 23 bits of seg_off in avpn */ | |
612 | offset = (avpn & 0x1ffff) << 23; | |
613 | vsid = avpn >> 17; | |
614 | if (base_pg_shift < 23) { | |
615 | offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) | |
616 | << base_pg_shift; | |
617 | } | |
618 | ||
619 | hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); | |
620 | } else { | |
621 | error_report("rehash_pte: Bad segment size in HPTE"); | |
622 | return H_HARDWARE; | |
623 | } | |
624 | ||
625 | new_pteg = hash & new_hash_mask; | |
626 | if (pte0 & HPTE64_V_SECONDARY) { | |
627 | assert(~pteg == (hash & old_hash_mask)); | |
628 | new_pteg = ~new_pteg; | |
629 | } else { | |
630 | assert(pteg == (hash & old_hash_mask)); | |
631 | } | |
632 | assert((oldsize != newsize) || (pteg == new_pteg)); | |
633 | replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); | |
634 | /* | |
635 | * Strictly speaking, we don't need all these tests, since we only | |
636 | * ever rehash bolted HPTEs. We might in future handle non-bolted | |
637 | * HPTEs, though so make the logic correct for those cases as | |
638 | * well. | |
639 | */ | |
640 | if (replace_pte0 & HPTE64_V_VALID) { | |
641 | assert(newsize < oldsize); | |
642 | if (replace_pte0 & HPTE64_V_BOLTED) { | |
643 | if (pte0 & HPTE64_V_BOLTED) { | |
644 | /* Bolted collision, nothing we can do */ | |
645 | return H_PTEG_FULL; | |
646 | } else { | |
647 | /* Discard this hpte */ | |
648 | return H_SUCCESS; | |
649 | } | |
650 | } | |
651 | } | |
652 | ||
653 | new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); | |
654 | return H_SUCCESS; | |
655 | } | |
656 | ||
657 | static int rehash_hpt(PowerPCCPU *cpu, | |
658 | void *old_hpt, uint64_t oldsize, | |
659 | void *new_hpt, uint64_t newsize) | |
660 | { | |
661 | uint64_t n_ptegs = oldsize >> 7; | |
662 | uint64_t pteg; | |
663 | int slot; | |
664 | int rc; | |
665 | ||
666 | for (pteg = 0; pteg < n_ptegs; pteg++) { | |
667 | hwaddr ptex = pteg * HPTES_PER_GROUP; | |
668 | const ppc_hash_pte64_t *hptes | |
669 | = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); | |
670 | ||
671 | if (!hptes) { | |
672 | return H_HARDWARE; | |
673 | } | |
674 | ||
675 | for (slot = 0; slot < HPTES_PER_GROUP; slot++) { | |
676 | rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, | |
677 | pteg, slot); | |
678 | if (rc != H_SUCCESS) { | |
679 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); | |
680 | return rc; | |
681 | } | |
682 | } | |
683 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); | |
684 | } | |
685 | ||
686 | return H_SUCCESS; | |
30f4b05b DG |
687 | } |
688 | ||
689 | static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, | |
690 | sPAPRMachineState *spapr, | |
691 | target_ulong opcode, | |
692 | target_ulong *args) | |
693 | { | |
694 | target_ulong flags = args[0]; | |
695 | target_ulong shift = args[1]; | |
0b0b8310 DG |
696 | sPAPRPendingHPT *pending = spapr->pending_hpt; |
697 | int rc; | |
698 | size_t newsize; | |
30f4b05b DG |
699 | |
700 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { | |
701 | return H_AUTHORITY; | |
702 | } | |
703 | ||
704 | trace_spapr_h_resize_hpt_commit(flags, shift); | |
0b0b8310 | 705 | |
b55d295e DG |
706 | rc = kvmppc_resize_hpt_commit(cpu, flags, shift); |
707 | if (rc != -ENOSYS) { | |
708 | return resize_hpt_convert_rc(rc); | |
709 | } | |
710 | ||
0b0b8310 DG |
711 | if (flags != 0) { |
712 | return H_PARAMETER; | |
713 | } | |
714 | ||
715 | if (!pending || (pending->shift != shift)) { | |
716 | /* no matching prepare */ | |
717 | return H_CLOSED; | |
718 | } | |
719 | ||
720 | if (!pending->complete) { | |
721 | /* prepare has not completed */ | |
722 | return H_BUSY; | |
723 | } | |
724 | ||
725 | /* Shouldn't have got past PREPARE without an HPT */ | |
726 | g_assert(spapr->htab_shift); | |
727 | ||
728 | newsize = 1ULL << pending->shift; | |
729 | rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), | |
730 | pending->hpt, newsize); | |
731 | if (rc == H_SUCCESS) { | |
732 | qemu_vfree(spapr->htab); | |
733 | spapr->htab = pending->hpt; | |
734 | spapr->htab_shift = pending->shift; | |
735 | ||
b55d295e DG |
736 | if (kvm_enabled()) { |
737 | /* For KVM PR, update the HPT pointer */ | |
738 | target_ulong sdr1 = (target_ulong)(uintptr_t)spapr->htab | |
739 | | (spapr->htab_shift - 18); | |
740 | kvmppc_update_sdr1(sdr1); | |
741 | } | |
742 | ||
0b0b8310 DG |
743 | pending->hpt = NULL; /* so it's not free()d */ |
744 | } | |
745 | ||
746 | /* Clean up */ | |
747 | spapr->pending_hpt = NULL; | |
748 | free_pending_hpt(pending); | |
749 | ||
750 | return rc; | |
30f4b05b DG |
751 | } |
752 | ||
423576f7 TH |
753 | static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
754 | target_ulong opcode, target_ulong *args) | |
755 | { | |
756 | cpu_synchronize_state(CPU(cpu)); | |
757 | cpu->env.spr[SPR_SPRG0] = args[0]; | |
758 | ||
759 | return H_SUCCESS; | |
760 | } | |
761 | ||
28e02042 | 762 | static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
821303f5 DG |
763 | target_ulong opcode, target_ulong *args) |
764 | { | |
af08a58f TH |
765 | if (!has_spr(cpu, SPR_DABR)) { |
766 | return H_HARDWARE; /* DABR register not available */ | |
767 | } | |
768 | cpu_synchronize_state(CPU(cpu)); | |
769 | ||
770 | if (has_spr(cpu, SPR_DABRX)) { | |
771 | cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ | |
772 | } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ | |
773 | return H_RESERVED_DABR; | |
774 | } | |
775 | ||
776 | cpu->env.spr[SPR_DABR] = args[0]; | |
777 | return H_SUCCESS; | |
821303f5 DG |
778 | } |
779 | ||
e49ff266 TH |
780 | static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
781 | target_ulong opcode, target_ulong *args) | |
782 | { | |
783 | target_ulong dabrx = args[1]; | |
784 | ||
785 | if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { | |
786 | return H_HARDWARE; | |
787 | } | |
788 | ||
789 | if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 | |
790 | || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { | |
791 | return H_PARAMETER; | |
792 | } | |
793 | ||
794 | cpu_synchronize_state(CPU(cpu)); | |
795 | cpu->env.spr[SPR_DABRX] = dabrx; | |
796 | cpu->env.spr[SPR_DABR] = args[0]; | |
797 | ||
798 | return H_SUCCESS; | |
799 | } | |
800 | ||
3240dd9a TH |
801 | static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
802 | target_ulong opcode, target_ulong *args) | |
803 | { | |
804 | target_ulong flags = args[0]; | |
805 | hwaddr dst = args[1]; | |
806 | hwaddr src = args[2]; | |
807 | hwaddr len = TARGET_PAGE_SIZE; | |
808 | uint8_t *pdst, *psrc; | |
809 | target_long ret = H_SUCCESS; | |
810 | ||
811 | if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE | |
812 | | H_COPY_PAGE | H_ZERO_PAGE)) { | |
813 | qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", | |
814 | flags); | |
815 | return H_PARAMETER; | |
816 | } | |
817 | ||
818 | /* Map-in destination */ | |
819 | if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { | |
820 | return H_PARAMETER; | |
821 | } | |
822 | pdst = cpu_physical_memory_map(dst, &len, 1); | |
823 | if (!pdst || len != TARGET_PAGE_SIZE) { | |
824 | return H_PARAMETER; | |
825 | } | |
826 | ||
827 | if (flags & H_COPY_PAGE) { | |
828 | /* Map-in source, copy to destination, and unmap source again */ | |
829 | if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { | |
830 | ret = H_PARAMETER; | |
831 | goto unmap_out; | |
832 | } | |
833 | psrc = cpu_physical_memory_map(src, &len, 0); | |
834 | if (!psrc || len != TARGET_PAGE_SIZE) { | |
835 | ret = H_PARAMETER; | |
836 | goto unmap_out; | |
837 | } | |
838 | memcpy(pdst, psrc, len); | |
839 | cpu_physical_memory_unmap(psrc, len, 0, len); | |
840 | } else if (flags & H_ZERO_PAGE) { | |
841 | memset(pdst, 0, len); /* Just clear the destination page */ | |
842 | } | |
843 | ||
844 | if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { | |
845 | kvmppc_dcbst_range(cpu, pdst, len); | |
846 | } | |
847 | if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { | |
848 | if (kvm_enabled()) { | |
849 | kvmppc_icbi_range(cpu, pdst, len); | |
850 | } else { | |
851 | tb_flush(CPU(cpu)); | |
852 | } | |
853 | } | |
854 | ||
855 | unmap_out: | |
856 | cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); | |
857 | return ret; | |
858 | } | |
859 | ||
ed120055 DG |
860 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
861 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL | |
862 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL | |
863 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL | |
864 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL | |
865 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL | |
866 | ||
867 | #define VPA_MIN_SIZE 640 | |
868 | #define VPA_SIZE_OFFSET 0x4 | |
869 | #define VPA_SHARED_PROC_OFFSET 0x9 | |
870 | #define VPA_SHARED_PROC_VAL 0x2 | |
871 | ||
e2684c0b | 872 | static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 873 | { |
33276f1b | 874 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
875 | uint16_t size; |
876 | uint8_t tmp; | |
877 | ||
878 | if (vpa == 0) { | |
879 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); | |
880 | return H_HARDWARE; | |
881 | } | |
882 | ||
883 | if (vpa % env->dcache_line_size) { | |
884 | return H_PARAMETER; | |
885 | } | |
886 | /* FIXME: bounds check the address */ | |
887 | ||
41701aa4 | 888 | size = lduw_be_phys(cs->as, vpa + 0x4); |
ed120055 DG |
889 | |
890 | if (size < VPA_MIN_SIZE) { | |
891 | return H_PARAMETER; | |
892 | } | |
893 | ||
894 | /* VPA is not allowed to cross a page boundary */ | |
895 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { | |
896 | return H_PARAMETER; | |
897 | } | |
898 | ||
1bfb37d1 | 899 | env->vpa_addr = vpa; |
ed120055 | 900 | |
2c17449b | 901 | tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
ed120055 | 902 | tmp |= VPA_SHARED_PROC_VAL; |
db3be60d | 903 | stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
ed120055 DG |
904 | |
905 | return H_SUCCESS; | |
906 | } | |
907 | ||
e2684c0b | 908 | static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 909 | { |
1bfb37d1 | 910 | if (env->slb_shadow_addr) { |
ed120055 DG |
911 | return H_RESOURCE; |
912 | } | |
913 | ||
1bfb37d1 | 914 | if (env->dtl_addr) { |
ed120055 DG |
915 | return H_RESOURCE; |
916 | } | |
917 | ||
1bfb37d1 | 918 | env->vpa_addr = 0; |
ed120055 DG |
919 | return H_SUCCESS; |
920 | } | |
921 | ||
e2684c0b | 922 | static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 923 | { |
33276f1b | 924 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
925 | uint32_t size; |
926 | ||
927 | if (addr == 0) { | |
928 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); | |
929 | return H_HARDWARE; | |
930 | } | |
931 | ||
fdfba1a2 | 932 | size = ldl_be_phys(cs->as, addr + 0x4); |
ed120055 DG |
933 | if (size < 0x8) { |
934 | return H_PARAMETER; | |
935 | } | |
936 | ||
937 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { | |
938 | return H_PARAMETER; | |
939 | } | |
940 | ||
1bfb37d1 | 941 | if (!env->vpa_addr) { |
ed120055 DG |
942 | return H_RESOURCE; |
943 | } | |
944 | ||
1bfb37d1 DG |
945 | env->slb_shadow_addr = addr; |
946 | env->slb_shadow_size = size; | |
ed120055 DG |
947 | |
948 | return H_SUCCESS; | |
949 | } | |
950 | ||
e2684c0b | 951 | static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 952 | { |
1bfb37d1 DG |
953 | env->slb_shadow_addr = 0; |
954 | env->slb_shadow_size = 0; | |
ed120055 DG |
955 | return H_SUCCESS; |
956 | } | |
957 | ||
e2684c0b | 958 | static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 959 | { |
33276f1b | 960 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
961 | uint32_t size; |
962 | ||
963 | if (addr == 0) { | |
964 | hcall_dprintf("Can't cope with DTL at logical 0\n"); | |
965 | return H_HARDWARE; | |
966 | } | |
967 | ||
fdfba1a2 | 968 | size = ldl_be_phys(cs->as, addr + 0x4); |
ed120055 DG |
969 | |
970 | if (size < 48) { | |
971 | return H_PARAMETER; | |
972 | } | |
973 | ||
1bfb37d1 | 974 | if (!env->vpa_addr) { |
ed120055 DG |
975 | return H_RESOURCE; |
976 | } | |
977 | ||
1bfb37d1 | 978 | env->dtl_addr = addr; |
ed120055 DG |
979 | env->dtl_size = size; |
980 | ||
981 | return H_SUCCESS; | |
982 | } | |
983 | ||
73f7821b | 984 | static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 985 | { |
1bfb37d1 | 986 | env->dtl_addr = 0; |
ed120055 DG |
987 | env->dtl_size = 0; |
988 | ||
989 | return H_SUCCESS; | |
990 | } | |
991 | ||
28e02042 | 992 | static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ed120055 DG |
993 | target_ulong opcode, target_ulong *args) |
994 | { | |
995 | target_ulong flags = args[0]; | |
996 | target_ulong procno = args[1]; | |
997 | target_ulong vpa = args[2]; | |
998 | target_ulong ret = H_PARAMETER; | |
e2684c0b | 999 | CPUPPCState *tenv; |
0f20ba62 | 1000 | PowerPCCPU *tcpu; |
ed120055 | 1001 | |
2e886fb3 | 1002 | tcpu = spapr_find_cpu(procno); |
5353d03d | 1003 | if (!tcpu) { |
ed120055 DG |
1004 | return H_PARAMETER; |
1005 | } | |
0f20ba62 | 1006 | tenv = &tcpu->env; |
ed120055 DG |
1007 | |
1008 | switch (flags) { | |
1009 | case FLAGS_REGISTER_VPA: | |
1010 | ret = register_vpa(tenv, vpa); | |
1011 | break; | |
1012 | ||
1013 | case FLAGS_DEREGISTER_VPA: | |
1014 | ret = deregister_vpa(tenv, vpa); | |
1015 | break; | |
1016 | ||
1017 | case FLAGS_REGISTER_SLBSHADOW: | |
1018 | ret = register_slb_shadow(tenv, vpa); | |
1019 | break; | |
1020 | ||
1021 | case FLAGS_DEREGISTER_SLBSHADOW: | |
1022 | ret = deregister_slb_shadow(tenv, vpa); | |
1023 | break; | |
1024 | ||
1025 | case FLAGS_REGISTER_DTL: | |
1026 | ret = register_dtl(tenv, vpa); | |
1027 | break; | |
1028 | ||
1029 | case FLAGS_DEREGISTER_DTL: | |
1030 | ret = deregister_dtl(tenv, vpa); | |
1031 | break; | |
1032 | } | |
1033 | ||
1034 | return ret; | |
1035 | } | |
1036 | ||
28e02042 | 1037 | static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ed120055 DG |
1038 | target_ulong opcode, target_ulong *args) |
1039 | { | |
b13ce26d | 1040 | CPUPPCState *env = &cpu->env; |
fcd7d003 | 1041 | CPUState *cs = CPU(cpu); |
b13ce26d | 1042 | |
ed120055 DG |
1043 | env->msr |= (1ULL << MSR_EE); |
1044 | hreg_compute_hflags(env); | |
fcd7d003 | 1045 | if (!cpu_has_work(cs)) { |
259186a7 | 1046 | cs->halted = 1; |
27103424 | 1047 | cs->exception_index = EXCP_HLT; |
fcd7d003 | 1048 | cs->exit_request = 1; |
ed120055 DG |
1049 | } |
1050 | return H_SUCCESS; | |
1051 | } | |
1052 | ||
28e02042 | 1053 | static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
39ac8455 DG |
1054 | target_ulong opcode, target_ulong *args) |
1055 | { | |
1056 | target_ulong rtas_r3 = args[0]; | |
4fe822e0 AK |
1057 | uint32_t token = rtas_ld(rtas_r3, 0); |
1058 | uint32_t nargs = rtas_ld(rtas_r3, 1); | |
1059 | uint32_t nret = rtas_ld(rtas_r3, 2); | |
39ac8455 | 1060 | |
210b580b | 1061 | return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, |
39ac8455 DG |
1062 | nret, rtas_r3 + 12 + 4*nargs); |
1063 | } | |
1064 | ||
28e02042 | 1065 | static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
1066 | target_ulong opcode, target_ulong *args) |
1067 | { | |
fdfba1a2 | 1068 | CPUState *cs = CPU(cpu); |
827200a2 DG |
1069 | target_ulong size = args[0]; |
1070 | target_ulong addr = args[1]; | |
1071 | ||
1072 | switch (size) { | |
1073 | case 1: | |
2c17449b | 1074 | args[0] = ldub_phys(cs->as, addr); |
827200a2 DG |
1075 | return H_SUCCESS; |
1076 | case 2: | |
41701aa4 | 1077 | args[0] = lduw_phys(cs->as, addr); |
827200a2 DG |
1078 | return H_SUCCESS; |
1079 | case 4: | |
fdfba1a2 | 1080 | args[0] = ldl_phys(cs->as, addr); |
827200a2 DG |
1081 | return H_SUCCESS; |
1082 | case 8: | |
2c17449b | 1083 | args[0] = ldq_phys(cs->as, addr); |
827200a2 DG |
1084 | return H_SUCCESS; |
1085 | } | |
1086 | return H_PARAMETER; | |
1087 | } | |
1088 | ||
28e02042 | 1089 | static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
1090 | target_ulong opcode, target_ulong *args) |
1091 | { | |
f606604f EI |
1092 | CPUState *cs = CPU(cpu); |
1093 | ||
827200a2 DG |
1094 | target_ulong size = args[0]; |
1095 | target_ulong addr = args[1]; | |
1096 | target_ulong val = args[2]; | |
1097 | ||
1098 | switch (size) { | |
1099 | case 1: | |
db3be60d | 1100 | stb_phys(cs->as, addr, val); |
827200a2 DG |
1101 | return H_SUCCESS; |
1102 | case 2: | |
5ce5944d | 1103 | stw_phys(cs->as, addr, val); |
827200a2 DG |
1104 | return H_SUCCESS; |
1105 | case 4: | |
ab1da857 | 1106 | stl_phys(cs->as, addr, val); |
827200a2 DG |
1107 | return H_SUCCESS; |
1108 | case 8: | |
f606604f | 1109 | stq_phys(cs->as, addr, val); |
827200a2 DG |
1110 | return H_SUCCESS; |
1111 | } | |
1112 | return H_PARAMETER; | |
1113 | } | |
1114 | ||
28e02042 | 1115 | static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c73e3771 BH |
1116 | target_ulong opcode, target_ulong *args) |
1117 | { | |
fdfba1a2 EI |
1118 | CPUState *cs = CPU(cpu); |
1119 | ||
c73e3771 BH |
1120 | target_ulong dst = args[0]; /* Destination address */ |
1121 | target_ulong src = args[1]; /* Source address */ | |
1122 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ | |
1123 | target_ulong count = args[3]; /* Element count */ | |
1124 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ | |
1125 | uint64_t tmp; | |
1126 | unsigned int mask = (1 << esize) - 1; | |
1127 | int step = 1 << esize; | |
1128 | ||
1129 | if (count > 0x80000000) { | |
1130 | return H_PARAMETER; | |
1131 | } | |
1132 | ||
1133 | if ((dst & mask) || (src & mask) || (op > 1)) { | |
1134 | return H_PARAMETER; | |
1135 | } | |
1136 | ||
1137 | if (dst >= src && dst < (src + (count << esize))) { | |
1138 | dst = dst + ((count - 1) << esize); | |
1139 | src = src + ((count - 1) << esize); | |
1140 | step = -step; | |
1141 | } | |
1142 | ||
1143 | while (count--) { | |
1144 | switch (esize) { | |
1145 | case 0: | |
2c17449b | 1146 | tmp = ldub_phys(cs->as, src); |
c73e3771 BH |
1147 | break; |
1148 | case 1: | |
41701aa4 | 1149 | tmp = lduw_phys(cs->as, src); |
c73e3771 BH |
1150 | break; |
1151 | case 2: | |
fdfba1a2 | 1152 | tmp = ldl_phys(cs->as, src); |
c73e3771 BH |
1153 | break; |
1154 | case 3: | |
2c17449b | 1155 | tmp = ldq_phys(cs->as, src); |
c73e3771 BH |
1156 | break; |
1157 | default: | |
1158 | return H_PARAMETER; | |
1159 | } | |
1160 | if (op == 1) { | |
1161 | tmp = ~tmp; | |
1162 | } | |
1163 | switch (esize) { | |
1164 | case 0: | |
db3be60d | 1165 | stb_phys(cs->as, dst, tmp); |
c73e3771 BH |
1166 | break; |
1167 | case 1: | |
5ce5944d | 1168 | stw_phys(cs->as, dst, tmp); |
c73e3771 BH |
1169 | break; |
1170 | case 2: | |
ab1da857 | 1171 | stl_phys(cs->as, dst, tmp); |
c73e3771 BH |
1172 | break; |
1173 | case 3: | |
f606604f | 1174 | stq_phys(cs->as, dst, tmp); |
c73e3771 BH |
1175 | break; |
1176 | } | |
1177 | dst = dst + step; | |
1178 | src = src + step; | |
1179 | } | |
1180 | ||
1181 | return H_SUCCESS; | |
1182 | } | |
1183 | ||
28e02042 | 1184 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
1185 | target_ulong opcode, target_ulong *args) |
1186 | { | |
1187 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
1188 | return H_SUCCESS; | |
1189 | } | |
1190 | ||
28e02042 | 1191 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
1192 | target_ulong opcode, target_ulong *args) |
1193 | { | |
1194 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
1195 | return H_SUCCESS; | |
1196 | } | |
1197 | ||
7d0cd464 PM |
1198 | static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, |
1199 | target_ulong mflags, | |
1200 | target_ulong value1, | |
1201 | target_ulong value2) | |
42561bf2 AB |
1202 | { |
1203 | CPUState *cs; | |
42561bf2 | 1204 | |
c4015bbd AK |
1205 | if (value1) { |
1206 | return H_P3; | |
1207 | } | |
1208 | if (value2) { | |
1209 | return H_P4; | |
1210 | } | |
1211 | ||
1212 | switch (mflags) { | |
1213 | case H_SET_MODE_ENDIAN_BIG: | |
1214 | CPU_FOREACH(cs) { | |
1215 | set_spr(cs, SPR_LPCR, 0, LPCR_ILE); | |
42561bf2 | 1216 | } |
eefaccc0 | 1217 | spapr_pci_switch_vga(true); |
c4015bbd AK |
1218 | return H_SUCCESS; |
1219 | ||
1220 | case H_SET_MODE_ENDIAN_LITTLE: | |
1221 | CPU_FOREACH(cs) { | |
1222 | set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); | |
42561bf2 | 1223 | } |
eefaccc0 | 1224 | spapr_pci_switch_vga(false); |
c4015bbd AK |
1225 | return H_SUCCESS; |
1226 | } | |
42561bf2 | 1227 | |
c4015bbd AK |
1228 | return H_UNSUPPORTED_FLAG; |
1229 | } | |
42561bf2 | 1230 | |
7d0cd464 PM |
1231 | static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, |
1232 | target_ulong mflags, | |
1233 | target_ulong value1, | |
1234 | target_ulong value2) | |
d5ac4f54 AK |
1235 | { |
1236 | CPUState *cs; | |
1237 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
d5ac4f54 AK |
1238 | |
1239 | if (!(pcc->insns_flags2 & PPC2_ISA207S)) { | |
1240 | return H_P2; | |
1241 | } | |
1242 | if (value1) { | |
1243 | return H_P3; | |
1244 | } | |
1245 | if (value2) { | |
1246 | return H_P4; | |
1247 | } | |
1248 | ||
5c94b2a5 | 1249 | if (mflags == AIL_RESERVED) { |
d5ac4f54 AK |
1250 | return H_UNSUPPORTED_FLAG; |
1251 | } | |
1252 | ||
1253 | CPU_FOREACH(cs) { | |
d5ac4f54 | 1254 | set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); |
d5ac4f54 AK |
1255 | } |
1256 | ||
1257 | return H_SUCCESS; | |
1258 | } | |
1259 | ||
28e02042 | 1260 | static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c4015bbd AK |
1261 | target_ulong opcode, target_ulong *args) |
1262 | { | |
1263 | target_ulong resource = args[1]; | |
1264 | target_ulong ret = H_P2; | |
1265 | ||
1266 | switch (resource) { | |
1267 | case H_SET_MODE_RESOURCE_LE: | |
7d0cd464 | 1268 | ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); |
c4015bbd | 1269 | break; |
d5ac4f54 | 1270 | case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: |
7d0cd464 PM |
1271 | ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], |
1272 | args[2], args[3]); | |
d5ac4f54 | 1273 | break; |
42561bf2 AB |
1274 | } |
1275 | ||
42561bf2 AB |
1276 | return ret; |
1277 | } | |
1278 | ||
d77a98b0 SJS |
1279 | static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
1280 | target_ulong opcode, target_ulong *args) | |
1281 | { | |
1282 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", | |
1283 | opcode, " (H_CLEAN_SLB)"); | |
1284 | return H_FUNCTION; | |
1285 | } | |
1286 | ||
1287 | static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, | |
1288 | target_ulong opcode, target_ulong *args) | |
1289 | { | |
1290 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", | |
1291 | opcode, " (H_INVALIDATE_PID)"); | |
1292 | return H_FUNCTION; | |
1293 | } | |
1294 | ||
b4db5413 SJS |
1295 | static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, |
1296 | uint64_t patbe_old, uint64_t patbe_new) | |
1297 | { | |
1298 | /* | |
1299 | * We have 4 Options: | |
1300 | * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing | |
1301 | * HASH->RADIX : Free HPT | |
1302 | * RADIX->HASH : Allocate HPT | |
1303 | * NOTHING->HASH : Allocate HPT | |
1304 | * Note: NOTHING implies the case where we said the guest could choose | |
1305 | * later and so assumed radix and now it's called H_REG_PROC_TBL | |
1306 | */ | |
1307 | ||
1308 | if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { | |
1309 | /* We assume RADIX, so this catches all the "Do Nothing" cases */ | |
1310 | } else if (!(patbe_old & PATBE1_GR)) { | |
1311 | /* HASH->RADIX : Free HPT */ | |
06ec79e8 | 1312 | spapr_free_hpt(spapr); |
b4db5413 SJS |
1313 | } else if (!(patbe_new & PATBE1_GR)) { |
1314 | /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ | |
1315 | spapr_setup_hpt_and_vrma(spapr); | |
1316 | } | |
1317 | return; | |
1318 | } | |
1319 | ||
1320 | #define FLAGS_MASK 0x01FULL | |
1321 | #define FLAG_MODIFY 0x10 | |
1322 | #define FLAG_REGISTER 0x08 | |
1323 | #define FLAG_RADIX 0x04 | |
1324 | #define FLAG_HASH_PROC_TBL 0x02 | |
1325 | #define FLAG_GTSE 0x01 | |
1326 | ||
d77a98b0 SJS |
1327 | static target_ulong h_register_process_table(PowerPCCPU *cpu, |
1328 | sPAPRMachineState *spapr, | |
1329 | target_ulong opcode, | |
1330 | target_ulong *args) | |
1331 | { | |
6de83307 | 1332 | CPUState *cs; |
b4db5413 SJS |
1333 | target_ulong flags = args[0]; |
1334 | target_ulong proc_tbl = args[1]; | |
1335 | target_ulong page_size = args[2]; | |
1336 | target_ulong table_size = args[3]; | |
1337 | uint64_t cproc; | |
1338 | ||
1339 | if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ | |
1340 | return H_PARAMETER; | |
1341 | } | |
1342 | if (flags & FLAG_MODIFY) { | |
1343 | if (flags & FLAG_REGISTER) { | |
1344 | if (flags & FLAG_RADIX) { /* Register new RADIX process table */ | |
1345 | if (proc_tbl & 0xfff || proc_tbl >> 60) { | |
1346 | return H_P2; | |
1347 | } else if (page_size) { | |
1348 | return H_P3; | |
1349 | } else if (table_size > 24) { | |
1350 | return H_P4; | |
1351 | } | |
1352 | cproc = PATBE1_GR | proc_tbl | table_size; | |
1353 | } else { /* Register new HPT process table */ | |
1354 | if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ | |
1355 | /* TODO - Not Supported */ | |
1356 | /* Technically caused by flag bits => H_PARAMETER */ | |
1357 | return H_PARAMETER; | |
1358 | } else { /* Hash with SLB */ | |
1359 | if (proc_tbl >> 38) { | |
1360 | return H_P2; | |
1361 | } else if (page_size & ~0x7) { | |
1362 | return H_P3; | |
1363 | } else if (table_size > 24) { | |
1364 | return H_P4; | |
1365 | } | |
1366 | } | |
1367 | cproc = (proc_tbl << 25) | page_size << 5 | table_size; | |
1368 | } | |
1369 | ||
1370 | } else { /* Deregister current process table */ | |
1371 | /* Set to benign value: (current GR) | 0. This allows | |
1372 | * deregistration in KVM to succeed even if the radix bit in flags | |
1373 | * doesn't match the radix bit in the old PATB. */ | |
1374 | cproc = spapr->patb_entry & PATBE1_GR; | |
1375 | } | |
1376 | } else { /* Maintain current registration */ | |
1377 | if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { | |
1378 | /* Technically caused by flag bits => H_PARAMETER */ | |
1379 | return H_PARAMETER; /* Existing Process Table Mismatch */ | |
1380 | } | |
1381 | cproc = spapr->patb_entry; | |
1382 | } | |
1383 | ||
1384 | /* Check if we need to setup OR free the hpt */ | |
1385 | spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); | |
1386 | ||
1387 | spapr->patb_entry = cproc; /* Save new process table */ | |
6de83307 SJS |
1388 | |
1389 | /* Update the UPRT and GTSE bits in the LPCR for all cpus */ | |
1390 | CPU_FOREACH(cs) { | |
60694bc6 | 1391 | set_spr(cs, SPR_LPCR, |
6de83307 | 1392 | ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | |
60694bc6 SJS |
1393 | ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), |
1394 | LPCR_UPRT | LPCR_GTSE); | |
b4db5413 SJS |
1395 | } |
1396 | ||
1397 | if (kvm_enabled()) { | |
1398 | return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, | |
1399 | flags & FLAG_GTSE, cproc); | |
1400 | } | |
1401 | return H_SUCCESS; | |
d77a98b0 SJS |
1402 | } |
1403 | ||
1c7ad77e NP |
1404 | #define H_SIGNAL_SYS_RESET_ALL -1 |
1405 | #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 | |
1406 | ||
1407 | static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, | |
1408 | sPAPRMachineState *spapr, | |
1409 | target_ulong opcode, target_ulong *args) | |
1410 | { | |
1411 | target_long target = args[0]; | |
1412 | CPUState *cs; | |
1413 | ||
1414 | if (target < 0) { | |
1415 | /* Broadcast */ | |
1416 | if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { | |
1417 | return H_PARAMETER; | |
1418 | } | |
1419 | ||
1420 | CPU_FOREACH(cs) { | |
1421 | PowerPCCPU *c = POWERPC_CPU(cs); | |
1422 | ||
1423 | if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { | |
1424 | if (c == cpu) { | |
1425 | continue; | |
1426 | } | |
1427 | } | |
1428 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); | |
1429 | } | |
1430 | return H_SUCCESS; | |
1431 | ||
1432 | } else { | |
1433 | /* Unicast */ | |
2e886fb3 | 1434 | cs = CPU(spapr_find_cpu(target)); |
f57467e3 SB |
1435 | if (cs) { |
1436 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); | |
1437 | return H_SUCCESS; | |
1c7ad77e NP |
1438 | } |
1439 | return H_PARAMETER; | |
1440 | } | |
1441 | } | |
1442 | ||
7843c0d6 | 1443 | static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, |
cc7b35b1 GK |
1444 | target_ulong *addr, bool *raw_mode_supported, |
1445 | Error **errp) | |
2a6593cb | 1446 | { |
152ef803 | 1447 | bool explicit_match = false; /* Matched the CPU's real PVR */ |
7843c0d6 | 1448 | uint32_t max_compat = spapr->max_compat_pvr; |
152ef803 DG |
1449 | uint32_t best_compat = 0; |
1450 | int i; | |
3794d548 | 1451 | |
152ef803 DG |
1452 | /* |
1453 | * We scan the supplied table of PVRs looking for two things | |
1454 | * 1. Is our real CPU PVR in the list? | |
1455 | * 2. What's the "best" listed logical PVR | |
1456 | */ | |
1457 | for (i = 0; i < 512; ++i) { | |
3794d548 AK |
1458 | uint32_t pvr, pvr_mask; |
1459 | ||
80c33d34 DG |
1460 | pvr_mask = ldl_be_phys(&address_space_memory, *addr); |
1461 | pvr = ldl_be_phys(&address_space_memory, *addr + 4); | |
1462 | *addr += 8; | |
152ef803 | 1463 | |
3794d548 | 1464 | if (~pvr_mask & pvr) { |
152ef803 | 1465 | break; /* Terminator record */ |
3794d548 | 1466 | } |
152ef803 DG |
1467 | |
1468 | if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { | |
1469 | explicit_match = true; | |
1470 | } else { | |
1471 | if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { | |
1472 | best_compat = pvr; | |
1473 | } | |
1474 | } | |
1475 | } | |
1476 | ||
1477 | if ((best_compat == 0) && (!explicit_match || max_compat)) { | |
1478 | /* We couldn't find a suitable compatibility mode, and either | |
1479 | * the guest doesn't support "raw" mode for this CPU, or raw | |
1480 | * mode is disabled because a maximum compat mode is set */ | |
80c33d34 DG |
1481 | error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); |
1482 | return 0; | |
3794d548 AK |
1483 | } |
1484 | ||
cc7b35b1 GK |
1485 | *raw_mode_supported = explicit_match; |
1486 | ||
3794d548 | 1487 | /* Parsing finished */ |
152ef803 | 1488 | trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); |
3794d548 | 1489 | |
80c33d34 DG |
1490 | return best_compat; |
1491 | } | |
3794d548 | 1492 | |
80c33d34 DG |
1493 | static target_ulong h_client_architecture_support(PowerPCCPU *cpu, |
1494 | sPAPRMachineState *spapr, | |
1495 | target_ulong opcode, | |
1496 | target_ulong *args) | |
1497 | { | |
1498 | /* Working address in data buffer */ | |
1499 | target_ulong addr = ppc64_phys_to_real(args[0]); | |
1500 | target_ulong ov_table; | |
1501 | uint32_t cas_pvr; | |
1502 | sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; | |
1503 | bool guest_radix; | |
1504 | Error *local_err = NULL; | |
cc7b35b1 | 1505 | bool raw_mode_supported = false; |
80c33d34 | 1506 | |
cc7b35b1 | 1507 | cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); |
80c33d34 DG |
1508 | if (local_err) { |
1509 | error_report_err(local_err); | |
1510 | return H_HARDWARE; | |
1511 | } | |
1512 | ||
1513 | /* Update CPUs */ | |
1514 | if (cpu->compat_pvr != cas_pvr) { | |
1515 | ppc_set_compat_all(cas_pvr, &local_err); | |
f6f242c7 | 1516 | if (local_err) { |
cc7b35b1 GK |
1517 | /* We fail to set compat mode (likely because running with KVM PR), |
1518 | * but maybe we can fallback to raw mode if the guest supports it. | |
1519 | */ | |
1520 | if (!raw_mode_supported) { | |
1521 | error_report_err(local_err); | |
1522 | return H_HARDWARE; | |
1523 | } | |
1524 | local_err = NULL; | |
3794d548 AK |
1525 | } |
1526 | } | |
1527 | ||
03d196b7 | 1528 | /* For the future use: here @ov_table points to the first option vector */ |
80c33d34 | 1529 | ov_table = addr; |
03d196b7 | 1530 | |
e957f6a9 | 1531 | ov1_guest = spapr_ovec_parse_vector(ov_table, 1); |
facdb8b6 | 1532 | ov5_guest = spapr_ovec_parse_vector(ov_table, 5); |
9fb4541f SB |
1533 | if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { |
1534 | error_report("guest requested hash and radix MMU, which is invalid."); | |
1535 | exit(EXIT_FAILURE); | |
1536 | } | |
1537 | /* The radix/hash bit in byte 24 requires special handling: */ | |
1538 | guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); | |
1539 | spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); | |
2a6593cb | 1540 | |
2772cf6b DG |
1541 | /* |
1542 | * HPT resizing is a bit of a special case, because when enabled | |
1543 | * we assume an HPT guest will support it until it says it | |
1544 | * doesn't, instead of assuming it won't support it until it says | |
1545 | * it does. Strictly speaking that approach could break for | |
1546 | * guests which don't make a CAS call, but those are so old we | |
1547 | * don't care about them. Without that assumption we'd have to | |
1548 | * make at least a temporary allocation of an HPT sized for max | |
1549 | * memory, which could be impossibly difficult under KVM HV if | |
1550 | * maxram is large. | |
1551 | */ | |
1552 | if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { | |
1553 | int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); | |
1554 | ||
1555 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { | |
1556 | error_report( | |
1557 | "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); | |
1558 | exit(1); | |
1559 | } | |
1560 | ||
1561 | if (spapr->htab_shift < maxshift) { | |
1562 | /* Guest doesn't know about HPT resizing, so we | |
1563 | * pre-emptively resize for the maximum permitted RAM. At | |
1564 | * the point this is called, nothing should have been | |
1565 | * entered into the existing HPT */ | |
1566 | spapr_reallocate_hpt(spapr, maxshift, &error_fatal); | |
4c563d9d GK |
1567 | if (kvm_enabled()) { |
1568 | /* For KVM PR, update the HPT pointer */ | |
1569 | target_ulong sdr1 = (target_ulong)(uintptr_t)spapr->htab | |
1570 | | (spapr->htab_shift - 18); | |
1571 | kvmppc_update_sdr1(sdr1); | |
b55d295e | 1572 | } |
2772cf6b DG |
1573 | } |
1574 | } | |
1575 | ||
facdb8b6 MR |
1576 | /* NOTE: there are actually a number of ov5 bits where input from the |
1577 | * guest is always zero, and the platform/QEMU enables them independently | |
1578 | * of guest input. To model these properly we'd want some sort of mask, | |
1579 | * but since they only currently apply to memory migration as defined | |
1580 | * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need | |
6787d27b | 1581 | * to worry about this for now. |
facdb8b6 | 1582 | */ |
6787d27b | 1583 | ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); |
30bf9ed1 CLG |
1584 | |
1585 | /* also clear the radix/hash bit from the current ov5_cas bits to | |
1586 | * be in sync with the newly ov5 bits. Else the radix bit will be | |
1587 | * seen as being removed and this will generate a reset loop | |
1588 | */ | |
1589 | spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); | |
1590 | ||
6787d27b | 1591 | /* full range of negotiated ov5 capabilities */ |
facdb8b6 MR |
1592 | spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); |
1593 | spapr_ovec_cleanup(ov5_guest); | |
6787d27b MR |
1594 | /* capabilities that have been added since CAS-generated guest reset. |
1595 | * if capabilities have since been removed, generate another reset | |
1596 | */ | |
1597 | ov5_updates = spapr_ovec_new(); | |
1598 | spapr->cas_reboot = spapr_ovec_diff(ov5_updates, | |
1599 | ov5_cas_old, spapr->ov5_cas); | |
9fb4541f SB |
1600 | /* Now that processing is finished, set the radix/hash bit for the |
1601 | * guest if it requested a valid mode; otherwise terminate the boot. */ | |
1602 | if (guest_radix) { | |
1603 | if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { | |
1604 | error_report("Guest requested unavailable MMU mode (radix)."); | |
1605 | exit(EXIT_FAILURE); | |
1606 | } | |
1607 | spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); | |
1608 | } else { | |
1609 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() | |
1610 | && !kvmppc_has_cap_mmu_hash_v3()) { | |
1611 | error_report("Guest requested unavailable MMU mode (hash)."); | |
1612 | exit(EXIT_FAILURE); | |
1613 | } | |
1614 | } | |
e957f6a9 SB |
1615 | spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, |
1616 | OV1_PPC_3_00); | |
6787d27b MR |
1617 | if (!spapr->cas_reboot) { |
1618 | spapr->cas_reboot = | |
5b120785 | 1619 | (spapr_h_cas_compose_response(spapr, args[1], args[2], |
6787d27b MR |
1620 | ov5_updates) != 0); |
1621 | } | |
1622 | spapr_ovec_cleanup(ov5_updates); | |
03d196b7 | 1623 | |
6787d27b | 1624 | if (spapr->cas_reboot) { |
cf83f140 | 1625 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
9fb4541f SB |
1626 | } else { |
1627 | /* If ppc_spapr_reset() did not set up a HPT but one is necessary | |
1628 | * (because the guest isn't going to use radix) then set it up here. */ | |
1629 | if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { | |
1630 | /* legacy hash or new hash: */ | |
1631 | spapr_setup_hpt_and_vrma(spapr); | |
1632 | } | |
2a6593cb AK |
1633 | } |
1634 | ||
1635 | return H_SUCCESS; | |
1636 | } | |
1637 | ||
7d7ba3fe DG |
1638 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
1639 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; | |
9fdf0c29 DG |
1640 | |
1641 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) | |
1642 | { | |
39ac8455 DG |
1643 | spapr_hcall_fn *slot; |
1644 | ||
1645 | if (opcode <= MAX_HCALL_OPCODE) { | |
1646 | assert((opcode & 0x3) == 0); | |
9fdf0c29 | 1647 | |
39ac8455 DG |
1648 | slot = &papr_hypercall_table[opcode / 4]; |
1649 | } else { | |
1650 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); | |
9fdf0c29 | 1651 | |
39ac8455 DG |
1652 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
1653 | } | |
9fdf0c29 | 1654 | |
c89d5299 | 1655 | assert(!(*slot)); |
39ac8455 | 1656 | *slot = fn; |
9fdf0c29 DG |
1657 | } |
1658 | ||
aa100fa4 | 1659 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
9fdf0c29 DG |
1660 | target_ulong *args) |
1661 | { | |
28e02042 DG |
1662 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
1663 | ||
9fdf0c29 DG |
1664 | if ((opcode <= MAX_HCALL_OPCODE) |
1665 | && ((opcode & 0x3) == 0)) { | |
39ac8455 DG |
1666 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
1667 | ||
1668 | if (fn) { | |
b13ce26d | 1669 | return fn(cpu, spapr, opcode, args); |
39ac8455 DG |
1670 | } |
1671 | } else if ((opcode >= KVMPPC_HCALL_BASE) && | |
1672 | (opcode <= KVMPPC_HCALL_MAX)) { | |
1673 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
1674 | |
1675 | if (fn) { | |
b13ce26d | 1676 | return fn(cpu, spapr, opcode, args); |
9fdf0c29 DG |
1677 | } |
1678 | } | |
1679 | ||
aaf87c66 TH |
1680 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", |
1681 | opcode); | |
9fdf0c29 DG |
1682 | return H_FUNCTION; |
1683 | } | |
f43e3525 | 1684 | |
83f7d43a | 1685 | static void hypercall_register_types(void) |
f43e3525 DG |
1686 | { |
1687 | /* hcall-pft */ | |
1688 | spapr_register_hypercall(H_ENTER, h_enter); | |
1689 | spapr_register_hypercall(H_REMOVE, h_remove); | |
1690 | spapr_register_hypercall(H_PROTECT, h_protect); | |
6bbd5dde | 1691 | spapr_register_hypercall(H_READ, h_read); |
39ac8455 | 1692 | |
a3d0abae DG |
1693 | /* hcall-bulk */ |
1694 | spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); | |
1695 | ||
30f4b05b DG |
1696 | /* hcall-hpt-resize */ |
1697 | spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); | |
1698 | spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); | |
1699 | ||
ed120055 DG |
1700 | /* hcall-splpar */ |
1701 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); | |
1702 | spapr_register_hypercall(H_CEDE, h_cede); | |
1c7ad77e | 1703 | spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); |
ed120055 | 1704 | |
423576f7 TH |
1705 | /* processor register resource access h-calls */ |
1706 | spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); | |
af08a58f | 1707 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
e49ff266 | 1708 | spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); |
3240dd9a | 1709 | spapr_register_hypercall(H_PAGE_INIT, h_page_init); |
423576f7 TH |
1710 | spapr_register_hypercall(H_SET_MODE, h_set_mode); |
1711 | ||
d77a98b0 SJS |
1712 | /* In Memory Table MMU h-calls */ |
1713 | spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); | |
1714 | spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); | |
1715 | spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); | |
1716 | ||
827200a2 DG |
1717 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate |
1718 | * here between the "CI" and the "CACHE" variants, they will use whatever | |
1719 | * mapping attributes qemu is using. When using KVM, the kernel will | |
1720 | * enforce the attributes more strongly | |
1721 | */ | |
1722 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); | |
1723 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); | |
1724 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); | |
1725 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); | |
1726 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); | |
1727 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); | |
c73e3771 | 1728 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
827200a2 | 1729 | |
39ac8455 DG |
1730 | /* qemu/KVM-PPC specific hcalls */ |
1731 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); | |
42561bf2 | 1732 | |
2a6593cb AK |
1733 | /* ibm,client-architecture-support support */ |
1734 | spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); | |
f43e3525 | 1735 | } |
83f7d43a AF |
1736 | |
1737 | type_init(hypercall_register_types) |