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Commit | Line | Data |
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0d75590d | 1 | #include "qemu/osdep.h" |
9c17d615 | 2 | #include "sysemu/sysemu.h" |
9fdf0c29 | 3 | #include "cpu.h" |
ed120055 | 4 | #include "helper_regs.h" |
0d09e41a | 5 | #include "hw/ppc/spapr.h" |
d5aea6f3 | 6 | #include "mmu-hash64.h" |
3794d548 AK |
7 | #include "cpu-models.h" |
8 | #include "trace.h" | |
9 | #include "kvm_ppc.h" | |
f43e3525 | 10 | |
a46622fd AK |
11 | struct SPRSyncState { |
12 | CPUState *cs; | |
13 | int spr; | |
14 | target_ulong value; | |
15 | target_ulong mask; | |
16 | }; | |
17 | ||
18 | static void do_spr_sync(void *arg) | |
19 | { | |
20 | struct SPRSyncState *s = arg; | |
21 | PowerPCCPU *cpu = POWERPC_CPU(s->cs); | |
22 | CPUPPCState *env = &cpu->env; | |
23 | ||
24 | cpu_synchronize_state(s->cs); | |
25 | env->spr[s->spr] &= ~s->mask; | |
26 | env->spr[s->spr] |= s->value; | |
27 | } | |
28 | ||
29 | static void set_spr(CPUState *cs, int spr, target_ulong value, | |
30 | target_ulong mask) | |
31 | { | |
32 | struct SPRSyncState s = { | |
33 | .cs = cs, | |
34 | .spr = spr, | |
35 | .value = value, | |
36 | .mask = mask | |
37 | }; | |
38 | run_on_cpu(cs, do_spr_sync, &s); | |
39 | } | |
40 | ||
f43e3525 DG |
41 | static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, |
42 | target_ulong pte_index) | |
43 | { | |
44 | target_ulong rb, va_low; | |
45 | ||
46 | rb = (v & ~0x7fULL) << 16; /* AVA field */ | |
47 | va_low = pte_index >> 3; | |
d5aea6f3 | 48 | if (v & HPTE64_V_SECONDARY) { |
f43e3525 DG |
49 | va_low = ~va_low; |
50 | } | |
51 | /* xor vsid from AVA */ | |
d5aea6f3 | 52 | if (!(v & HPTE64_V_1TB_SEG)) { |
f43e3525 DG |
53 | va_low ^= v >> 12; |
54 | } else { | |
55 | va_low ^= v >> 24; | |
56 | } | |
57 | va_low &= 0x7ff; | |
d5aea6f3 | 58 | if (v & HPTE64_V_LARGE) { |
f43e3525 DG |
59 | rb |= 1; /* L field */ |
60 | #if 0 /* Disable that P7 specific bit for now */ | |
61 | if (r & 0xff000) { | |
62 | /* non-16MB large page, must be 64k */ | |
63 | /* (masks depend on page size) */ | |
64 | rb |= 0x1000; /* page encoding in LP field */ | |
65 | rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */ | |
66 | rb |= (va_low & 0xfe); /* AVAL field */ | |
67 | } | |
68 | #endif | |
69 | } else { | |
70 | /* 4kB page */ | |
71 | rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ | |
72 | } | |
73 | rb |= (v >> 54) & 0x300; /* B field */ | |
74 | return rb; | |
75 | } | |
76 | ||
f3c75d42 AK |
77 | static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index) |
78 | { | |
79 | /* | |
80 | * hash value/pteg group index is normalized by htab_mask | |
81 | */ | |
82 | if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) { | |
83 | return false; | |
84 | } | |
85 | return true; | |
86 | } | |
87 | ||
ecbc25fa DG |
88 | static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) |
89 | { | |
90 | MachineState *machine = MACHINE(spapr); | |
91 | MemoryHotplugState *hpms = &spapr->hotplug_memory; | |
92 | ||
93 | if (addr < machine->ram_size) { | |
94 | return true; | |
95 | } | |
96 | if ((addr >= hpms->base) | |
97 | && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { | |
98 | return true; | |
99 | } | |
100 | ||
101 | return false; | |
102 | } | |
103 | ||
28e02042 | 104 | static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
f43e3525 DG |
105 | target_ulong opcode, target_ulong *args) |
106 | { | |
b13ce26d | 107 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
108 | target_ulong flags = args[0]; |
109 | target_ulong pte_index = args[1]; | |
110 | target_ulong pteh = args[2]; | |
111 | target_ulong ptel = args[3]; | |
f73a2575 DG |
112 | target_ulong page_shift = 12; |
113 | target_ulong raddr; | |
7c43bca0 | 114 | target_ulong index; |
7c43bca0 | 115 | uint64_t token; |
f43e3525 DG |
116 | |
117 | /* only handle 4k and 16M pages for now */ | |
d5aea6f3 | 118 | if (pteh & HPTE64_V_LARGE) { |
f43e3525 DG |
119 | #if 0 /* We don't support 64k pages yet */ |
120 | if ((ptel & 0xf000) == 0x1000) { | |
121 | /* 64k page */ | |
f43e3525 DG |
122 | } else |
123 | #endif | |
124 | if ((ptel & 0xff000) == 0) { | |
125 | /* 16M page */ | |
f73a2575 | 126 | page_shift = 24; |
f43e3525 DG |
127 | /* lowest AVA bit must be 0 for 16M pages */ |
128 | if (pteh & 0x80) { | |
129 | return H_PARAMETER; | |
130 | } | |
131 | } else { | |
132 | return H_PARAMETER; | |
133 | } | |
134 | } | |
135 | ||
d5aea6f3 | 136 | raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1); |
f43e3525 | 137 | |
ecbc25fa | 138 | if (is_ram_address(spapr, raddr)) { |
f73a2575 | 139 | /* Regular RAM - should have WIMG=0010 */ |
d5aea6f3 | 140 | if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { |
f73a2575 DG |
141 | return H_PARAMETER; |
142 | } | |
143 | } else { | |
144 | /* Looks like an IO address */ | |
145 | /* FIXME: What WIMG combinations could be sensible for IO? | |
146 | * For now we allow WIMG=010x, but are there others? */ | |
147 | /* FIXME: Should we check against registered IO addresses? */ | |
d5aea6f3 | 148 | if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) { |
f73a2575 DG |
149 | return H_PARAMETER; |
150 | } | |
f43e3525 | 151 | } |
f73a2575 | 152 | |
f43e3525 DG |
153 | pteh &= ~0x60ULL; |
154 | ||
f3c75d42 | 155 | if (!valid_pte_index(env, pte_index)) { |
f43e3525 DG |
156 | return H_PARAMETER; |
157 | } | |
7c43bca0 AK |
158 | |
159 | index = 0; | |
f43e3525 DG |
160 | if (likely((flags & H_EXACT) == 0)) { |
161 | pte_index &= ~7ULL; | |
7c43bca0 | 162 | token = ppc_hash64_start_access(cpu, pte_index); |
7aaf4957 | 163 | for (; index < 8; index++) { |
7ef23068 | 164 | if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALID)) { |
f43e3525 DG |
165 | break; |
166 | } | |
7aaf4957 | 167 | } |
7c43bca0 | 168 | ppc_hash64_stop_access(token); |
7aaf4957 AK |
169 | if (index == 8) { |
170 | return H_PTEG_FULL; | |
171 | } | |
f43e3525 | 172 | } else { |
7c43bca0 | 173 | token = ppc_hash64_start_access(cpu, pte_index); |
7ef23068 | 174 | if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) { |
7c43bca0 | 175 | ppc_hash64_stop_access(token); |
f43e3525 DG |
176 | return H_PTEG_FULL; |
177 | } | |
7c43bca0 | 178 | ppc_hash64_stop_access(token); |
f43e3525 | 179 | } |
7c43bca0 | 180 | |
7ef23068 | 181 | ppc_hash64_store_hpte(cpu, pte_index + index, |
3f94170b | 182 | pteh | HPTE64_V_HPTE_DIRTY, ptel); |
f43e3525 | 183 | |
7c43bca0 | 184 | args[0] = pte_index + index; |
f43e3525 DG |
185 | return H_SUCCESS; |
186 | } | |
187 | ||
a3801402 | 188 | typedef enum { |
a3d0abae DG |
189 | REMOVE_SUCCESS = 0, |
190 | REMOVE_NOT_FOUND = 1, | |
191 | REMOVE_PARM = 2, | |
192 | REMOVE_HW = 3, | |
a3801402 | 193 | } RemoveResult; |
a3d0abae | 194 | |
7ef23068 | 195 | static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, |
a3d0abae DG |
196 | target_ulong avpn, |
197 | target_ulong flags, | |
198 | target_ulong *vp, target_ulong *rp) | |
f43e3525 | 199 | { |
7ef23068 | 200 | CPUPPCState *env = &cpu->env; |
7c43bca0 | 201 | uint64_t token; |
f43e3525 DG |
202 | target_ulong v, r, rb; |
203 | ||
f3c75d42 | 204 | if (!valid_pte_index(env, ptex)) { |
a3d0abae | 205 | return REMOVE_PARM; |
f43e3525 DG |
206 | } |
207 | ||
7ef23068 DG |
208 | token = ppc_hash64_start_access(cpu, ptex); |
209 | v = ppc_hash64_load_hpte0(cpu, token, 0); | |
210 | r = ppc_hash64_load_hpte1(cpu, token, 0); | |
7c43bca0 | 211 | ppc_hash64_stop_access(token); |
f43e3525 | 212 | |
d5aea6f3 | 213 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 DG |
214 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || |
215 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { | |
a3d0abae | 216 | return REMOVE_NOT_FOUND; |
f43e3525 | 217 | } |
35f9304d | 218 | *vp = v; |
a3d0abae | 219 | *rp = r; |
7ef23068 | 220 | ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); |
a3d0abae | 221 | rb = compute_tlbie_rb(v, r, ptex); |
f43e3525 | 222 | ppc_tlb_invalidate_one(env, rb); |
a3d0abae DG |
223 | return REMOVE_SUCCESS; |
224 | } | |
225 | ||
28e02042 | 226 | static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a3d0abae DG |
227 | target_ulong opcode, target_ulong *args) |
228 | { | |
229 | target_ulong flags = args[0]; | |
230 | target_ulong pte_index = args[1]; | |
231 | target_ulong avpn = args[2]; | |
a3801402 | 232 | RemoveResult ret; |
a3d0abae | 233 | |
7ef23068 | 234 | ret = remove_hpte(cpu, pte_index, avpn, flags, |
a3d0abae DG |
235 | &args[0], &args[1]); |
236 | ||
237 | switch (ret) { | |
238 | case REMOVE_SUCCESS: | |
239 | return H_SUCCESS; | |
240 | ||
241 | case REMOVE_NOT_FOUND: | |
242 | return H_NOT_FOUND; | |
243 | ||
244 | case REMOVE_PARM: | |
245 | return H_PARAMETER; | |
246 | ||
247 | case REMOVE_HW: | |
248 | return H_HARDWARE; | |
249 | } | |
250 | ||
9a39970d | 251 | g_assert_not_reached(); |
a3d0abae DG |
252 | } |
253 | ||
254 | #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL | |
255 | #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL | |
256 | #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL | |
257 | #define H_BULK_REMOVE_END 0xc000000000000000ULL | |
258 | #define H_BULK_REMOVE_CODE 0x3000000000000000ULL | |
259 | #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL | |
260 | #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL | |
261 | #define H_BULK_REMOVE_PARM 0x2000000000000000ULL | |
262 | #define H_BULK_REMOVE_HW 0x3000000000000000ULL | |
263 | #define H_BULK_REMOVE_RC 0x0c00000000000000ULL | |
264 | #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL | |
265 | #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL | |
266 | #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL | |
267 | #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL | |
268 | #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL | |
269 | ||
270 | #define H_BULK_REMOVE_MAX_BATCH 4 | |
271 | ||
28e02042 | 272 | static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a3d0abae DG |
273 | target_ulong opcode, target_ulong *args) |
274 | { | |
275 | int i; | |
276 | ||
277 | for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { | |
278 | target_ulong *tsh = &args[i*2]; | |
279 | target_ulong tsl = args[i*2 + 1]; | |
280 | target_ulong v, r, ret; | |
281 | ||
282 | if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { | |
283 | break; | |
284 | } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { | |
285 | return H_PARAMETER; | |
286 | } | |
287 | ||
288 | *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; | |
289 | *tsh |= H_BULK_REMOVE_RESPONSE; | |
290 | ||
291 | if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { | |
292 | *tsh |= H_BULK_REMOVE_PARM; | |
293 | return H_PARAMETER; | |
294 | } | |
295 | ||
7ef23068 | 296 | ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, |
a3d0abae DG |
297 | (*tsh & H_BULK_REMOVE_FLAGS) >> 26, |
298 | &v, &r); | |
299 | ||
300 | *tsh |= ret << 60; | |
301 | ||
302 | switch (ret) { | |
303 | case REMOVE_SUCCESS: | |
d5aea6f3 | 304 | *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; |
a3d0abae DG |
305 | break; |
306 | ||
307 | case REMOVE_PARM: | |
308 | return H_PARAMETER; | |
309 | ||
310 | case REMOVE_HW: | |
311 | return H_HARDWARE; | |
312 | } | |
313 | } | |
314 | ||
f43e3525 DG |
315 | return H_SUCCESS; |
316 | } | |
317 | ||
28e02042 | 318 | static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
f43e3525 DG |
319 | target_ulong opcode, target_ulong *args) |
320 | { | |
b13ce26d | 321 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
322 | target_ulong flags = args[0]; |
323 | target_ulong pte_index = args[1]; | |
324 | target_ulong avpn = args[2]; | |
7c43bca0 | 325 | uint64_t token; |
f43e3525 DG |
326 | target_ulong v, r, rb; |
327 | ||
f3c75d42 | 328 | if (!valid_pte_index(env, pte_index)) { |
f43e3525 DG |
329 | return H_PARAMETER; |
330 | } | |
331 | ||
7c43bca0 | 332 | token = ppc_hash64_start_access(cpu, pte_index); |
7ef23068 DG |
333 | v = ppc_hash64_load_hpte0(cpu, token, 0); |
334 | r = ppc_hash64_load_hpte1(cpu, token, 0); | |
7c43bca0 | 335 | ppc_hash64_stop_access(token); |
f43e3525 | 336 | |
d5aea6f3 | 337 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 | 338 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { |
f43e3525 DG |
339 | return H_NOT_FOUND; |
340 | } | |
341 | ||
d5aea6f3 DG |
342 | r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | |
343 | HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); | |
344 | r |= (flags << 55) & HPTE64_R_PP0; | |
345 | r |= (flags << 48) & HPTE64_R_KEY_HI; | |
346 | r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); | |
f43e3525 | 347 | rb = compute_tlbie_rb(v, r, pte_index); |
7ef23068 | 348 | ppc_hash64_store_hpte(cpu, pte_index, |
3f94170b | 349 | (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); |
f43e3525 | 350 | ppc_tlb_invalidate_one(env, rb); |
f43e3525 | 351 | /* Don't need a memory barrier, due to qemu's global lock */ |
7ef23068 | 352 | ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r); |
f43e3525 DG |
353 | return H_SUCCESS; |
354 | } | |
355 | ||
28e02042 | 356 | static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
6bbd5dde EC |
357 | target_ulong opcode, target_ulong *args) |
358 | { | |
359 | CPUPPCState *env = &cpu->env; | |
360 | target_ulong flags = args[0]; | |
361 | target_ulong pte_index = args[1]; | |
362 | uint8_t *hpte; | |
363 | int i, ridx, n_entries = 1; | |
364 | ||
f3c75d42 | 365 | if (!valid_pte_index(env, pte_index)) { |
6bbd5dde EC |
366 | return H_PARAMETER; |
367 | } | |
368 | ||
369 | if (flags & H_READ_4) { | |
370 | /* Clear the two low order bits */ | |
371 | pte_index &= ~(3ULL); | |
372 | n_entries = 4; | |
373 | } | |
374 | ||
375 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
376 | ||
377 | for (i = 0, ridx = 0; i < n_entries; i++) { | |
378 | args[ridx++] = ldq_p(hpte); | |
379 | args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
380 | hpte += HASH_PTE_SIZE_64; | |
381 | } | |
382 | ||
383 | return H_SUCCESS; | |
384 | } | |
385 | ||
28e02042 | 386 | static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
821303f5 DG |
387 | target_ulong opcode, target_ulong *args) |
388 | { | |
389 | /* FIXME: actually implement this */ | |
390 | return H_HARDWARE; | |
391 | } | |
392 | ||
ed120055 DG |
393 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
394 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL | |
395 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL | |
396 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL | |
397 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL | |
398 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL | |
399 | ||
400 | #define VPA_MIN_SIZE 640 | |
401 | #define VPA_SIZE_OFFSET 0x4 | |
402 | #define VPA_SHARED_PROC_OFFSET 0x9 | |
403 | #define VPA_SHARED_PROC_VAL 0x2 | |
404 | ||
e2684c0b | 405 | static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 406 | { |
33276f1b | 407 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
408 | uint16_t size; |
409 | uint8_t tmp; | |
410 | ||
411 | if (vpa == 0) { | |
412 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); | |
413 | return H_HARDWARE; | |
414 | } | |
415 | ||
416 | if (vpa % env->dcache_line_size) { | |
417 | return H_PARAMETER; | |
418 | } | |
419 | /* FIXME: bounds check the address */ | |
420 | ||
41701aa4 | 421 | size = lduw_be_phys(cs->as, vpa + 0x4); |
ed120055 DG |
422 | |
423 | if (size < VPA_MIN_SIZE) { | |
424 | return H_PARAMETER; | |
425 | } | |
426 | ||
427 | /* VPA is not allowed to cross a page boundary */ | |
428 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { | |
429 | return H_PARAMETER; | |
430 | } | |
431 | ||
1bfb37d1 | 432 | env->vpa_addr = vpa; |
ed120055 | 433 | |
2c17449b | 434 | tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
ed120055 | 435 | tmp |= VPA_SHARED_PROC_VAL; |
db3be60d | 436 | stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
ed120055 DG |
437 | |
438 | return H_SUCCESS; | |
439 | } | |
440 | ||
e2684c0b | 441 | static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 442 | { |
1bfb37d1 | 443 | if (env->slb_shadow_addr) { |
ed120055 DG |
444 | return H_RESOURCE; |
445 | } | |
446 | ||
1bfb37d1 | 447 | if (env->dtl_addr) { |
ed120055 DG |
448 | return H_RESOURCE; |
449 | } | |
450 | ||
1bfb37d1 | 451 | env->vpa_addr = 0; |
ed120055 DG |
452 | return H_SUCCESS; |
453 | } | |
454 | ||
e2684c0b | 455 | static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 456 | { |
33276f1b | 457 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
458 | uint32_t size; |
459 | ||
460 | if (addr == 0) { | |
461 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); | |
462 | return H_HARDWARE; | |
463 | } | |
464 | ||
fdfba1a2 | 465 | size = ldl_be_phys(cs->as, addr + 0x4); |
ed120055 DG |
466 | if (size < 0x8) { |
467 | return H_PARAMETER; | |
468 | } | |
469 | ||
470 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { | |
471 | return H_PARAMETER; | |
472 | } | |
473 | ||
1bfb37d1 | 474 | if (!env->vpa_addr) { |
ed120055 DG |
475 | return H_RESOURCE; |
476 | } | |
477 | ||
1bfb37d1 DG |
478 | env->slb_shadow_addr = addr; |
479 | env->slb_shadow_size = size; | |
ed120055 DG |
480 | |
481 | return H_SUCCESS; | |
482 | } | |
483 | ||
e2684c0b | 484 | static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 485 | { |
1bfb37d1 DG |
486 | env->slb_shadow_addr = 0; |
487 | env->slb_shadow_size = 0; | |
ed120055 DG |
488 | return H_SUCCESS; |
489 | } | |
490 | ||
e2684c0b | 491 | static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 492 | { |
33276f1b | 493 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
494 | uint32_t size; |
495 | ||
496 | if (addr == 0) { | |
497 | hcall_dprintf("Can't cope with DTL at logical 0\n"); | |
498 | return H_HARDWARE; | |
499 | } | |
500 | ||
fdfba1a2 | 501 | size = ldl_be_phys(cs->as, addr + 0x4); |
ed120055 DG |
502 | |
503 | if (size < 48) { | |
504 | return H_PARAMETER; | |
505 | } | |
506 | ||
1bfb37d1 | 507 | if (!env->vpa_addr) { |
ed120055 DG |
508 | return H_RESOURCE; |
509 | } | |
510 | ||
1bfb37d1 | 511 | env->dtl_addr = addr; |
ed120055 DG |
512 | env->dtl_size = size; |
513 | ||
514 | return H_SUCCESS; | |
515 | } | |
516 | ||
73f7821b | 517 | static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 518 | { |
1bfb37d1 | 519 | env->dtl_addr = 0; |
ed120055 DG |
520 | env->dtl_size = 0; |
521 | ||
522 | return H_SUCCESS; | |
523 | } | |
524 | ||
28e02042 | 525 | static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ed120055 DG |
526 | target_ulong opcode, target_ulong *args) |
527 | { | |
528 | target_ulong flags = args[0]; | |
529 | target_ulong procno = args[1]; | |
530 | target_ulong vpa = args[2]; | |
531 | target_ulong ret = H_PARAMETER; | |
e2684c0b | 532 | CPUPPCState *tenv; |
0f20ba62 | 533 | PowerPCCPU *tcpu; |
ed120055 | 534 | |
0f20ba62 | 535 | tcpu = ppc_get_vcpu_by_dt_id(procno); |
5353d03d | 536 | if (!tcpu) { |
ed120055 DG |
537 | return H_PARAMETER; |
538 | } | |
0f20ba62 | 539 | tenv = &tcpu->env; |
ed120055 DG |
540 | |
541 | switch (flags) { | |
542 | case FLAGS_REGISTER_VPA: | |
543 | ret = register_vpa(tenv, vpa); | |
544 | break; | |
545 | ||
546 | case FLAGS_DEREGISTER_VPA: | |
547 | ret = deregister_vpa(tenv, vpa); | |
548 | break; | |
549 | ||
550 | case FLAGS_REGISTER_SLBSHADOW: | |
551 | ret = register_slb_shadow(tenv, vpa); | |
552 | break; | |
553 | ||
554 | case FLAGS_DEREGISTER_SLBSHADOW: | |
555 | ret = deregister_slb_shadow(tenv, vpa); | |
556 | break; | |
557 | ||
558 | case FLAGS_REGISTER_DTL: | |
559 | ret = register_dtl(tenv, vpa); | |
560 | break; | |
561 | ||
562 | case FLAGS_DEREGISTER_DTL: | |
563 | ret = deregister_dtl(tenv, vpa); | |
564 | break; | |
565 | } | |
566 | ||
567 | return ret; | |
568 | } | |
569 | ||
28e02042 | 570 | static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ed120055 DG |
571 | target_ulong opcode, target_ulong *args) |
572 | { | |
b13ce26d | 573 | CPUPPCState *env = &cpu->env; |
fcd7d003 | 574 | CPUState *cs = CPU(cpu); |
b13ce26d | 575 | |
ed120055 DG |
576 | env->msr |= (1ULL << MSR_EE); |
577 | hreg_compute_hflags(env); | |
fcd7d003 | 578 | if (!cpu_has_work(cs)) { |
259186a7 | 579 | cs->halted = 1; |
27103424 | 580 | cs->exception_index = EXCP_HLT; |
fcd7d003 | 581 | cs->exit_request = 1; |
ed120055 DG |
582 | } |
583 | return H_SUCCESS; | |
584 | } | |
585 | ||
28e02042 | 586 | static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
39ac8455 DG |
587 | target_ulong opcode, target_ulong *args) |
588 | { | |
589 | target_ulong rtas_r3 = args[0]; | |
4fe822e0 AK |
590 | uint32_t token = rtas_ld(rtas_r3, 0); |
591 | uint32_t nargs = rtas_ld(rtas_r3, 1); | |
592 | uint32_t nret = rtas_ld(rtas_r3, 2); | |
39ac8455 | 593 | |
210b580b | 594 | return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, |
39ac8455 DG |
595 | nret, rtas_r3 + 12 + 4*nargs); |
596 | } | |
597 | ||
28e02042 | 598 | static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
599 | target_ulong opcode, target_ulong *args) |
600 | { | |
fdfba1a2 | 601 | CPUState *cs = CPU(cpu); |
827200a2 DG |
602 | target_ulong size = args[0]; |
603 | target_ulong addr = args[1]; | |
604 | ||
605 | switch (size) { | |
606 | case 1: | |
2c17449b | 607 | args[0] = ldub_phys(cs->as, addr); |
827200a2 DG |
608 | return H_SUCCESS; |
609 | case 2: | |
41701aa4 | 610 | args[0] = lduw_phys(cs->as, addr); |
827200a2 DG |
611 | return H_SUCCESS; |
612 | case 4: | |
fdfba1a2 | 613 | args[0] = ldl_phys(cs->as, addr); |
827200a2 DG |
614 | return H_SUCCESS; |
615 | case 8: | |
2c17449b | 616 | args[0] = ldq_phys(cs->as, addr); |
827200a2 DG |
617 | return H_SUCCESS; |
618 | } | |
619 | return H_PARAMETER; | |
620 | } | |
621 | ||
28e02042 | 622 | static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
623 | target_ulong opcode, target_ulong *args) |
624 | { | |
f606604f EI |
625 | CPUState *cs = CPU(cpu); |
626 | ||
827200a2 DG |
627 | target_ulong size = args[0]; |
628 | target_ulong addr = args[1]; | |
629 | target_ulong val = args[2]; | |
630 | ||
631 | switch (size) { | |
632 | case 1: | |
db3be60d | 633 | stb_phys(cs->as, addr, val); |
827200a2 DG |
634 | return H_SUCCESS; |
635 | case 2: | |
5ce5944d | 636 | stw_phys(cs->as, addr, val); |
827200a2 DG |
637 | return H_SUCCESS; |
638 | case 4: | |
ab1da857 | 639 | stl_phys(cs->as, addr, val); |
827200a2 DG |
640 | return H_SUCCESS; |
641 | case 8: | |
f606604f | 642 | stq_phys(cs->as, addr, val); |
827200a2 DG |
643 | return H_SUCCESS; |
644 | } | |
645 | return H_PARAMETER; | |
646 | } | |
647 | ||
28e02042 | 648 | static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c73e3771 BH |
649 | target_ulong opcode, target_ulong *args) |
650 | { | |
fdfba1a2 EI |
651 | CPUState *cs = CPU(cpu); |
652 | ||
c73e3771 BH |
653 | target_ulong dst = args[0]; /* Destination address */ |
654 | target_ulong src = args[1]; /* Source address */ | |
655 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ | |
656 | target_ulong count = args[3]; /* Element count */ | |
657 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ | |
658 | uint64_t tmp; | |
659 | unsigned int mask = (1 << esize) - 1; | |
660 | int step = 1 << esize; | |
661 | ||
662 | if (count > 0x80000000) { | |
663 | return H_PARAMETER; | |
664 | } | |
665 | ||
666 | if ((dst & mask) || (src & mask) || (op > 1)) { | |
667 | return H_PARAMETER; | |
668 | } | |
669 | ||
670 | if (dst >= src && dst < (src + (count << esize))) { | |
671 | dst = dst + ((count - 1) << esize); | |
672 | src = src + ((count - 1) << esize); | |
673 | step = -step; | |
674 | } | |
675 | ||
676 | while (count--) { | |
677 | switch (esize) { | |
678 | case 0: | |
2c17449b | 679 | tmp = ldub_phys(cs->as, src); |
c73e3771 BH |
680 | break; |
681 | case 1: | |
41701aa4 | 682 | tmp = lduw_phys(cs->as, src); |
c73e3771 BH |
683 | break; |
684 | case 2: | |
fdfba1a2 | 685 | tmp = ldl_phys(cs->as, src); |
c73e3771 BH |
686 | break; |
687 | case 3: | |
2c17449b | 688 | tmp = ldq_phys(cs->as, src); |
c73e3771 BH |
689 | break; |
690 | default: | |
691 | return H_PARAMETER; | |
692 | } | |
693 | if (op == 1) { | |
694 | tmp = ~tmp; | |
695 | } | |
696 | switch (esize) { | |
697 | case 0: | |
db3be60d | 698 | stb_phys(cs->as, dst, tmp); |
c73e3771 BH |
699 | break; |
700 | case 1: | |
5ce5944d | 701 | stw_phys(cs->as, dst, tmp); |
c73e3771 BH |
702 | break; |
703 | case 2: | |
ab1da857 | 704 | stl_phys(cs->as, dst, tmp); |
c73e3771 BH |
705 | break; |
706 | case 3: | |
f606604f | 707 | stq_phys(cs->as, dst, tmp); |
c73e3771 BH |
708 | break; |
709 | } | |
710 | dst = dst + step; | |
711 | src = src + step; | |
712 | } | |
713 | ||
714 | return H_SUCCESS; | |
715 | } | |
716 | ||
28e02042 | 717 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
718 | target_ulong opcode, target_ulong *args) |
719 | { | |
720 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
721 | return H_SUCCESS; | |
722 | } | |
723 | ||
28e02042 | 724 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
725 | target_ulong opcode, target_ulong *args) |
726 | { | |
727 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
728 | return H_SUCCESS; | |
729 | } | |
730 | ||
7d0cd464 PM |
731 | static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, |
732 | target_ulong mflags, | |
733 | target_ulong value1, | |
734 | target_ulong value2) | |
42561bf2 AB |
735 | { |
736 | CPUState *cs; | |
42561bf2 | 737 | |
c4015bbd AK |
738 | if (value1) { |
739 | return H_P3; | |
740 | } | |
741 | if (value2) { | |
742 | return H_P4; | |
743 | } | |
744 | ||
745 | switch (mflags) { | |
746 | case H_SET_MODE_ENDIAN_BIG: | |
747 | CPU_FOREACH(cs) { | |
748 | set_spr(cs, SPR_LPCR, 0, LPCR_ILE); | |
42561bf2 | 749 | } |
eefaccc0 | 750 | spapr_pci_switch_vga(true); |
c4015bbd AK |
751 | return H_SUCCESS; |
752 | ||
753 | case H_SET_MODE_ENDIAN_LITTLE: | |
754 | CPU_FOREACH(cs) { | |
755 | set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); | |
42561bf2 | 756 | } |
eefaccc0 | 757 | spapr_pci_switch_vga(false); |
c4015bbd AK |
758 | return H_SUCCESS; |
759 | } | |
42561bf2 | 760 | |
c4015bbd AK |
761 | return H_UNSUPPORTED_FLAG; |
762 | } | |
42561bf2 | 763 | |
7d0cd464 PM |
764 | static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, |
765 | target_ulong mflags, | |
766 | target_ulong value1, | |
767 | target_ulong value2) | |
d5ac4f54 AK |
768 | { |
769 | CPUState *cs; | |
770 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
771 | target_ulong prefix; | |
772 | ||
773 | if (!(pcc->insns_flags2 & PPC2_ISA207S)) { | |
774 | return H_P2; | |
775 | } | |
776 | if (value1) { | |
777 | return H_P3; | |
778 | } | |
779 | if (value2) { | |
780 | return H_P4; | |
781 | } | |
782 | ||
783 | switch (mflags) { | |
784 | case H_SET_MODE_ADDR_TRANS_NONE: | |
785 | prefix = 0; | |
786 | break; | |
787 | case H_SET_MODE_ADDR_TRANS_0001_8000: | |
788 | prefix = 0x18000; | |
789 | break; | |
790 | case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000: | |
b653282e | 791 | prefix = 0xC000000000004000ULL; |
d5ac4f54 AK |
792 | break; |
793 | default: | |
794 | return H_UNSUPPORTED_FLAG; | |
795 | } | |
796 | ||
797 | CPU_FOREACH(cs) { | |
798 | CPUPPCState *env = &POWERPC_CPU(cpu)->env; | |
799 | ||
800 | set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); | |
801 | env->excp_prefix = prefix; | |
802 | } | |
803 | ||
804 | return H_SUCCESS; | |
805 | } | |
806 | ||
28e02042 | 807 | static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c4015bbd AK |
808 | target_ulong opcode, target_ulong *args) |
809 | { | |
810 | target_ulong resource = args[1]; | |
811 | target_ulong ret = H_P2; | |
812 | ||
813 | switch (resource) { | |
814 | case H_SET_MODE_RESOURCE_LE: | |
7d0cd464 | 815 | ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); |
c4015bbd | 816 | break; |
d5ac4f54 | 817 | case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: |
7d0cd464 PM |
818 | ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], |
819 | args[2], args[3]); | |
d5ac4f54 | 820 | break; |
42561bf2 AB |
821 | } |
822 | ||
42561bf2 AB |
823 | return ret; |
824 | } | |
825 | ||
03d196b7 BR |
826 | /* |
827 | * Return the offset to the requested option vector @vector in the | |
828 | * option vector table @table. | |
829 | */ | |
830 | static target_ulong cas_get_option_vector(int vector, target_ulong table) | |
831 | { | |
832 | int i; | |
833 | char nr_vectors, nr_entries; | |
834 | ||
835 | if (!table) { | |
836 | return 0; | |
837 | } | |
838 | ||
839 | nr_vectors = (ldl_phys(&address_space_memory, table) >> 24) + 1; | |
840 | if (!vector || vector > nr_vectors) { | |
841 | return 0; | |
842 | } | |
843 | table++; /* skip nr option vectors */ | |
844 | ||
845 | for (i = 0; i < vector - 1; i++) { | |
846 | nr_entries = ldl_phys(&address_space_memory, table) >> 24; | |
847 | table += nr_entries + 2; | |
848 | } | |
849 | return table; | |
850 | } | |
851 | ||
3794d548 AK |
852 | typedef struct { |
853 | PowerPCCPU *cpu; | |
854 | uint32_t cpu_version; | |
f9ab1e87 | 855 | Error *err; |
3794d548 AK |
856 | } SetCompatState; |
857 | ||
858 | static void do_set_compat(void *arg) | |
859 | { | |
860 | SetCompatState *s = arg; | |
861 | ||
862 | cpu_synchronize_state(CPU(s->cpu)); | |
f9ab1e87 | 863 | ppc_set_compat(s->cpu, s->cpu_version, &s->err); |
3794d548 AK |
864 | } |
865 | ||
866 | #define get_compat_level(cpuver) ( \ | |
867 | ((cpuver) == CPU_POWERPC_LOGICAL_2_05) ? 2050 : \ | |
868 | ((cpuver) == CPU_POWERPC_LOGICAL_2_06) ? 2060 : \ | |
869 | ((cpuver) == CPU_POWERPC_LOGICAL_2_06_PLUS) ? 2061 : \ | |
870 | ((cpuver) == CPU_POWERPC_LOGICAL_2_07) ? 2070 : 0) | |
871 | ||
03d196b7 BR |
872 | #define OV5_DRCONF_MEMORY 0x20 |
873 | ||
2a6593cb | 874 | static target_ulong h_client_architecture_support(PowerPCCPU *cpu_, |
28e02042 | 875 | sPAPRMachineState *spapr, |
2a6593cb AK |
876 | target_ulong opcode, |
877 | target_ulong *args) | |
878 | { | |
27ac3e06 DG |
879 | target_ulong list = ppc64_phys_to_real(args[0]); |
880 | target_ulong ov_table, ov5; | |
3794d548 AK |
881 | PowerPCCPUClass *pcc_ = POWERPC_CPU_GET_CLASS(cpu_); |
882 | CPUState *cs; | |
03d196b7 | 883 | bool cpu_match = false, cpu_update = true, memory_update = false; |
3794d548 AK |
884 | unsigned old_cpu_version = cpu_->cpu_version; |
885 | unsigned compat_lvl = 0, cpu_version = 0; | |
886 | unsigned max_lvl = get_compat_level(cpu_->max_compat); | |
887 | int counter; | |
03d196b7 | 888 | char ov5_byte2; |
3794d548 AK |
889 | |
890 | /* Parse PVR list */ | |
891 | for (counter = 0; counter < 512; ++counter) { | |
892 | uint32_t pvr, pvr_mask; | |
893 | ||
27ac3e06 | 894 | pvr_mask = ldl_be_phys(&address_space_memory, list); |
3794d548 | 895 | list += 4; |
27ac3e06 | 896 | pvr = ldl_be_phys(&address_space_memory, list); |
3794d548 AK |
897 | list += 4; |
898 | ||
899 | trace_spapr_cas_pvr_try(pvr); | |
900 | if (!max_lvl && | |
901 | ((cpu_->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask))) { | |
902 | cpu_match = true; | |
903 | cpu_version = 0; | |
904 | } else if (pvr == cpu_->cpu_version) { | |
905 | cpu_match = true; | |
906 | cpu_version = cpu_->cpu_version; | |
907 | } else if (!cpu_match) { | |
908 | /* If it is a logical PVR, try to determine the highest level */ | |
909 | unsigned lvl = get_compat_level(pvr); | |
910 | if (lvl) { | |
911 | bool is205 = (pcc_->pcr_mask & PCR_COMPAT_2_05) && | |
912 | (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); | |
913 | bool is206 = (pcc_->pcr_mask & PCR_COMPAT_2_06) && | |
914 | ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || | |
915 | (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); | |
916 | ||
917 | if (is205 || is206) { | |
918 | if (!max_lvl) { | |
919 | /* User did not set the level, choose the highest */ | |
920 | if (compat_lvl <= lvl) { | |
921 | compat_lvl = lvl; | |
922 | cpu_version = pvr; | |
923 | } | |
924 | } else if (max_lvl >= lvl) { | |
925 | /* User chose the level, don't set higher than this */ | |
926 | compat_lvl = lvl; | |
927 | cpu_version = pvr; | |
928 | } | |
929 | } | |
930 | } | |
931 | } | |
932 | /* Terminator record */ | |
933 | if (~pvr_mask & pvr) { | |
934 | break; | |
935 | } | |
936 | } | |
937 | ||
3794d548 AK |
938 | /* Parsing finished */ |
939 | trace_spapr_cas_pvr(cpu_->cpu_version, cpu_match, | |
940 | cpu_version, pcc_->pcr_mask); | |
941 | ||
942 | /* Update CPUs */ | |
943 | if (old_cpu_version != cpu_version) { | |
944 | CPU_FOREACH(cs) { | |
945 | SetCompatState s = { | |
946 | .cpu = POWERPC_CPU(cs), | |
947 | .cpu_version = cpu_version, | |
f9ab1e87 | 948 | .err = NULL, |
3794d548 AK |
949 | }; |
950 | ||
951 | run_on_cpu(cs, do_set_compat, &s); | |
952 | ||
f9ab1e87 DG |
953 | if (s.err) { |
954 | error_report_err(s.err); | |
3794d548 AK |
955 | return H_HARDWARE; |
956 | } | |
957 | } | |
958 | } | |
959 | ||
960 | if (!cpu_version) { | |
03d196b7 | 961 | cpu_update = false; |
3794d548 | 962 | } |
2a6593cb | 963 | |
03d196b7 BR |
964 | /* For the future use: here @ov_table points to the first option vector */ |
965 | ov_table = list; | |
966 | ||
27ac3e06 DG |
967 | ov5 = cas_get_option_vector(5, ov_table); |
968 | if (!ov5) { | |
2a6593cb AK |
969 | return H_SUCCESS; |
970 | } | |
971 | ||
03d196b7 | 972 | /* @list now points to OV 5 */ |
27ac3e06 | 973 | ov5_byte2 = ldub_phys(&address_space_memory, ov5 + 2); |
03d196b7 BR |
974 | if (ov5_byte2 & OV5_DRCONF_MEMORY) { |
975 | memory_update = true; | |
976 | } | |
977 | ||
978 | if (spapr_h_cas_compose_response(spapr, args[1], args[2], | |
979 | cpu_update, memory_update)) { | |
2a6593cb AK |
980 | qemu_system_reset_request(); |
981 | } | |
982 | ||
983 | return H_SUCCESS; | |
984 | } | |
985 | ||
7d7ba3fe DG |
986 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
987 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; | |
9fdf0c29 DG |
988 | |
989 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) | |
990 | { | |
39ac8455 DG |
991 | spapr_hcall_fn *slot; |
992 | ||
993 | if (opcode <= MAX_HCALL_OPCODE) { | |
994 | assert((opcode & 0x3) == 0); | |
9fdf0c29 | 995 | |
39ac8455 DG |
996 | slot = &papr_hypercall_table[opcode / 4]; |
997 | } else { | |
998 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); | |
9fdf0c29 | 999 | |
39ac8455 DG |
1000 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
1001 | } | |
9fdf0c29 | 1002 | |
c89d5299 | 1003 | assert(!(*slot)); |
39ac8455 | 1004 | *slot = fn; |
9fdf0c29 DG |
1005 | } |
1006 | ||
aa100fa4 | 1007 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
9fdf0c29 DG |
1008 | target_ulong *args) |
1009 | { | |
28e02042 DG |
1010 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
1011 | ||
9fdf0c29 DG |
1012 | if ((opcode <= MAX_HCALL_OPCODE) |
1013 | && ((opcode & 0x3) == 0)) { | |
39ac8455 DG |
1014 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
1015 | ||
1016 | if (fn) { | |
b13ce26d | 1017 | return fn(cpu, spapr, opcode, args); |
39ac8455 DG |
1018 | } |
1019 | } else if ((opcode >= KVMPPC_HCALL_BASE) && | |
1020 | (opcode <= KVMPPC_HCALL_MAX)) { | |
1021 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
1022 | |
1023 | if (fn) { | |
b13ce26d | 1024 | return fn(cpu, spapr, opcode, args); |
9fdf0c29 DG |
1025 | } |
1026 | } | |
1027 | ||
aaf87c66 TH |
1028 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", |
1029 | opcode); | |
9fdf0c29 DG |
1030 | return H_FUNCTION; |
1031 | } | |
f43e3525 | 1032 | |
83f7d43a | 1033 | static void hypercall_register_types(void) |
f43e3525 DG |
1034 | { |
1035 | /* hcall-pft */ | |
1036 | spapr_register_hypercall(H_ENTER, h_enter); | |
1037 | spapr_register_hypercall(H_REMOVE, h_remove); | |
1038 | spapr_register_hypercall(H_PROTECT, h_protect); | |
6bbd5dde | 1039 | spapr_register_hypercall(H_READ, h_read); |
39ac8455 | 1040 | |
a3d0abae DG |
1041 | /* hcall-bulk */ |
1042 | spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); | |
1043 | ||
821303f5 DG |
1044 | /* hcall-dabr */ |
1045 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); | |
1046 | ||
ed120055 DG |
1047 | /* hcall-splpar */ |
1048 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); | |
1049 | spapr_register_hypercall(H_CEDE, h_cede); | |
1050 | ||
827200a2 DG |
1051 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate |
1052 | * here between the "CI" and the "CACHE" variants, they will use whatever | |
1053 | * mapping attributes qemu is using. When using KVM, the kernel will | |
1054 | * enforce the attributes more strongly | |
1055 | */ | |
1056 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); | |
1057 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); | |
1058 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); | |
1059 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); | |
1060 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); | |
1061 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); | |
c73e3771 | 1062 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
827200a2 | 1063 | |
39ac8455 DG |
1064 | /* qemu/KVM-PPC specific hcalls */ |
1065 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); | |
42561bf2 AB |
1066 | |
1067 | spapr_register_hypercall(H_SET_MODE, h_set_mode); | |
2a6593cb AK |
1068 | |
1069 | /* ibm,client-architecture-support support */ | |
1070 | spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); | |
f43e3525 | 1071 | } |
83f7d43a AF |
1072 | |
1073 | type_init(hypercall_register_types) |