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Commit | Line | Data |
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ad0ebb91 DG |
1 | /* |
2 | * QEMU sPAPR IOMMU (TCE) code | |
3 | * | |
4 | * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
df7625d4 | 20 | #include "qemu/error-report.h" |
83c9f4ca | 21 | #include "hw/hw.h" |
03dd024f | 22 | #include "qemu/log.h" |
9c17d615 | 23 | #include "sysemu/kvm.h" |
83c9f4ca | 24 | #include "hw/qdev.h" |
ad0ebb91 | 25 | #include "kvm_ppc.h" |
9c17d615 | 26 | #include "sysemu/dma.h" |
022c62cb | 27 | #include "exec/address-spaces.h" |
7e472264 | 28 | #include "trace.h" |
ad0ebb91 | 29 | |
0d09e41a | 30 | #include "hw/ppc/spapr.h" |
ee9a569a | 31 | #include "hw/ppc/spapr_vio.h" |
ad0ebb91 DG |
32 | |
33 | #include <libfdt.h> | |
34 | ||
ce2918cb | 35 | enum SpaprTceAccess { |
ad0ebb91 DG |
36 | SPAPR_TCE_FAULT = 0, |
37 | SPAPR_TCE_RO = 1, | |
38 | SPAPR_TCE_WO = 2, | |
39 | SPAPR_TCE_RW = 3, | |
40 | }; | |
41 | ||
650f33ad AK |
42 | #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift)) |
43 | #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1)) | |
44 | ||
ce2918cb | 45 | static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables; |
ad0ebb91 | 46 | |
ce2918cb | 47 | SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn) |
ad0ebb91 | 48 | { |
ce2918cb | 49 | SpaprTceTable *tcet; |
ad0ebb91 | 50 | |
d4261662 DG |
51 | if (liobn & 0xFFFFFFFF00000000ULL) { |
52 | hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n", | |
53 | liobn); | |
54 | return NULL; | |
55 | } | |
56 | ||
ad0ebb91 | 57 | QLIST_FOREACH(tcet, &spapr_tce_tables, list) { |
f9ce8e0a | 58 | if (tcet->liobn == (uint32_t)liobn) { |
ad0ebb91 DG |
59 | return tcet; |
60 | } | |
61 | } | |
62 | ||
63 | return NULL; | |
64 | } | |
65 | ||
5709af3b GK |
66 | static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce) |
67 | { | |
68 | switch (tce & SPAPR_TCE_RW) { | |
69 | case SPAPR_TCE_FAULT: | |
70 | return IOMMU_NONE; | |
71 | case SPAPR_TCE_RO: | |
72 | return IOMMU_RO; | |
73 | case SPAPR_TCE_WO: | |
74 | return IOMMU_WO; | |
75 | default: /* SPAPR_TCE_RW */ | |
76 | return IOMMU_RW; | |
77 | } | |
78 | } | |
79 | ||
fec5d3a1 AK |
80 | static uint64_t *spapr_tce_alloc_table(uint32_t liobn, |
81 | uint32_t page_shift, | |
d6ee2a7c | 82 | uint64_t bus_offset, |
fec5d3a1 AK |
83 | uint32_t nb_table, |
84 | int *fd, | |
85 | bool need_vfio) | |
86 | { | |
87 | uint64_t *table = NULL; | |
fec5d3a1 | 88 | |
d6ee2a7c AK |
89 | if (kvm_enabled()) { |
90 | table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table, | |
91 | fd, need_vfio); | |
fec5d3a1 AK |
92 | } |
93 | ||
94 | if (!table) { | |
95 | *fd = -1; | |
dec4ec40 | 96 | table = g_new0(uint64_t, nb_table); |
fec5d3a1 AK |
97 | } |
98 | ||
99 | trace_spapr_iommu_new_table(liobn, table, *fd); | |
100 | ||
101 | return table; | |
102 | } | |
103 | ||
104 | static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) | |
105 | { | |
106 | if (!kvm_enabled() || | |
107 | (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) { | |
108 | g_free(table); | |
109 | } | |
110 | } | |
111 | ||
79e2b9ae | 112 | /* Called from RCU critical section */ |
3df9d748 AK |
113 | static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu, |
114 | hwaddr addr, | |
2c91bcf2 PM |
115 | IOMMUAccessFlags flag, |
116 | int iommu_idx) | |
ad0ebb91 | 117 | { |
ce2918cb | 118 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
ad0ebb91 | 119 | uint64_t tce; |
7e472264 AK |
120 | IOMMUTLBEntry ret = { |
121 | .target_as = &address_space_memory, | |
122 | .iova = 0, | |
123 | .translated_addr = 0, | |
124 | .addr_mask = ~(hwaddr)0, | |
125 | .perm = IOMMU_NONE, | |
126 | }; | |
ad0ebb91 | 127 | |
ee9a569a | 128 | if ((addr >> tcet->page_shift) < tcet->nb_table) { |
7e472264 | 129 | /* Check if we are in bound */ |
650f33ad AK |
130 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
131 | ||
132 | tce = tcet->table[addr >> tcet->page_shift]; | |
133 | ret.iova = addr & page_mask; | |
134 | ret.translated_addr = tce & page_mask; | |
135 | ret.addr_mask = ~page_mask; | |
5709af3b | 136 | ret.perm = spapr_tce_iommu_access_flags(tce); |
ad0ebb91 | 137 | } |
7e472264 AK |
138 | trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm, |
139 | ret.addr_mask); | |
ad0ebb91 | 140 | |
7e472264 | 141 | return ret; |
a71bfbfe PB |
142 | } |
143 | ||
5f366667 AK |
144 | static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) |
145 | { | |
146 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); | |
147 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
148 | hwaddr addr, granularity; | |
149 | IOMMUTLBEntry iotlb; | |
ce2918cb | 150 | SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu); |
5f366667 AK |
151 | |
152 | if (tcet->skipping_replay) { | |
153 | return; | |
154 | } | |
155 | ||
156 | granularity = memory_region_iommu_get_min_page_size(iommu_mr); | |
157 | ||
158 | for (addr = 0; addr < memory_region_size(mr); addr += granularity) { | |
159 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx); | |
160 | if (iotlb.perm != IOMMU_NONE) { | |
161 | n->notify(n, &iotlb); | |
162 | } | |
163 | ||
164 | /* | |
165 | * if (2^64 - MR size) < granularity, it's possible to get an | |
166 | * infinite loop here. This should catch such a wraparound. | |
167 | */ | |
168 | if ((addr + granularity) < addr) { | |
169 | break; | |
170 | } | |
171 | } | |
172 | } | |
173 | ||
44b1ff31 | 174 | static int spapr_tce_table_pre_save(void *opaque) |
a26fdf39 | 175 | { |
ce2918cb | 176 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque); |
a26fdf39 AK |
177 | |
178 | tcet->mig_table = tcet->table; | |
179 | tcet->mig_nb_table = tcet->nb_table; | |
180 | ||
181 | trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table, | |
182 | tcet->bus_offset, tcet->page_shift); | |
44b1ff31 DDAG |
183 | |
184 | return 0; | |
a26fdf39 AK |
185 | } |
186 | ||
3df9d748 | 187 | static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu) |
f682e9c2 | 188 | { |
ce2918cb | 189 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
f682e9c2 AK |
190 | |
191 | return 1ULL << tcet->page_shift; | |
192 | } | |
193 | ||
9ded780c AK |
194 | static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu, |
195 | enum IOMMUMemoryRegionAttr attr, void *data) | |
196 | { | |
ce2918cb | 197 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
9ded780c AK |
198 | |
199 | if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) { | |
200 | *(int *) data = tcet->fd; | |
201 | return 0; | |
202 | } | |
203 | ||
204 | return -EINVAL; | |
205 | } | |
206 | ||
3df9d748 | 207 | static void spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu, |
5bf3d319 PX |
208 | IOMMUNotifierFlag old, |
209 | IOMMUNotifierFlag new) | |
606b5498 | 210 | { |
ce2918cb | 211 | struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu); |
606b5498 | 212 | |
5bf3d319 PX |
213 | if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) { |
214 | spapr_tce_set_need_vfio(tbl, true); | |
215 | } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) { | |
216 | spapr_tce_set_need_vfio(tbl, false); | |
217 | } | |
606b5498 AK |
218 | } |
219 | ||
ee9a569a AK |
220 | static int spapr_tce_table_post_load(void *opaque, int version_id) |
221 | { | |
ce2918cb | 222 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque); |
a26fdf39 AK |
223 | uint32_t old_nb_table = tcet->nb_table; |
224 | uint64_t old_bus_offset = tcet->bus_offset; | |
225 | uint32_t old_page_shift = tcet->page_shift; | |
ee9a569a AK |
226 | |
227 | if (tcet->vdev) { | |
228 | spapr_vio_set_bypass(tcet->vdev, tcet->bypass); | |
229 | } | |
230 | ||
a26fdf39 AK |
231 | if (tcet->mig_nb_table != tcet->nb_table) { |
232 | spapr_tce_table_disable(tcet); | |
233 | } | |
234 | ||
235 | if (tcet->mig_nb_table) { | |
236 | if (!tcet->nb_table) { | |
237 | spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset, | |
238 | tcet->mig_nb_table); | |
239 | } | |
240 | ||
241 | memcpy(tcet->table, tcet->mig_table, | |
242 | tcet->nb_table * sizeof(tcet->table[0])); | |
243 | ||
244 | free(tcet->mig_table); | |
245 | tcet->mig_table = NULL; | |
246 | } | |
247 | ||
248 | trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table, | |
249 | tcet->bus_offset, tcet->page_shift); | |
250 | ||
ee9a569a AK |
251 | return 0; |
252 | } | |
253 | ||
a26fdf39 AK |
254 | static bool spapr_tce_table_ex_needed(void *opaque) |
255 | { | |
ce2918cb | 256 | SpaprTceTable *tcet = opaque; |
a26fdf39 AK |
257 | |
258 | return tcet->bus_offset || tcet->page_shift != 0xC; | |
259 | } | |
260 | ||
261 | static const VMStateDescription vmstate_spapr_tce_table_ex = { | |
262 | .name = "spapr_iommu_ex", | |
263 | .version_id = 1, | |
264 | .minimum_version_id = 1, | |
265 | .needed = spapr_tce_table_ex_needed, | |
266 | .fields = (VMStateField[]) { | |
ce2918cb DG |
267 | VMSTATE_UINT64(bus_offset, SpaprTceTable), |
268 | VMSTATE_UINT32(page_shift, SpaprTceTable), | |
a26fdf39 AK |
269 | VMSTATE_END_OF_LIST() |
270 | }, | |
271 | }; | |
272 | ||
a83000f5 AL |
273 | static const VMStateDescription vmstate_spapr_tce_table = { |
274 | .name = "spapr_iommu", | |
523e7b8a AK |
275 | .version_id = 2, |
276 | .minimum_version_id = 2, | |
a26fdf39 | 277 | .pre_save = spapr_tce_table_pre_save, |
ee9a569a | 278 | .post_load = spapr_tce_table_post_load, |
523e7b8a | 279 | .fields = (VMStateField []) { |
a83000f5 | 280 | /* Sanity check */ |
ce2918cb | 281 | VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL), |
a83000f5 AL |
282 | |
283 | /* IOMMU state */ | |
ce2918cb DG |
284 | VMSTATE_UINT32(mig_nb_table, SpaprTceTable), |
285 | VMSTATE_BOOL(bypass, SpaprTceTable), | |
286 | VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0, | |
a26fdf39 | 287 | vmstate_info_uint64, uint64_t), |
a83000f5 AL |
288 | |
289 | VMSTATE_END_OF_LIST() | |
290 | }, | |
a26fdf39 AK |
291 | .subsections = (const VMStateDescription*[]) { |
292 | &vmstate_spapr_tce_table_ex, | |
293 | NULL | |
294 | } | |
a83000f5 AL |
295 | }; |
296 | ||
a931ad13 | 297 | static void spapr_tce_table_realize(DeviceState *dev, Error **errp) |
ad0ebb91 | 298 | { |
ce2918cb | 299 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
b4b6eb77 | 300 | Object *tcetobj = OBJECT(tcet); |
a205a053 | 301 | gchar *tmp; |
ad0ebb91 | 302 | |
fec5d3a1 | 303 | tcet->fd = -1; |
df7625d4 | 304 | tcet->need_vfio = false; |
a205a053 | 305 | tmp = g_strdup_printf("tce-root-%x", tcet->liobn); |
b4b6eb77 | 306 | memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX); |
a205a053 | 307 | g_free(tmp); |
b4b6eb77 | 308 | |
a205a053 | 309 | tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn); |
1221a474 AK |
310 | memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu), |
311 | TYPE_SPAPR_IOMMU_MEMORY_REGION, | |
312 | tcetobj, tmp, 0); | |
a205a053 | 313 | g_free(tmp); |
a84bb436 | 314 | |
ad0ebb91 DG |
315 | QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); |
316 | ||
00d4f525 AK |
317 | vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table, |
318 | tcet); | |
a83000f5 AL |
319 | } |
320 | ||
ce2918cb | 321 | void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio) |
c10325d6 DG |
322 | { |
323 | size_t table_size = tcet->nb_table * sizeof(uint64_t); | |
f5509b6b AK |
324 | uint64_t *oldtable; |
325 | int newfd = -1; | |
c10325d6 | 326 | |
f5509b6b | 327 | g_assert(need_vfio != tcet->need_vfio); |
c10325d6 | 328 | |
f5509b6b | 329 | tcet->need_vfio = need_vfio; |
c10325d6 | 330 | |
9ded780c AK |
331 | if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) { |
332 | return; | |
333 | } | |
334 | ||
f5509b6b | 335 | oldtable = tcet->table; |
c10325d6 | 336 | |
f5509b6b AK |
337 | tcet->table = spapr_tce_alloc_table(tcet->liobn, |
338 | tcet->page_shift, | |
339 | tcet->bus_offset, | |
340 | tcet->nb_table, | |
341 | &newfd, | |
342 | need_vfio); | |
343 | memcpy(tcet->table, oldtable, table_size); | |
c10325d6 | 344 | |
f5509b6b | 345 | spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table); |
c10325d6 | 346 | |
f5509b6b | 347 | tcet->fd = newfd; |
c10325d6 DG |
348 | } |
349 | ||
ce2918cb | 350 | SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn) |
a83000f5 | 351 | { |
ce2918cb | 352 | SpaprTceTable *tcet; |
a205a053 | 353 | gchar *tmp; |
a83000f5 AL |
354 | |
355 | if (spapr_tce_find_by_liobn(liobn)) { | |
ce9863b7 CLG |
356 | error_report("Attempted to create TCE table with duplicate" |
357 | " LIOBN 0x%x", liobn); | |
a83000f5 AL |
358 | return NULL; |
359 | } | |
360 | ||
a83000f5 AL |
361 | tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); |
362 | tcet->liobn = liobn; | |
a83000f5 | 363 | |
a205a053 | 364 | tmp = g_strdup_printf("tce-table-%x", liobn); |
dea1b3ce | 365 | object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); |
a205a053 | 366 | g_free(tmp); |
8dc9785c | 367 | object_unref(OBJECT(tcet)); |
a83000f5 | 368 | |
e4c35b78 | 369 | object_property_set_bool(OBJECT(tcet), true, "realized", NULL); |
a83000f5 | 370 | |
2b7dc949 | 371 | return tcet; |
ad0ebb91 DG |
372 | } |
373 | ||
ce2918cb | 374 | void spapr_tce_table_enable(SpaprTceTable *tcet, |
df7625d4 AK |
375 | uint32_t page_shift, uint64_t bus_offset, |
376 | uint32_t nb_table) | |
377 | { | |
378 | if (tcet->nb_table) { | |
3dc6f869 | 379 | warn_report("trying to enable already enabled TCE table"); |
df7625d4 AK |
380 | return; |
381 | } | |
382 | ||
383 | tcet->bus_offset = bus_offset; | |
384 | tcet->page_shift = page_shift; | |
385 | tcet->nb_table = nb_table; | |
386 | tcet->table = spapr_tce_alloc_table(tcet->liobn, | |
387 | tcet->page_shift, | |
d6ee2a7c | 388 | tcet->bus_offset, |
df7625d4 AK |
389 | tcet->nb_table, |
390 | &tcet->fd, | |
391 | tcet->need_vfio); | |
392 | ||
3df9d748 | 393 | memory_region_set_size(MEMORY_REGION(&tcet->iommu), |
df7625d4 | 394 | (uint64_t)tcet->nb_table << tcet->page_shift); |
3df9d748 AK |
395 | memory_region_add_subregion(&tcet->root, tcet->bus_offset, |
396 | MEMORY_REGION(&tcet->iommu)); | |
df7625d4 AK |
397 | } |
398 | ||
ce2918cb | 399 | void spapr_tce_table_disable(SpaprTceTable *tcet) |
df7625d4 AK |
400 | { |
401 | if (!tcet->nb_table) { | |
402 | return; | |
403 | } | |
404 | ||
3df9d748 AK |
405 | memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu)); |
406 | memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0); | |
df7625d4 AK |
407 | |
408 | spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table); | |
409 | tcet->fd = -1; | |
410 | tcet->table = NULL; | |
411 | tcet->bus_offset = 0; | |
412 | tcet->page_shift = 0; | |
413 | tcet->nb_table = 0; | |
414 | } | |
415 | ||
5f9490de | 416 | static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) |
ad0ebb91 | 417 | { |
ce2918cb | 418 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
a83000f5 | 419 | |
ea359d20 GK |
420 | vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet); |
421 | ||
2b7dc949 | 422 | QLIST_REMOVE(tcet, list); |
ad0ebb91 | 423 | |
df7625d4 | 424 | spapr_tce_table_disable(tcet); |
ad0ebb91 DG |
425 | } |
426 | ||
ce2918cb | 427 | MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet) |
a84bb436 | 428 | { |
b4b6eb77 | 429 | return &tcet->root; |
a84bb436 PB |
430 | } |
431 | ||
a83000f5 | 432 | static void spapr_tce_reset(DeviceState *dev) |
eddeed26 | 433 | { |
ce2918cb | 434 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
523e7b8a | 435 | size_t table_size = tcet->nb_table * sizeof(uint64_t); |
eddeed26 | 436 | |
57c0eb1e DG |
437 | if (tcet->nb_table) { |
438 | memset(tcet->table, 0, table_size); | |
439 | } | |
eddeed26 DG |
440 | } |
441 | ||
ce2918cb | 442 | static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba, |
edded454 DG |
443 | target_ulong tce) |
444 | { | |
a84bb436 | 445 | IOMMUTLBEntry entry; |
650f33ad | 446 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
1b8eceee | 447 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
edded454 | 448 | |
1b8eceee | 449 | if (index >= tcet->nb_table) { |
b55519a0 | 450 | hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x" |
edded454 DG |
451 | TARGET_FMT_lx "\n", ioba); |
452 | return H_PARAMETER; | |
453 | } | |
454 | ||
1b8eceee | 455 | tcet->table[index] = tce; |
edded454 | 456 | |
a84bb436 | 457 | entry.target_as = &address_space_memory, |
d78c19b5 | 458 | entry.iova = (ioba - tcet->bus_offset) & page_mask; |
650f33ad AK |
459 | entry.translated_addr = tce & page_mask; |
460 | entry.addr_mask = ~page_mask; | |
5709af3b | 461 | entry.perm = spapr_tce_iommu_access_flags(tce); |
cb1efcf4 | 462 | memory_region_notify_iommu(&tcet->iommu, 0, entry); |
a84bb436 | 463 | |
edded454 DG |
464 | return H_SUCCESS; |
465 | } | |
ad0ebb91 | 466 | |
da95324e | 467 | static target_ulong h_put_tce_indirect(PowerPCCPU *cpu, |
ce2918cb | 468 | SpaprMachineState *spapr, |
da95324e AK |
469 | target_ulong opcode, target_ulong *args) |
470 | { | |
471 | int i; | |
472 | target_ulong liobn = args[0]; | |
473 | target_ulong ioba = args[1]; | |
474 | target_ulong ioba1 = ioba; | |
475 | target_ulong tce_list = args[2]; | |
476 | target_ulong npages = args[3]; | |
f1215ea7 | 477 | target_ulong ret = H_PARAMETER, tce = 0; |
ce2918cb | 478 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
da95324e | 479 | CPUState *cs = CPU(cpu); |
650f33ad | 480 | hwaddr page_mask, page_size; |
da95324e AK |
481 | |
482 | if (!tcet) { | |
483 | return H_PARAMETER; | |
484 | } | |
485 | ||
650f33ad | 486 | if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) { |
da95324e AK |
487 | return H_PARAMETER; |
488 | } | |
489 | ||
650f33ad AK |
490 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
491 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
492 | ioba &= page_mask; | |
493 | ||
494 | for (i = 0; i < npages; ++i, ioba += page_size) { | |
4d9ab7d4 | 495 | tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong)); |
da95324e | 496 | |
da95324e AK |
497 | ret = put_tce_emu(tcet, ioba, tce); |
498 | if (ret) { | |
499 | break; | |
500 | } | |
501 | } | |
502 | ||
503 | /* Trace last successful or the first problematic entry */ | |
504 | i = i ? (i - 1) : 0; | |
d9d96a3c AK |
505 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
506 | trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
507 | } else { | |
508 | trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
509 | } | |
da95324e AK |
510 | return ret; |
511 | } | |
512 | ||
ce2918cb | 513 | static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
da95324e AK |
514 | target_ulong opcode, target_ulong *args) |
515 | { | |
516 | int i; | |
517 | target_ulong liobn = args[0]; | |
518 | target_ulong ioba = args[1]; | |
519 | target_ulong tce_value = args[2]; | |
520 | target_ulong npages = args[3]; | |
521 | target_ulong ret = H_PARAMETER; | |
ce2918cb | 522 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
650f33ad | 523 | hwaddr page_mask, page_size; |
da95324e AK |
524 | |
525 | if (!tcet) { | |
526 | return H_PARAMETER; | |
527 | } | |
528 | ||
529 | if (npages > tcet->nb_table) { | |
530 | return H_PARAMETER; | |
531 | } | |
532 | ||
650f33ad AK |
533 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
534 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
535 | ioba &= page_mask; | |
da95324e | 536 | |
650f33ad | 537 | for (i = 0; i < npages; ++i, ioba += page_size) { |
da95324e AK |
538 | ret = put_tce_emu(tcet, ioba, tce_value); |
539 | if (ret) { | |
540 | break; | |
541 | } | |
542 | } | |
d9d96a3c AK |
543 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
544 | trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret); | |
545 | } else { | |
546 | trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret); | |
547 | } | |
da95324e AK |
548 | |
549 | return ret; | |
550 | } | |
551 | ||
ce2918cb | 552 | static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
ad0ebb91 DG |
553 | target_ulong opcode, target_ulong *args) |
554 | { | |
555 | target_ulong liobn = args[0]; | |
556 | target_ulong ioba = args[1]; | |
557 | target_ulong tce = args[2]; | |
7e472264 | 558 | target_ulong ret = H_PARAMETER; |
ce2918cb | 559 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
ad0ebb91 | 560 | |
edded454 | 561 | if (tcet) { |
650f33ad AK |
562 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
563 | ||
564 | ioba &= page_mask; | |
565 | ||
7e472264 | 566 | ret = put_tce_emu(tcet, ioba, tce); |
edded454 | 567 | } |
d9d96a3c AK |
568 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
569 | trace_spapr_iommu_pci_put(liobn, ioba, tce, ret); | |
570 | } else { | |
571 | trace_spapr_iommu_put(liobn, ioba, tce, ret); | |
572 | } | |
ad0ebb91 | 573 | |
7e472264 | 574 | return ret; |
ad0ebb91 DG |
575 | } |
576 | ||
ce2918cb | 577 | static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba, |
a0fcac9c LD |
578 | target_ulong *tce) |
579 | { | |
1b8eceee AK |
580 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
581 | ||
582 | if (index >= tcet->nb_table) { | |
a0fcac9c LD |
583 | hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x" |
584 | TARGET_FMT_lx "\n", ioba); | |
585 | return H_PARAMETER; | |
586 | } | |
587 | ||
1b8eceee | 588 | *tce = tcet->table[index]; |
a0fcac9c LD |
589 | |
590 | return H_SUCCESS; | |
591 | } | |
592 | ||
ce2918cb | 593 | static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
a0fcac9c LD |
594 | target_ulong opcode, target_ulong *args) |
595 | { | |
596 | target_ulong liobn = args[0]; | |
597 | target_ulong ioba = args[1]; | |
598 | target_ulong tce = 0; | |
599 | target_ulong ret = H_PARAMETER; | |
ce2918cb | 600 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
a0fcac9c | 601 | |
a0fcac9c | 602 | if (tcet) { |
650f33ad AK |
603 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
604 | ||
605 | ioba &= page_mask; | |
606 | ||
a0fcac9c LD |
607 | ret = get_tce_emu(tcet, ioba, &tce); |
608 | if (!ret) { | |
609 | args[0] = tce; | |
610 | } | |
611 | } | |
d9d96a3c AK |
612 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
613 | trace_spapr_iommu_pci_get(liobn, ioba, ret, tce); | |
614 | } else { | |
615 | trace_spapr_iommu_get(liobn, ioba, ret, tce); | |
616 | } | |
a0fcac9c LD |
617 | |
618 | return ret; | |
619 | } | |
620 | ||
ad0ebb91 | 621 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
5c4cbcf2 | 622 | uint32_t liobn, uint64_t window, uint32_t size) |
ad0ebb91 | 623 | { |
5c4cbcf2 AK |
624 | uint32_t dma_prop[5]; |
625 | int ret; | |
626 | ||
627 | dma_prop[0] = cpu_to_be32(liobn); | |
628 | dma_prop[1] = cpu_to_be32(window >> 32); | |
629 | dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF); | |
630 | dma_prop[3] = 0; /* window size is 32 bits */ | |
631 | dma_prop[4] = cpu_to_be32(size); | |
632 | ||
633 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2); | |
634 | if (ret < 0) { | |
635 | return ret; | |
636 | } | |
ad0ebb91 | 637 | |
5c4cbcf2 AK |
638 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2); |
639 | if (ret < 0) { | |
640 | return ret; | |
641 | } | |
ad0ebb91 | 642 | |
5c4cbcf2 AK |
643 | ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop)); |
644 | if (ret < 0) { | |
645 | return ret; | |
ad0ebb91 DG |
646 | } |
647 | ||
648 | return 0; | |
649 | } | |
5c4cbcf2 AK |
650 | |
651 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, | |
ce2918cb | 652 | SpaprTceTable *tcet) |
5c4cbcf2 | 653 | { |
2b7dc949 | 654 | if (!tcet) { |
5c4cbcf2 AK |
655 | return 0; |
656 | } | |
657 | ||
2b7dc949 | 658 | return spapr_dma_dt(fdt, node_off, propname, |
650f33ad | 659 | tcet->liobn, 0, tcet->nb_table << tcet->page_shift); |
5c4cbcf2 | 660 | } |
a83000f5 AL |
661 | |
662 | static void spapr_tce_table_class_init(ObjectClass *klass, void *data) | |
663 | { | |
664 | DeviceClass *dc = DEVICE_CLASS(klass); | |
a931ad13 | 665 | dc->realize = spapr_tce_table_realize; |
a83000f5 | 666 | dc->reset = spapr_tce_reset; |
5f9490de | 667 | dc->unrealize = spapr_tce_table_unrealize; |
1f98e553 TH |
668 | /* Reason: This is just an internal device for handling the hypercalls */ |
669 | dc->user_creatable = false; | |
a83000f5 AL |
670 | |
671 | QLIST_INIT(&spapr_tce_tables); | |
672 | ||
673 | /* hcall-tce */ | |
674 | spapr_register_hypercall(H_PUT_TCE, h_put_tce); | |
a0fcac9c | 675 | spapr_register_hypercall(H_GET_TCE, h_get_tce); |
da95324e AK |
676 | spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect); |
677 | spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); | |
a83000f5 AL |
678 | } |
679 | ||
680 | static TypeInfo spapr_tce_table_info = { | |
681 | .name = TYPE_SPAPR_TCE_TABLE, | |
682 | .parent = TYPE_DEVICE, | |
ce2918cb | 683 | .instance_size = sizeof(SpaprTceTable), |
a83000f5 | 684 | .class_init = spapr_tce_table_class_init, |
a83000f5 AL |
685 | }; |
686 | ||
1221a474 AK |
687 | static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data) |
688 | { | |
689 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); | |
690 | ||
691 | imrc->translate = spapr_tce_translate_iommu; | |
5f366667 | 692 | imrc->replay = spapr_tce_replay; |
1221a474 AK |
693 | imrc->get_min_page_size = spapr_tce_get_min_page_size; |
694 | imrc->notify_flag_changed = spapr_tce_notify_flag_changed; | |
9ded780c | 695 | imrc->get_attr = spapr_tce_get_attr; |
1221a474 AK |
696 | } |
697 | ||
698 | static const TypeInfo spapr_iommu_memory_region_info = { | |
699 | .parent = TYPE_IOMMU_MEMORY_REGION, | |
700 | .name = TYPE_SPAPR_IOMMU_MEMORY_REGION, | |
701 | .class_init = spapr_iommu_memory_region_class_init, | |
702 | }; | |
703 | ||
a83000f5 AL |
704 | static void register_types(void) |
705 | { | |
706 | type_register_static(&spapr_tce_table_info); | |
1221a474 | 707 | type_register_static(&spapr_iommu_memory_region_info); |
a83000f5 AL |
708 | } |
709 | ||
710 | type_init(register_types); |