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Commit | Line | Data |
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ad0ebb91 DG |
1 | /* |
2 | * QEMU sPAPR IOMMU (TCE) code | |
3 | * | |
4 | * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0b8fa32f | 19 | |
0d75590d | 20 | #include "qemu/osdep.h" |
df7625d4 | 21 | #include "qemu/error-report.h" |
83c9f4ca | 22 | #include "hw/hw.h" |
03dd024f | 23 | #include "qemu/log.h" |
0b8fa32f | 24 | #include "qemu/module.h" |
9c17d615 | 25 | #include "sysemu/kvm.h" |
83c9f4ca | 26 | #include "hw/qdev.h" |
ad0ebb91 | 27 | #include "kvm_ppc.h" |
9c17d615 | 28 | #include "sysemu/dma.h" |
022c62cb | 29 | #include "exec/address-spaces.h" |
7e472264 | 30 | #include "trace.h" |
ad0ebb91 | 31 | |
0d09e41a | 32 | #include "hw/ppc/spapr.h" |
ee9a569a | 33 | #include "hw/ppc/spapr_vio.h" |
ad0ebb91 DG |
34 | |
35 | #include <libfdt.h> | |
36 | ||
ce2918cb | 37 | enum SpaprTceAccess { |
ad0ebb91 DG |
38 | SPAPR_TCE_FAULT = 0, |
39 | SPAPR_TCE_RO = 1, | |
40 | SPAPR_TCE_WO = 2, | |
41 | SPAPR_TCE_RW = 3, | |
42 | }; | |
43 | ||
650f33ad AK |
44 | #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift)) |
45 | #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1)) | |
46 | ||
ce2918cb | 47 | static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables; |
ad0ebb91 | 48 | |
ce2918cb | 49 | SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn) |
ad0ebb91 | 50 | { |
ce2918cb | 51 | SpaprTceTable *tcet; |
ad0ebb91 | 52 | |
d4261662 DG |
53 | if (liobn & 0xFFFFFFFF00000000ULL) { |
54 | hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n", | |
55 | liobn); | |
56 | return NULL; | |
57 | } | |
58 | ||
ad0ebb91 | 59 | QLIST_FOREACH(tcet, &spapr_tce_tables, list) { |
f9ce8e0a | 60 | if (tcet->liobn == (uint32_t)liobn) { |
ad0ebb91 DG |
61 | return tcet; |
62 | } | |
63 | } | |
64 | ||
65 | return NULL; | |
66 | } | |
67 | ||
5709af3b GK |
68 | static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce) |
69 | { | |
70 | switch (tce & SPAPR_TCE_RW) { | |
71 | case SPAPR_TCE_FAULT: | |
72 | return IOMMU_NONE; | |
73 | case SPAPR_TCE_RO: | |
74 | return IOMMU_RO; | |
75 | case SPAPR_TCE_WO: | |
76 | return IOMMU_WO; | |
77 | default: /* SPAPR_TCE_RW */ | |
78 | return IOMMU_RW; | |
79 | } | |
80 | } | |
81 | ||
fec5d3a1 AK |
82 | static uint64_t *spapr_tce_alloc_table(uint32_t liobn, |
83 | uint32_t page_shift, | |
d6ee2a7c | 84 | uint64_t bus_offset, |
fec5d3a1 AK |
85 | uint32_t nb_table, |
86 | int *fd, | |
87 | bool need_vfio) | |
88 | { | |
89 | uint64_t *table = NULL; | |
fec5d3a1 | 90 | |
d6ee2a7c AK |
91 | if (kvm_enabled()) { |
92 | table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table, | |
93 | fd, need_vfio); | |
fec5d3a1 AK |
94 | } |
95 | ||
96 | if (!table) { | |
97 | *fd = -1; | |
dec4ec40 | 98 | table = g_new0(uint64_t, nb_table); |
fec5d3a1 AK |
99 | } |
100 | ||
101 | trace_spapr_iommu_new_table(liobn, table, *fd); | |
102 | ||
103 | return table; | |
104 | } | |
105 | ||
106 | static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) | |
107 | { | |
108 | if (!kvm_enabled() || | |
109 | (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) { | |
110 | g_free(table); | |
111 | } | |
112 | } | |
113 | ||
79e2b9ae | 114 | /* Called from RCU critical section */ |
3df9d748 AK |
115 | static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu, |
116 | hwaddr addr, | |
2c91bcf2 PM |
117 | IOMMUAccessFlags flag, |
118 | int iommu_idx) | |
ad0ebb91 | 119 | { |
ce2918cb | 120 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
ad0ebb91 | 121 | uint64_t tce; |
7e472264 AK |
122 | IOMMUTLBEntry ret = { |
123 | .target_as = &address_space_memory, | |
124 | .iova = 0, | |
125 | .translated_addr = 0, | |
126 | .addr_mask = ~(hwaddr)0, | |
127 | .perm = IOMMU_NONE, | |
128 | }; | |
ad0ebb91 | 129 | |
ee9a569a | 130 | if ((addr >> tcet->page_shift) < tcet->nb_table) { |
7e472264 | 131 | /* Check if we are in bound */ |
650f33ad AK |
132 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
133 | ||
134 | tce = tcet->table[addr >> tcet->page_shift]; | |
135 | ret.iova = addr & page_mask; | |
136 | ret.translated_addr = tce & page_mask; | |
137 | ret.addr_mask = ~page_mask; | |
5709af3b | 138 | ret.perm = spapr_tce_iommu_access_flags(tce); |
ad0ebb91 | 139 | } |
7e472264 AK |
140 | trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm, |
141 | ret.addr_mask); | |
ad0ebb91 | 142 | |
7e472264 | 143 | return ret; |
a71bfbfe PB |
144 | } |
145 | ||
5f366667 AK |
146 | static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) |
147 | { | |
148 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); | |
149 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
150 | hwaddr addr, granularity; | |
151 | IOMMUTLBEntry iotlb; | |
ce2918cb | 152 | SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu); |
5f366667 AK |
153 | |
154 | if (tcet->skipping_replay) { | |
155 | return; | |
156 | } | |
157 | ||
158 | granularity = memory_region_iommu_get_min_page_size(iommu_mr); | |
159 | ||
160 | for (addr = 0; addr < memory_region_size(mr); addr += granularity) { | |
161 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx); | |
162 | if (iotlb.perm != IOMMU_NONE) { | |
163 | n->notify(n, &iotlb); | |
164 | } | |
165 | ||
166 | /* | |
167 | * if (2^64 - MR size) < granularity, it's possible to get an | |
168 | * infinite loop here. This should catch such a wraparound. | |
169 | */ | |
170 | if ((addr + granularity) < addr) { | |
171 | break; | |
172 | } | |
173 | } | |
174 | } | |
175 | ||
44b1ff31 | 176 | static int spapr_tce_table_pre_save(void *opaque) |
a26fdf39 | 177 | { |
ce2918cb | 178 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque); |
a26fdf39 AK |
179 | |
180 | tcet->mig_table = tcet->table; | |
181 | tcet->mig_nb_table = tcet->nb_table; | |
182 | ||
183 | trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table, | |
184 | tcet->bus_offset, tcet->page_shift); | |
44b1ff31 DDAG |
185 | |
186 | return 0; | |
a26fdf39 AK |
187 | } |
188 | ||
3df9d748 | 189 | static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu) |
f682e9c2 | 190 | { |
ce2918cb | 191 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
f682e9c2 AK |
192 | |
193 | return 1ULL << tcet->page_shift; | |
194 | } | |
195 | ||
9ded780c AK |
196 | static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu, |
197 | enum IOMMUMemoryRegionAttr attr, void *data) | |
198 | { | |
ce2918cb | 199 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
9ded780c AK |
200 | |
201 | if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) { | |
202 | *(int *) data = tcet->fd; | |
203 | return 0; | |
204 | } | |
205 | ||
206 | return -EINVAL; | |
207 | } | |
208 | ||
3df9d748 | 209 | static void spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu, |
5bf3d319 PX |
210 | IOMMUNotifierFlag old, |
211 | IOMMUNotifierFlag new) | |
606b5498 | 212 | { |
ce2918cb | 213 | struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu); |
606b5498 | 214 | |
5bf3d319 PX |
215 | if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) { |
216 | spapr_tce_set_need_vfio(tbl, true); | |
217 | } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) { | |
218 | spapr_tce_set_need_vfio(tbl, false); | |
219 | } | |
606b5498 AK |
220 | } |
221 | ||
ee9a569a AK |
222 | static int spapr_tce_table_post_load(void *opaque, int version_id) |
223 | { | |
ce2918cb | 224 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque); |
a26fdf39 AK |
225 | uint32_t old_nb_table = tcet->nb_table; |
226 | uint64_t old_bus_offset = tcet->bus_offset; | |
227 | uint32_t old_page_shift = tcet->page_shift; | |
ee9a569a AK |
228 | |
229 | if (tcet->vdev) { | |
230 | spapr_vio_set_bypass(tcet->vdev, tcet->bypass); | |
231 | } | |
232 | ||
a26fdf39 AK |
233 | if (tcet->mig_nb_table != tcet->nb_table) { |
234 | spapr_tce_table_disable(tcet); | |
235 | } | |
236 | ||
237 | if (tcet->mig_nb_table) { | |
238 | if (!tcet->nb_table) { | |
239 | spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset, | |
240 | tcet->mig_nb_table); | |
241 | } | |
242 | ||
243 | memcpy(tcet->table, tcet->mig_table, | |
244 | tcet->nb_table * sizeof(tcet->table[0])); | |
245 | ||
246 | free(tcet->mig_table); | |
247 | tcet->mig_table = NULL; | |
248 | } | |
249 | ||
250 | trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table, | |
251 | tcet->bus_offset, tcet->page_shift); | |
252 | ||
ee9a569a AK |
253 | return 0; |
254 | } | |
255 | ||
a26fdf39 AK |
256 | static bool spapr_tce_table_ex_needed(void *opaque) |
257 | { | |
ce2918cb | 258 | SpaprTceTable *tcet = opaque; |
a26fdf39 AK |
259 | |
260 | return tcet->bus_offset || tcet->page_shift != 0xC; | |
261 | } | |
262 | ||
263 | static const VMStateDescription vmstate_spapr_tce_table_ex = { | |
264 | .name = "spapr_iommu_ex", | |
265 | .version_id = 1, | |
266 | .minimum_version_id = 1, | |
267 | .needed = spapr_tce_table_ex_needed, | |
268 | .fields = (VMStateField[]) { | |
ce2918cb DG |
269 | VMSTATE_UINT64(bus_offset, SpaprTceTable), |
270 | VMSTATE_UINT32(page_shift, SpaprTceTable), | |
a26fdf39 AK |
271 | VMSTATE_END_OF_LIST() |
272 | }, | |
273 | }; | |
274 | ||
a83000f5 AL |
275 | static const VMStateDescription vmstate_spapr_tce_table = { |
276 | .name = "spapr_iommu", | |
523e7b8a AK |
277 | .version_id = 2, |
278 | .minimum_version_id = 2, | |
a26fdf39 | 279 | .pre_save = spapr_tce_table_pre_save, |
ee9a569a | 280 | .post_load = spapr_tce_table_post_load, |
523e7b8a | 281 | .fields = (VMStateField []) { |
a83000f5 | 282 | /* Sanity check */ |
ce2918cb | 283 | VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL), |
a83000f5 AL |
284 | |
285 | /* IOMMU state */ | |
ce2918cb DG |
286 | VMSTATE_UINT32(mig_nb_table, SpaprTceTable), |
287 | VMSTATE_BOOL(bypass, SpaprTceTable), | |
288 | VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0, | |
a26fdf39 | 289 | vmstate_info_uint64, uint64_t), |
a83000f5 AL |
290 | |
291 | VMSTATE_END_OF_LIST() | |
292 | }, | |
a26fdf39 AK |
293 | .subsections = (const VMStateDescription*[]) { |
294 | &vmstate_spapr_tce_table_ex, | |
295 | NULL | |
296 | } | |
a83000f5 AL |
297 | }; |
298 | ||
a931ad13 | 299 | static void spapr_tce_table_realize(DeviceState *dev, Error **errp) |
ad0ebb91 | 300 | { |
ce2918cb | 301 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
b4b6eb77 | 302 | Object *tcetobj = OBJECT(tcet); |
a205a053 | 303 | gchar *tmp; |
ad0ebb91 | 304 | |
fec5d3a1 | 305 | tcet->fd = -1; |
df7625d4 | 306 | tcet->need_vfio = false; |
a205a053 | 307 | tmp = g_strdup_printf("tce-root-%x", tcet->liobn); |
b4b6eb77 | 308 | memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX); |
a205a053 | 309 | g_free(tmp); |
b4b6eb77 | 310 | |
a205a053 | 311 | tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn); |
1221a474 AK |
312 | memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu), |
313 | TYPE_SPAPR_IOMMU_MEMORY_REGION, | |
314 | tcetobj, tmp, 0); | |
a205a053 | 315 | g_free(tmp); |
a84bb436 | 316 | |
ad0ebb91 DG |
317 | QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); |
318 | ||
00d4f525 AK |
319 | vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table, |
320 | tcet); | |
a83000f5 AL |
321 | } |
322 | ||
ce2918cb | 323 | void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio) |
c10325d6 DG |
324 | { |
325 | size_t table_size = tcet->nb_table * sizeof(uint64_t); | |
f5509b6b AK |
326 | uint64_t *oldtable; |
327 | int newfd = -1; | |
c10325d6 | 328 | |
f5509b6b | 329 | g_assert(need_vfio != tcet->need_vfio); |
c10325d6 | 330 | |
f5509b6b | 331 | tcet->need_vfio = need_vfio; |
c10325d6 | 332 | |
9ded780c AK |
333 | if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) { |
334 | return; | |
335 | } | |
336 | ||
f5509b6b | 337 | oldtable = tcet->table; |
c10325d6 | 338 | |
f5509b6b AK |
339 | tcet->table = spapr_tce_alloc_table(tcet->liobn, |
340 | tcet->page_shift, | |
341 | tcet->bus_offset, | |
342 | tcet->nb_table, | |
343 | &newfd, | |
344 | need_vfio); | |
345 | memcpy(tcet->table, oldtable, table_size); | |
c10325d6 | 346 | |
f5509b6b | 347 | spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table); |
c10325d6 | 348 | |
f5509b6b | 349 | tcet->fd = newfd; |
c10325d6 DG |
350 | } |
351 | ||
ce2918cb | 352 | SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn) |
a83000f5 | 353 | { |
ce2918cb | 354 | SpaprTceTable *tcet; |
a205a053 | 355 | gchar *tmp; |
a83000f5 AL |
356 | |
357 | if (spapr_tce_find_by_liobn(liobn)) { | |
ce9863b7 CLG |
358 | error_report("Attempted to create TCE table with duplicate" |
359 | " LIOBN 0x%x", liobn); | |
a83000f5 AL |
360 | return NULL; |
361 | } | |
362 | ||
a83000f5 AL |
363 | tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); |
364 | tcet->liobn = liobn; | |
a83000f5 | 365 | |
a205a053 | 366 | tmp = g_strdup_printf("tce-table-%x", liobn); |
dea1b3ce | 367 | object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); |
a205a053 | 368 | g_free(tmp); |
8dc9785c | 369 | object_unref(OBJECT(tcet)); |
a83000f5 | 370 | |
e4c35b78 | 371 | object_property_set_bool(OBJECT(tcet), true, "realized", NULL); |
a83000f5 | 372 | |
2b7dc949 | 373 | return tcet; |
ad0ebb91 DG |
374 | } |
375 | ||
ce2918cb | 376 | void spapr_tce_table_enable(SpaprTceTable *tcet, |
df7625d4 AK |
377 | uint32_t page_shift, uint64_t bus_offset, |
378 | uint32_t nb_table) | |
379 | { | |
380 | if (tcet->nb_table) { | |
3dc6f869 | 381 | warn_report("trying to enable already enabled TCE table"); |
df7625d4 AK |
382 | return; |
383 | } | |
384 | ||
385 | tcet->bus_offset = bus_offset; | |
386 | tcet->page_shift = page_shift; | |
387 | tcet->nb_table = nb_table; | |
388 | tcet->table = spapr_tce_alloc_table(tcet->liobn, | |
389 | tcet->page_shift, | |
d6ee2a7c | 390 | tcet->bus_offset, |
df7625d4 AK |
391 | tcet->nb_table, |
392 | &tcet->fd, | |
393 | tcet->need_vfio); | |
394 | ||
3df9d748 | 395 | memory_region_set_size(MEMORY_REGION(&tcet->iommu), |
df7625d4 | 396 | (uint64_t)tcet->nb_table << tcet->page_shift); |
3df9d748 AK |
397 | memory_region_add_subregion(&tcet->root, tcet->bus_offset, |
398 | MEMORY_REGION(&tcet->iommu)); | |
df7625d4 AK |
399 | } |
400 | ||
ce2918cb | 401 | void spapr_tce_table_disable(SpaprTceTable *tcet) |
df7625d4 AK |
402 | { |
403 | if (!tcet->nb_table) { | |
404 | return; | |
405 | } | |
406 | ||
3df9d748 AK |
407 | memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu)); |
408 | memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0); | |
df7625d4 AK |
409 | |
410 | spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table); | |
411 | tcet->fd = -1; | |
412 | tcet->table = NULL; | |
413 | tcet->bus_offset = 0; | |
414 | tcet->page_shift = 0; | |
415 | tcet->nb_table = 0; | |
416 | } | |
417 | ||
5f9490de | 418 | static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) |
ad0ebb91 | 419 | { |
ce2918cb | 420 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
a83000f5 | 421 | |
ea359d20 GK |
422 | vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet); |
423 | ||
2b7dc949 | 424 | QLIST_REMOVE(tcet, list); |
ad0ebb91 | 425 | |
df7625d4 | 426 | spapr_tce_table_disable(tcet); |
ad0ebb91 DG |
427 | } |
428 | ||
ce2918cb | 429 | MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet) |
a84bb436 | 430 | { |
b4b6eb77 | 431 | return &tcet->root; |
a84bb436 PB |
432 | } |
433 | ||
a83000f5 | 434 | static void spapr_tce_reset(DeviceState *dev) |
eddeed26 | 435 | { |
ce2918cb | 436 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
523e7b8a | 437 | size_t table_size = tcet->nb_table * sizeof(uint64_t); |
eddeed26 | 438 | |
57c0eb1e DG |
439 | if (tcet->nb_table) { |
440 | memset(tcet->table, 0, table_size); | |
441 | } | |
eddeed26 DG |
442 | } |
443 | ||
ce2918cb | 444 | static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba, |
edded454 DG |
445 | target_ulong tce) |
446 | { | |
a84bb436 | 447 | IOMMUTLBEntry entry; |
650f33ad | 448 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
1b8eceee | 449 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
edded454 | 450 | |
1b8eceee | 451 | if (index >= tcet->nb_table) { |
b55519a0 | 452 | hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x" |
edded454 DG |
453 | TARGET_FMT_lx "\n", ioba); |
454 | return H_PARAMETER; | |
455 | } | |
456 | ||
1b8eceee | 457 | tcet->table[index] = tce; |
edded454 | 458 | |
a84bb436 | 459 | entry.target_as = &address_space_memory, |
d78c19b5 | 460 | entry.iova = (ioba - tcet->bus_offset) & page_mask; |
650f33ad AK |
461 | entry.translated_addr = tce & page_mask; |
462 | entry.addr_mask = ~page_mask; | |
5709af3b | 463 | entry.perm = spapr_tce_iommu_access_flags(tce); |
cb1efcf4 | 464 | memory_region_notify_iommu(&tcet->iommu, 0, entry); |
a84bb436 | 465 | |
edded454 DG |
466 | return H_SUCCESS; |
467 | } | |
ad0ebb91 | 468 | |
da95324e | 469 | static target_ulong h_put_tce_indirect(PowerPCCPU *cpu, |
ce2918cb | 470 | SpaprMachineState *spapr, |
da95324e AK |
471 | target_ulong opcode, target_ulong *args) |
472 | { | |
473 | int i; | |
474 | target_ulong liobn = args[0]; | |
475 | target_ulong ioba = args[1]; | |
476 | target_ulong ioba1 = ioba; | |
477 | target_ulong tce_list = args[2]; | |
478 | target_ulong npages = args[3]; | |
f1215ea7 | 479 | target_ulong ret = H_PARAMETER, tce = 0; |
ce2918cb | 480 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
da95324e | 481 | CPUState *cs = CPU(cpu); |
650f33ad | 482 | hwaddr page_mask, page_size; |
da95324e AK |
483 | |
484 | if (!tcet) { | |
485 | return H_PARAMETER; | |
486 | } | |
487 | ||
650f33ad | 488 | if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) { |
da95324e AK |
489 | return H_PARAMETER; |
490 | } | |
491 | ||
650f33ad AK |
492 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
493 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
494 | ioba &= page_mask; | |
495 | ||
496 | for (i = 0; i < npages; ++i, ioba += page_size) { | |
4d9ab7d4 | 497 | tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong)); |
da95324e | 498 | |
da95324e AK |
499 | ret = put_tce_emu(tcet, ioba, tce); |
500 | if (ret) { | |
501 | break; | |
502 | } | |
503 | } | |
504 | ||
505 | /* Trace last successful or the first problematic entry */ | |
506 | i = i ? (i - 1) : 0; | |
d9d96a3c AK |
507 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
508 | trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
509 | } else { | |
510 | trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
511 | } | |
da95324e AK |
512 | return ret; |
513 | } | |
514 | ||
ce2918cb | 515 | static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
da95324e AK |
516 | target_ulong opcode, target_ulong *args) |
517 | { | |
518 | int i; | |
519 | target_ulong liobn = args[0]; | |
520 | target_ulong ioba = args[1]; | |
521 | target_ulong tce_value = args[2]; | |
522 | target_ulong npages = args[3]; | |
523 | target_ulong ret = H_PARAMETER; | |
ce2918cb | 524 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
650f33ad | 525 | hwaddr page_mask, page_size; |
da95324e AK |
526 | |
527 | if (!tcet) { | |
528 | return H_PARAMETER; | |
529 | } | |
530 | ||
531 | if (npages > tcet->nb_table) { | |
532 | return H_PARAMETER; | |
533 | } | |
534 | ||
650f33ad AK |
535 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
536 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
537 | ioba &= page_mask; | |
da95324e | 538 | |
650f33ad | 539 | for (i = 0; i < npages; ++i, ioba += page_size) { |
da95324e AK |
540 | ret = put_tce_emu(tcet, ioba, tce_value); |
541 | if (ret) { | |
542 | break; | |
543 | } | |
544 | } | |
d9d96a3c AK |
545 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
546 | trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret); | |
547 | } else { | |
548 | trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret); | |
549 | } | |
da95324e AK |
550 | |
551 | return ret; | |
552 | } | |
553 | ||
ce2918cb | 554 | static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
ad0ebb91 DG |
555 | target_ulong opcode, target_ulong *args) |
556 | { | |
557 | target_ulong liobn = args[0]; | |
558 | target_ulong ioba = args[1]; | |
559 | target_ulong tce = args[2]; | |
7e472264 | 560 | target_ulong ret = H_PARAMETER; |
ce2918cb | 561 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
ad0ebb91 | 562 | |
edded454 | 563 | if (tcet) { |
650f33ad AK |
564 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
565 | ||
566 | ioba &= page_mask; | |
567 | ||
7e472264 | 568 | ret = put_tce_emu(tcet, ioba, tce); |
edded454 | 569 | } |
d9d96a3c AK |
570 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
571 | trace_spapr_iommu_pci_put(liobn, ioba, tce, ret); | |
572 | } else { | |
573 | trace_spapr_iommu_put(liobn, ioba, tce, ret); | |
574 | } | |
ad0ebb91 | 575 | |
7e472264 | 576 | return ret; |
ad0ebb91 DG |
577 | } |
578 | ||
ce2918cb | 579 | static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba, |
a0fcac9c LD |
580 | target_ulong *tce) |
581 | { | |
1b8eceee AK |
582 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
583 | ||
584 | if (index >= tcet->nb_table) { | |
a0fcac9c LD |
585 | hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x" |
586 | TARGET_FMT_lx "\n", ioba); | |
587 | return H_PARAMETER; | |
588 | } | |
589 | ||
1b8eceee | 590 | *tce = tcet->table[index]; |
a0fcac9c LD |
591 | |
592 | return H_SUCCESS; | |
593 | } | |
594 | ||
ce2918cb | 595 | static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
a0fcac9c LD |
596 | target_ulong opcode, target_ulong *args) |
597 | { | |
598 | target_ulong liobn = args[0]; | |
599 | target_ulong ioba = args[1]; | |
600 | target_ulong tce = 0; | |
601 | target_ulong ret = H_PARAMETER; | |
ce2918cb | 602 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
a0fcac9c | 603 | |
a0fcac9c | 604 | if (tcet) { |
650f33ad AK |
605 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
606 | ||
607 | ioba &= page_mask; | |
608 | ||
a0fcac9c LD |
609 | ret = get_tce_emu(tcet, ioba, &tce); |
610 | if (!ret) { | |
611 | args[0] = tce; | |
612 | } | |
613 | } | |
d9d96a3c AK |
614 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
615 | trace_spapr_iommu_pci_get(liobn, ioba, ret, tce); | |
616 | } else { | |
617 | trace_spapr_iommu_get(liobn, ioba, ret, tce); | |
618 | } | |
a0fcac9c LD |
619 | |
620 | return ret; | |
621 | } | |
622 | ||
ad0ebb91 | 623 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
5c4cbcf2 | 624 | uint32_t liobn, uint64_t window, uint32_t size) |
ad0ebb91 | 625 | { |
5c4cbcf2 AK |
626 | uint32_t dma_prop[5]; |
627 | int ret; | |
628 | ||
629 | dma_prop[0] = cpu_to_be32(liobn); | |
630 | dma_prop[1] = cpu_to_be32(window >> 32); | |
631 | dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF); | |
632 | dma_prop[3] = 0; /* window size is 32 bits */ | |
633 | dma_prop[4] = cpu_to_be32(size); | |
634 | ||
635 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2); | |
636 | if (ret < 0) { | |
637 | return ret; | |
638 | } | |
ad0ebb91 | 639 | |
5c4cbcf2 AK |
640 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2); |
641 | if (ret < 0) { | |
642 | return ret; | |
643 | } | |
ad0ebb91 | 644 | |
5c4cbcf2 AK |
645 | ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop)); |
646 | if (ret < 0) { | |
647 | return ret; | |
ad0ebb91 DG |
648 | } |
649 | ||
650 | return 0; | |
651 | } | |
5c4cbcf2 AK |
652 | |
653 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, | |
ce2918cb | 654 | SpaprTceTable *tcet) |
5c4cbcf2 | 655 | { |
2b7dc949 | 656 | if (!tcet) { |
5c4cbcf2 AK |
657 | return 0; |
658 | } | |
659 | ||
2b7dc949 | 660 | return spapr_dma_dt(fdt, node_off, propname, |
650f33ad | 661 | tcet->liobn, 0, tcet->nb_table << tcet->page_shift); |
5c4cbcf2 | 662 | } |
a83000f5 AL |
663 | |
664 | static void spapr_tce_table_class_init(ObjectClass *klass, void *data) | |
665 | { | |
666 | DeviceClass *dc = DEVICE_CLASS(klass); | |
a931ad13 | 667 | dc->realize = spapr_tce_table_realize; |
a83000f5 | 668 | dc->reset = spapr_tce_reset; |
5f9490de | 669 | dc->unrealize = spapr_tce_table_unrealize; |
1f98e553 TH |
670 | /* Reason: This is just an internal device for handling the hypercalls */ |
671 | dc->user_creatable = false; | |
a83000f5 AL |
672 | |
673 | QLIST_INIT(&spapr_tce_tables); | |
674 | ||
675 | /* hcall-tce */ | |
676 | spapr_register_hypercall(H_PUT_TCE, h_put_tce); | |
a0fcac9c | 677 | spapr_register_hypercall(H_GET_TCE, h_get_tce); |
da95324e AK |
678 | spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect); |
679 | spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); | |
a83000f5 AL |
680 | } |
681 | ||
682 | static TypeInfo spapr_tce_table_info = { | |
683 | .name = TYPE_SPAPR_TCE_TABLE, | |
684 | .parent = TYPE_DEVICE, | |
ce2918cb | 685 | .instance_size = sizeof(SpaprTceTable), |
a83000f5 | 686 | .class_init = spapr_tce_table_class_init, |
a83000f5 AL |
687 | }; |
688 | ||
1221a474 AK |
689 | static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data) |
690 | { | |
691 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); | |
692 | ||
693 | imrc->translate = spapr_tce_translate_iommu; | |
5f366667 | 694 | imrc->replay = spapr_tce_replay; |
1221a474 AK |
695 | imrc->get_min_page_size = spapr_tce_get_min_page_size; |
696 | imrc->notify_flag_changed = spapr_tce_notify_flag_changed; | |
9ded780c | 697 | imrc->get_attr = spapr_tce_get_attr; |
1221a474 AK |
698 | } |
699 | ||
700 | static const TypeInfo spapr_iommu_memory_region_info = { | |
701 | .parent = TYPE_IOMMU_MEMORY_REGION, | |
702 | .name = TYPE_SPAPR_IOMMU_MEMORY_REGION, | |
703 | .class_init = spapr_iommu_memory_region_class_init, | |
704 | }; | |
705 | ||
a83000f5 AL |
706 | static void register_types(void) |
707 | { | |
708 | type_register_static(&spapr_tce_table_info); | |
1221a474 | 709 | type_register_static(&spapr_iommu_memory_region_info); |
a83000f5 AL |
710 | } |
711 | ||
712 | type_init(register_types); |