]> git.proxmox.com Git - mirror_qemu.git/blame - hw/ppc/spapr_iommu.c
spapr_iommu: drop erroneous check in h_put_tce_indirect()
[mirror_qemu.git] / hw / ppc / spapr_iommu.c
CommitLineData
ad0ebb91
DG
1/*
2 * QEMU sPAPR IOMMU (TCE) code
3 *
4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
83c9f4ca 19#include "hw/hw.h"
9c17d615 20#include "sysemu/kvm.h"
83c9f4ca 21#include "hw/qdev.h"
ad0ebb91 22#include "kvm_ppc.h"
9c17d615 23#include "sysemu/dma.h"
022c62cb 24#include "exec/address-spaces.h"
7e472264 25#include "trace.h"
ad0ebb91 26
0d09e41a 27#include "hw/ppc/spapr.h"
ee9a569a 28#include "hw/ppc/spapr_vio.h"
ad0ebb91
DG
29
30#include <libfdt.h>
31
ad0ebb91
DG
32enum sPAPRTCEAccess {
33 SPAPR_TCE_FAULT = 0,
34 SPAPR_TCE_RO = 1,
35 SPAPR_TCE_WO = 2,
36 SPAPR_TCE_RW = 3,
37};
38
650f33ad
AK
39#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
40#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
41
6a0a70b0 42static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
ad0ebb91 43
f9ce8e0a 44sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
ad0ebb91
DG
45{
46 sPAPRTCETable *tcet;
47
d4261662
DG
48 if (liobn & 0xFFFFFFFF00000000ULL) {
49 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
50 liobn);
51 return NULL;
52 }
53
ad0ebb91 54 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
f9ce8e0a 55 if (tcet->liobn == (uint32_t)liobn) {
ad0ebb91
DG
56 return tcet;
57 }
58 }
59
60 return NULL;
61}
62
79e2b9ae 63/* Called from RCU critical section */
8d7b8cb9
LT
64static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr,
65 bool is_write)
ad0ebb91 66{
a84bb436 67 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
ad0ebb91 68 uint64_t tce;
7e472264
AK
69 IOMMUTLBEntry ret = {
70 .target_as = &address_space_memory,
71 .iova = 0,
72 .translated_addr = 0,
73 .addr_mask = ~(hwaddr)0,
74 .perm = IOMMU_NONE,
75 };
ad0ebb91 76
ee9a569a 77 if ((addr >> tcet->page_shift) < tcet->nb_table) {
7e472264 78 /* Check if we are in bound */
650f33ad
AK
79 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
80
81 tce = tcet->table[addr >> tcet->page_shift];
82 ret.iova = addr & page_mask;
83 ret.translated_addr = tce & page_mask;
84 ret.addr_mask = ~page_mask;
27e27782 85 ret.perm = tce & IOMMU_RW;
ad0ebb91 86 }
7e472264
AK
87 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
88 ret.addr_mask);
ad0ebb91 89
7e472264 90 return ret;
a71bfbfe
PB
91}
92
ee9a569a
AK
93static int spapr_tce_table_post_load(void *opaque, int version_id)
94{
95 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
96
97 if (tcet->vdev) {
98 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
99 }
100
101 return 0;
102}
103
a83000f5
AL
104static const VMStateDescription vmstate_spapr_tce_table = {
105 .name = "spapr_iommu",
523e7b8a
AK
106 .version_id = 2,
107 .minimum_version_id = 2,
ee9a569a 108 .post_load = spapr_tce_table_post_load,
523e7b8a 109 .fields = (VMStateField []) {
a83000f5
AL
110 /* Sanity check */
111 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable),
523e7b8a 112 VMSTATE_UINT32_EQUAL(nb_table, sPAPRTCETable),
a83000f5
AL
113
114 /* IOMMU state */
115 VMSTATE_BOOL(bypass, sPAPRTCETable),
116 VMSTATE_VARRAY_UINT32(table, sPAPRTCETable, nb_table, 0, vmstate_info_uint64, uint64_t),
117
118 VMSTATE_END_OF_LIST()
119 },
120};
121
a84bb436
PB
122static MemoryRegionIOMMUOps spapr_iommu_ops = {
123 .translate = spapr_tce_translate_iommu,
124};
ad0ebb91 125
a83000f5 126static int spapr_tce_table_realize(DeviceState *dev)
ad0ebb91 127{
a83000f5 128 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
12fd2853 129 uint64_t window_size = (uint64_t)tcet->nb_table << tcet->page_shift;
ad0ebb91 130
12fd2853 131 if (kvm_enabled() && !(window_size >> 32)) {
a83000f5 132 tcet->table = kvmppc_create_spapr_tce(tcet->liobn,
12fd2853 133 window_size,
9bb62a07
AK
134 &tcet->fd,
135 tcet->vfio_accel);
ad0ebb91
DG
136 }
137
138 if (!tcet->table) {
523e7b8a 139 size_t table_size = tcet->nb_table * sizeof(uint64_t);
ad0ebb91
DG
140 tcet->table = g_malloc0(table_size);
141 }
142
7e472264 143 trace_spapr_iommu_new_table(tcet->liobn, tcet, tcet->table, tcet->fd);
ad0ebb91 144
a83000f5 145 memory_region_init_iommu(&tcet->iommu, OBJECT(dev), &spapr_iommu_ops,
ee9a569a
AK
146 "iommu-spapr",
147 (uint64_t)tcet->nb_table << tcet->page_shift);
a84bb436 148
ad0ebb91
DG
149 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
150
00d4f525
AK
151 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
152 tcet);
153
a83000f5
AL
154 return 0;
155}
156
523e7b8a 157sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
1b8eceee 158 uint64_t bus_offset,
650f33ad 159 uint32_t page_shift,
9bb62a07
AK
160 uint32_t nb_table,
161 bool vfio_accel)
a83000f5
AL
162{
163 sPAPRTCETable *tcet;
dea1b3ce 164 char tmp[64];
a83000f5
AL
165
166 if (spapr_tce_find_by_liobn(liobn)) {
167 fprintf(stderr, "Attempted to create TCE table with duplicate"
168 " LIOBN 0x%x\n", liobn);
169 return NULL;
170 }
171
523e7b8a 172 if (!nb_table) {
a83000f5
AL
173 return NULL;
174 }
175
176 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
177 tcet->liobn = liobn;
1b8eceee 178 tcet->bus_offset = bus_offset;
650f33ad 179 tcet->page_shift = page_shift;
523e7b8a 180 tcet->nb_table = nb_table;
9bb62a07 181 tcet->vfio_accel = vfio_accel;
a83000f5 182
dea1b3ce
AK
183 snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn);
184 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
a83000f5 185
e4c35b78 186 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
a83000f5 187
2b7dc949 188 return tcet;
ad0ebb91
DG
189}
190
5f9490de 191static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
ad0ebb91 192{
5f9490de 193 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
a83000f5 194
2b7dc949 195 QLIST_REMOVE(tcet, list);
ad0ebb91 196
2b7dc949
PB
197 if (!kvm_enabled() ||
198 (kvmppc_remove_spapr_tce(tcet->table, tcet->fd,
523e7b8a 199 tcet->nb_table) != 0)) {
2b7dc949 200 g_free(tcet->table);
ad0ebb91
DG
201 }
202}
203
a84bb436
PB
204MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
205{
206 return &tcet->iommu;
207}
208
a83000f5 209static void spapr_tce_reset(DeviceState *dev)
eddeed26 210{
a83000f5 211 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
523e7b8a 212 size_t table_size = tcet->nb_table * sizeof(uint64_t);
eddeed26 213
53724ee5 214 memset(tcet->table, 0, table_size);
eddeed26
DG
215}
216
edded454
DG
217static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
218 target_ulong tce)
219{
a84bb436 220 IOMMUTLBEntry entry;
650f33ad 221 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
1b8eceee 222 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
edded454 223
1b8eceee 224 if (index >= tcet->nb_table) {
b55519a0 225 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
edded454
DG
226 TARGET_FMT_lx "\n", ioba);
227 return H_PARAMETER;
228 }
229
1b8eceee 230 tcet->table[index] = tce;
edded454 231
a84bb436 232 entry.target_as = &address_space_memory,
650f33ad
AK
233 entry.iova = ioba & page_mask;
234 entry.translated_addr = tce & page_mask;
235 entry.addr_mask = ~page_mask;
27e27782 236 entry.perm = tce & IOMMU_RW;
a84bb436
PB
237 memory_region_notify_iommu(&tcet->iommu, entry);
238
edded454
DG
239 return H_SUCCESS;
240}
ad0ebb91 241
da95324e 242static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
28e02042 243 sPAPRMachineState *spapr,
da95324e
AK
244 target_ulong opcode, target_ulong *args)
245{
246 int i;
247 target_ulong liobn = args[0];
248 target_ulong ioba = args[1];
249 target_ulong ioba1 = ioba;
250 target_ulong tce_list = args[2];
251 target_ulong npages = args[3];
f1215ea7 252 target_ulong ret = H_PARAMETER, tce = 0;
da95324e
AK
253 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
254 CPUState *cs = CPU(cpu);
650f33ad 255 hwaddr page_mask, page_size;
da95324e
AK
256
257 if (!tcet) {
258 return H_PARAMETER;
259 }
260
650f33ad 261 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
da95324e
AK
262 return H_PARAMETER;
263 }
264
650f33ad
AK
265 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
266 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
267 ioba &= page_mask;
268
269 for (i = 0; i < npages; ++i, ioba += page_size) {
4d9ab7d4 270 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
da95324e 271
da95324e
AK
272 ret = put_tce_emu(tcet, ioba, tce);
273 if (ret) {
274 break;
275 }
276 }
277
278 /* Trace last successful or the first problematic entry */
279 i = i ? (i - 1) : 0;
d9d96a3c
AK
280 if (SPAPR_IS_PCI_LIOBN(liobn)) {
281 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
282 } else {
283 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
284 }
da95324e
AK
285 return ret;
286}
287
28e02042 288static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
da95324e
AK
289 target_ulong opcode, target_ulong *args)
290{
291 int i;
292 target_ulong liobn = args[0];
293 target_ulong ioba = args[1];
294 target_ulong tce_value = args[2];
295 target_ulong npages = args[3];
296 target_ulong ret = H_PARAMETER;
297 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
650f33ad 298 hwaddr page_mask, page_size;
da95324e
AK
299
300 if (!tcet) {
301 return H_PARAMETER;
302 }
303
304 if (npages > tcet->nb_table) {
305 return H_PARAMETER;
306 }
307
650f33ad
AK
308 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
309 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
310 ioba &= page_mask;
da95324e 311
650f33ad 312 for (i = 0; i < npages; ++i, ioba += page_size) {
da95324e
AK
313 ret = put_tce_emu(tcet, ioba, tce_value);
314 if (ret) {
315 break;
316 }
317 }
d9d96a3c
AK
318 if (SPAPR_IS_PCI_LIOBN(liobn)) {
319 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
320 } else {
321 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
322 }
da95324e
AK
323
324 return ret;
325}
326
28e02042 327static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
ad0ebb91
DG
328 target_ulong opcode, target_ulong *args)
329{
330 target_ulong liobn = args[0];
331 target_ulong ioba = args[1];
332 target_ulong tce = args[2];
7e472264 333 target_ulong ret = H_PARAMETER;
ad0ebb91 334 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
ad0ebb91 335
edded454 336 if (tcet) {
650f33ad
AK
337 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
338
339 ioba &= page_mask;
340
7e472264 341 ret = put_tce_emu(tcet, ioba, tce);
edded454 342 }
d9d96a3c
AK
343 if (SPAPR_IS_PCI_LIOBN(liobn)) {
344 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
345 } else {
346 trace_spapr_iommu_put(liobn, ioba, tce, ret);
347 }
ad0ebb91 348
7e472264 349 return ret;
ad0ebb91
DG
350}
351
a0fcac9c
LD
352static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
353 target_ulong *tce)
354{
1b8eceee
AK
355 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
356
357 if (index >= tcet->nb_table) {
a0fcac9c
LD
358 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
359 TARGET_FMT_lx "\n", ioba);
360 return H_PARAMETER;
361 }
362
1b8eceee 363 *tce = tcet->table[index];
a0fcac9c
LD
364
365 return H_SUCCESS;
366}
367
28e02042 368static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
a0fcac9c
LD
369 target_ulong opcode, target_ulong *args)
370{
371 target_ulong liobn = args[0];
372 target_ulong ioba = args[1];
373 target_ulong tce = 0;
374 target_ulong ret = H_PARAMETER;
375 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
376
a0fcac9c 377 if (tcet) {
650f33ad
AK
378 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
379
380 ioba &= page_mask;
381
a0fcac9c
LD
382 ret = get_tce_emu(tcet, ioba, &tce);
383 if (!ret) {
384 args[0] = tce;
385 }
386 }
d9d96a3c
AK
387 if (SPAPR_IS_PCI_LIOBN(liobn)) {
388 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
389 } else {
390 trace_spapr_iommu_get(liobn, ioba, ret, tce);
391 }
a0fcac9c
LD
392
393 return ret;
394}
395
ad0ebb91 396int spapr_dma_dt(void *fdt, int node_off, const char *propname,
5c4cbcf2 397 uint32_t liobn, uint64_t window, uint32_t size)
ad0ebb91 398{
5c4cbcf2
AK
399 uint32_t dma_prop[5];
400 int ret;
401
402 dma_prop[0] = cpu_to_be32(liobn);
403 dma_prop[1] = cpu_to_be32(window >> 32);
404 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
405 dma_prop[3] = 0; /* window size is 32 bits */
406 dma_prop[4] = cpu_to_be32(size);
407
408 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
409 if (ret < 0) {
410 return ret;
411 }
ad0ebb91 412
5c4cbcf2
AK
413 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
414 if (ret < 0) {
415 return ret;
416 }
ad0ebb91 417
5c4cbcf2
AK
418 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
419 if (ret < 0) {
420 return ret;
ad0ebb91
DG
421 }
422
423 return 0;
424}
5c4cbcf2
AK
425
426int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
2b7dc949 427 sPAPRTCETable *tcet)
5c4cbcf2 428{
2b7dc949 429 if (!tcet) {
5c4cbcf2
AK
430 return 0;
431 }
432
2b7dc949 433 return spapr_dma_dt(fdt, node_off, propname,
650f33ad 434 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
5c4cbcf2 435}
a83000f5
AL
436
437static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
438{
439 DeviceClass *dc = DEVICE_CLASS(klass);
a83000f5
AL
440 dc->init = spapr_tce_table_realize;
441 dc->reset = spapr_tce_reset;
5f9490de 442 dc->unrealize = spapr_tce_table_unrealize;
a83000f5
AL
443
444 QLIST_INIT(&spapr_tce_tables);
445
446 /* hcall-tce */
447 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
a0fcac9c 448 spapr_register_hypercall(H_GET_TCE, h_get_tce);
da95324e
AK
449 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
450 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
a83000f5
AL
451}
452
453static TypeInfo spapr_tce_table_info = {
454 .name = TYPE_SPAPR_TCE_TABLE,
455 .parent = TYPE_DEVICE,
456 .instance_size = sizeof(sPAPRTCETable),
457 .class_init = spapr_tce_table_class_init,
a83000f5
AL
458};
459
460static void register_types(void)
461{
462 type_register_static(&spapr_tce_table_info);
463}
464
465type_init(register_types);