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Commit | Line | Data |
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ad0ebb91 DG |
1 | /* |
2 | * QEMU sPAPR IOMMU (TCE) code | |
3 | * | |
4 | * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0b8fa32f | 19 | |
0d75590d | 20 | #include "qemu/osdep.h" |
df7625d4 | 21 | #include "qemu/error-report.h" |
03dd024f | 22 | #include "qemu/log.h" |
0b8fa32f | 23 | #include "qemu/module.h" |
9c17d615 | 24 | #include "sysemu/kvm.h" |
ad0ebb91 | 25 | #include "kvm_ppc.h" |
d6454270 | 26 | #include "migration/vmstate.h" |
9c17d615 | 27 | #include "sysemu/dma.h" |
022c62cb | 28 | #include "exec/address-spaces.h" |
7e472264 | 29 | #include "trace.h" |
ad0ebb91 | 30 | |
0d09e41a | 31 | #include "hw/ppc/spapr.h" |
ee9a569a | 32 | #include "hw/ppc/spapr_vio.h" |
ad0ebb91 DG |
33 | |
34 | #include <libfdt.h> | |
35 | ||
ce2918cb | 36 | enum SpaprTceAccess { |
ad0ebb91 DG |
37 | SPAPR_TCE_FAULT = 0, |
38 | SPAPR_TCE_RO = 1, | |
39 | SPAPR_TCE_WO = 2, | |
40 | SPAPR_TCE_RW = 3, | |
41 | }; | |
42 | ||
650f33ad AK |
43 | #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift)) |
44 | #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1)) | |
45 | ||
ce2918cb | 46 | static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables; |
ad0ebb91 | 47 | |
ce2918cb | 48 | SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn) |
ad0ebb91 | 49 | { |
ce2918cb | 50 | SpaprTceTable *tcet; |
ad0ebb91 | 51 | |
d4261662 DG |
52 | if (liobn & 0xFFFFFFFF00000000ULL) { |
53 | hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n", | |
54 | liobn); | |
55 | return NULL; | |
56 | } | |
57 | ||
ad0ebb91 | 58 | QLIST_FOREACH(tcet, &spapr_tce_tables, list) { |
f9ce8e0a | 59 | if (tcet->liobn == (uint32_t)liobn) { |
ad0ebb91 DG |
60 | return tcet; |
61 | } | |
62 | } | |
63 | ||
64 | return NULL; | |
65 | } | |
66 | ||
5709af3b GK |
67 | static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce) |
68 | { | |
69 | switch (tce & SPAPR_TCE_RW) { | |
70 | case SPAPR_TCE_FAULT: | |
71 | return IOMMU_NONE; | |
72 | case SPAPR_TCE_RO: | |
73 | return IOMMU_RO; | |
74 | case SPAPR_TCE_WO: | |
75 | return IOMMU_WO; | |
76 | default: /* SPAPR_TCE_RW */ | |
77 | return IOMMU_RW; | |
78 | } | |
79 | } | |
80 | ||
fec5d3a1 AK |
81 | static uint64_t *spapr_tce_alloc_table(uint32_t liobn, |
82 | uint32_t page_shift, | |
d6ee2a7c | 83 | uint64_t bus_offset, |
fec5d3a1 AK |
84 | uint32_t nb_table, |
85 | int *fd, | |
86 | bool need_vfio) | |
87 | { | |
88 | uint64_t *table = NULL; | |
fec5d3a1 | 89 | |
d6ee2a7c AK |
90 | if (kvm_enabled()) { |
91 | table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table, | |
92 | fd, need_vfio); | |
fec5d3a1 AK |
93 | } |
94 | ||
95 | if (!table) { | |
96 | *fd = -1; | |
dec4ec40 | 97 | table = g_new0(uint64_t, nb_table); |
fec5d3a1 AK |
98 | } |
99 | ||
100 | trace_spapr_iommu_new_table(liobn, table, *fd); | |
101 | ||
102 | return table; | |
103 | } | |
104 | ||
105 | static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) | |
106 | { | |
107 | if (!kvm_enabled() || | |
108 | (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) { | |
109 | g_free(table); | |
110 | } | |
111 | } | |
112 | ||
79e2b9ae | 113 | /* Called from RCU critical section */ |
3df9d748 AK |
114 | static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu, |
115 | hwaddr addr, | |
2c91bcf2 PM |
116 | IOMMUAccessFlags flag, |
117 | int iommu_idx) | |
ad0ebb91 | 118 | { |
ce2918cb | 119 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
ad0ebb91 | 120 | uint64_t tce; |
7e472264 AK |
121 | IOMMUTLBEntry ret = { |
122 | .target_as = &address_space_memory, | |
123 | .iova = 0, | |
124 | .translated_addr = 0, | |
125 | .addr_mask = ~(hwaddr)0, | |
126 | .perm = IOMMU_NONE, | |
127 | }; | |
ad0ebb91 | 128 | |
ee9a569a | 129 | if ((addr >> tcet->page_shift) < tcet->nb_table) { |
7e472264 | 130 | /* Check if we are in bound */ |
650f33ad AK |
131 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
132 | ||
133 | tce = tcet->table[addr >> tcet->page_shift]; | |
134 | ret.iova = addr & page_mask; | |
135 | ret.translated_addr = tce & page_mask; | |
136 | ret.addr_mask = ~page_mask; | |
5709af3b | 137 | ret.perm = spapr_tce_iommu_access_flags(tce); |
ad0ebb91 | 138 | } |
a14f04eb | 139 | trace_spapr_iommu_xlate(tcet->liobn, addr, ret.translated_addr, ret.perm, |
7e472264 | 140 | ret.addr_mask); |
ad0ebb91 | 141 | |
7e472264 | 142 | return ret; |
a71bfbfe PB |
143 | } |
144 | ||
5f366667 AK |
145 | static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) |
146 | { | |
147 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); | |
148 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
149 | hwaddr addr, granularity; | |
150 | IOMMUTLBEntry iotlb; | |
ce2918cb | 151 | SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu); |
5f366667 AK |
152 | |
153 | if (tcet->skipping_replay) { | |
154 | return; | |
155 | } | |
156 | ||
157 | granularity = memory_region_iommu_get_min_page_size(iommu_mr); | |
158 | ||
159 | for (addr = 0; addr < memory_region_size(mr); addr += granularity) { | |
160 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx); | |
161 | if (iotlb.perm != IOMMU_NONE) { | |
162 | n->notify(n, &iotlb); | |
163 | } | |
164 | ||
165 | /* | |
166 | * if (2^64 - MR size) < granularity, it's possible to get an | |
167 | * infinite loop here. This should catch such a wraparound. | |
168 | */ | |
169 | if ((addr + granularity) < addr) { | |
170 | break; | |
171 | } | |
172 | } | |
173 | } | |
174 | ||
44b1ff31 | 175 | static int spapr_tce_table_pre_save(void *opaque) |
a26fdf39 | 176 | { |
ce2918cb | 177 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque); |
a26fdf39 AK |
178 | |
179 | tcet->mig_table = tcet->table; | |
180 | tcet->mig_nb_table = tcet->nb_table; | |
181 | ||
182 | trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table, | |
183 | tcet->bus_offset, tcet->page_shift); | |
44b1ff31 DDAG |
184 | |
185 | return 0; | |
a26fdf39 AK |
186 | } |
187 | ||
3df9d748 | 188 | static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu) |
f682e9c2 | 189 | { |
ce2918cb | 190 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
f682e9c2 AK |
191 | |
192 | return 1ULL << tcet->page_shift; | |
193 | } | |
194 | ||
9ded780c AK |
195 | static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu, |
196 | enum IOMMUMemoryRegionAttr attr, void *data) | |
197 | { | |
ce2918cb | 198 | SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); |
9ded780c AK |
199 | |
200 | if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) { | |
201 | *(int *) data = tcet->fd; | |
202 | return 0; | |
203 | } | |
204 | ||
205 | return -EINVAL; | |
206 | } | |
207 | ||
549d4005 EA |
208 | static int spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu, |
209 | IOMMUNotifierFlag old, | |
210 | IOMMUNotifierFlag new, | |
211 | Error **errp) | |
606b5498 | 212 | { |
ce2918cb | 213 | struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu); |
606b5498 | 214 | |
5bf3d319 PX |
215 | if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) { |
216 | spapr_tce_set_need_vfio(tbl, true); | |
217 | } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) { | |
218 | spapr_tce_set_need_vfio(tbl, false); | |
219 | } | |
549d4005 | 220 | return 0; |
606b5498 AK |
221 | } |
222 | ||
ee9a569a AK |
223 | static int spapr_tce_table_post_load(void *opaque, int version_id) |
224 | { | |
ce2918cb | 225 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque); |
a26fdf39 AK |
226 | uint32_t old_nb_table = tcet->nb_table; |
227 | uint64_t old_bus_offset = tcet->bus_offset; | |
228 | uint32_t old_page_shift = tcet->page_shift; | |
ee9a569a AK |
229 | |
230 | if (tcet->vdev) { | |
231 | spapr_vio_set_bypass(tcet->vdev, tcet->bypass); | |
232 | } | |
233 | ||
a26fdf39 AK |
234 | if (tcet->mig_nb_table != tcet->nb_table) { |
235 | spapr_tce_table_disable(tcet); | |
236 | } | |
237 | ||
238 | if (tcet->mig_nb_table) { | |
239 | if (!tcet->nb_table) { | |
240 | spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset, | |
241 | tcet->mig_nb_table); | |
242 | } | |
243 | ||
244 | memcpy(tcet->table, tcet->mig_table, | |
245 | tcet->nb_table * sizeof(tcet->table[0])); | |
246 | ||
247 | free(tcet->mig_table); | |
248 | tcet->mig_table = NULL; | |
249 | } | |
250 | ||
251 | trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table, | |
252 | tcet->bus_offset, tcet->page_shift); | |
253 | ||
ee9a569a AK |
254 | return 0; |
255 | } | |
256 | ||
a26fdf39 AK |
257 | static bool spapr_tce_table_ex_needed(void *opaque) |
258 | { | |
ce2918cb | 259 | SpaprTceTable *tcet = opaque; |
a26fdf39 AK |
260 | |
261 | return tcet->bus_offset || tcet->page_shift != 0xC; | |
262 | } | |
263 | ||
264 | static const VMStateDescription vmstate_spapr_tce_table_ex = { | |
265 | .name = "spapr_iommu_ex", | |
266 | .version_id = 1, | |
267 | .minimum_version_id = 1, | |
268 | .needed = spapr_tce_table_ex_needed, | |
269 | .fields = (VMStateField[]) { | |
ce2918cb DG |
270 | VMSTATE_UINT64(bus_offset, SpaprTceTable), |
271 | VMSTATE_UINT32(page_shift, SpaprTceTable), | |
a26fdf39 AK |
272 | VMSTATE_END_OF_LIST() |
273 | }, | |
274 | }; | |
275 | ||
a83000f5 AL |
276 | static const VMStateDescription vmstate_spapr_tce_table = { |
277 | .name = "spapr_iommu", | |
523e7b8a AK |
278 | .version_id = 2, |
279 | .minimum_version_id = 2, | |
a26fdf39 | 280 | .pre_save = spapr_tce_table_pre_save, |
ee9a569a | 281 | .post_load = spapr_tce_table_post_load, |
523e7b8a | 282 | .fields = (VMStateField []) { |
a83000f5 | 283 | /* Sanity check */ |
ce2918cb | 284 | VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL), |
a83000f5 AL |
285 | |
286 | /* IOMMU state */ | |
ce2918cb DG |
287 | VMSTATE_UINT32(mig_nb_table, SpaprTceTable), |
288 | VMSTATE_BOOL(bypass, SpaprTceTable), | |
289 | VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0, | |
a26fdf39 | 290 | vmstate_info_uint64, uint64_t), |
a83000f5 AL |
291 | |
292 | VMSTATE_END_OF_LIST() | |
293 | }, | |
a26fdf39 AK |
294 | .subsections = (const VMStateDescription*[]) { |
295 | &vmstate_spapr_tce_table_ex, | |
296 | NULL | |
297 | } | |
a83000f5 AL |
298 | }; |
299 | ||
a931ad13 | 300 | static void spapr_tce_table_realize(DeviceState *dev, Error **errp) |
ad0ebb91 | 301 | { |
ce2918cb | 302 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
b4b6eb77 | 303 | Object *tcetobj = OBJECT(tcet); |
a205a053 | 304 | gchar *tmp; |
ad0ebb91 | 305 | |
fec5d3a1 | 306 | tcet->fd = -1; |
df7625d4 | 307 | tcet->need_vfio = false; |
a205a053 | 308 | tmp = g_strdup_printf("tce-root-%x", tcet->liobn); |
b4b6eb77 | 309 | memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX); |
a205a053 | 310 | g_free(tmp); |
b4b6eb77 | 311 | |
a205a053 | 312 | tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn); |
1221a474 AK |
313 | memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu), |
314 | TYPE_SPAPR_IOMMU_MEMORY_REGION, | |
315 | tcetobj, tmp, 0); | |
a205a053 | 316 | g_free(tmp); |
a84bb436 | 317 | |
ad0ebb91 DG |
318 | QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); |
319 | ||
00d4f525 AK |
320 | vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table, |
321 | tcet); | |
a83000f5 AL |
322 | } |
323 | ||
ce2918cb | 324 | void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio) |
c10325d6 DG |
325 | { |
326 | size_t table_size = tcet->nb_table * sizeof(uint64_t); | |
f5509b6b AK |
327 | uint64_t *oldtable; |
328 | int newfd = -1; | |
c10325d6 | 329 | |
f5509b6b | 330 | g_assert(need_vfio != tcet->need_vfio); |
c10325d6 | 331 | |
f5509b6b | 332 | tcet->need_vfio = need_vfio; |
c10325d6 | 333 | |
9ded780c AK |
334 | if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) { |
335 | return; | |
336 | } | |
337 | ||
f5509b6b | 338 | oldtable = tcet->table; |
c10325d6 | 339 | |
f5509b6b AK |
340 | tcet->table = spapr_tce_alloc_table(tcet->liobn, |
341 | tcet->page_shift, | |
342 | tcet->bus_offset, | |
343 | tcet->nb_table, | |
344 | &newfd, | |
345 | need_vfio); | |
346 | memcpy(tcet->table, oldtable, table_size); | |
c10325d6 | 347 | |
f5509b6b | 348 | spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table); |
c10325d6 | 349 | |
f5509b6b | 350 | tcet->fd = newfd; |
c10325d6 DG |
351 | } |
352 | ||
ce2918cb | 353 | SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn) |
a83000f5 | 354 | { |
ce2918cb | 355 | SpaprTceTable *tcet; |
a205a053 | 356 | gchar *tmp; |
a83000f5 AL |
357 | |
358 | if (spapr_tce_find_by_liobn(liobn)) { | |
ce9863b7 CLG |
359 | error_report("Attempted to create TCE table with duplicate" |
360 | " LIOBN 0x%x", liobn); | |
a83000f5 AL |
361 | return NULL; |
362 | } | |
363 | ||
a83000f5 AL |
364 | tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); |
365 | tcet->liobn = liobn; | |
a83000f5 | 366 | |
a205a053 | 367 | tmp = g_strdup_printf("tce-table-%x", liobn); |
dea1b3ce | 368 | object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); |
a205a053 | 369 | g_free(tmp); |
8dc9785c | 370 | object_unref(OBJECT(tcet)); |
a83000f5 | 371 | |
e4c35b78 | 372 | object_property_set_bool(OBJECT(tcet), true, "realized", NULL); |
a83000f5 | 373 | |
2b7dc949 | 374 | return tcet; |
ad0ebb91 DG |
375 | } |
376 | ||
ce2918cb | 377 | void spapr_tce_table_enable(SpaprTceTable *tcet, |
df7625d4 AK |
378 | uint32_t page_shift, uint64_t bus_offset, |
379 | uint32_t nb_table) | |
380 | { | |
381 | if (tcet->nb_table) { | |
3dc6f869 | 382 | warn_report("trying to enable already enabled TCE table"); |
df7625d4 AK |
383 | return; |
384 | } | |
385 | ||
386 | tcet->bus_offset = bus_offset; | |
387 | tcet->page_shift = page_shift; | |
388 | tcet->nb_table = nb_table; | |
389 | tcet->table = spapr_tce_alloc_table(tcet->liobn, | |
390 | tcet->page_shift, | |
d6ee2a7c | 391 | tcet->bus_offset, |
df7625d4 AK |
392 | tcet->nb_table, |
393 | &tcet->fd, | |
394 | tcet->need_vfio); | |
395 | ||
3df9d748 | 396 | memory_region_set_size(MEMORY_REGION(&tcet->iommu), |
df7625d4 | 397 | (uint64_t)tcet->nb_table << tcet->page_shift); |
3df9d748 AK |
398 | memory_region_add_subregion(&tcet->root, tcet->bus_offset, |
399 | MEMORY_REGION(&tcet->iommu)); | |
df7625d4 AK |
400 | } |
401 | ||
ce2918cb | 402 | void spapr_tce_table_disable(SpaprTceTable *tcet) |
df7625d4 AK |
403 | { |
404 | if (!tcet->nb_table) { | |
405 | return; | |
406 | } | |
407 | ||
3df9d748 AK |
408 | memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu)); |
409 | memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0); | |
df7625d4 AK |
410 | |
411 | spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table); | |
412 | tcet->fd = -1; | |
413 | tcet->table = NULL; | |
414 | tcet->bus_offset = 0; | |
415 | tcet->page_shift = 0; | |
416 | tcet->nb_table = 0; | |
417 | } | |
418 | ||
5f9490de | 419 | static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) |
ad0ebb91 | 420 | { |
ce2918cb | 421 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
a83000f5 | 422 | |
ea359d20 GK |
423 | vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet); |
424 | ||
2b7dc949 | 425 | QLIST_REMOVE(tcet, list); |
ad0ebb91 | 426 | |
df7625d4 | 427 | spapr_tce_table_disable(tcet); |
ad0ebb91 DG |
428 | } |
429 | ||
ce2918cb | 430 | MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet) |
a84bb436 | 431 | { |
b4b6eb77 | 432 | return &tcet->root; |
a84bb436 PB |
433 | } |
434 | ||
a83000f5 | 435 | static void spapr_tce_reset(DeviceState *dev) |
eddeed26 | 436 | { |
ce2918cb | 437 | SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev); |
523e7b8a | 438 | size_t table_size = tcet->nb_table * sizeof(uint64_t); |
eddeed26 | 439 | |
57c0eb1e DG |
440 | if (tcet->nb_table) { |
441 | memset(tcet->table, 0, table_size); | |
442 | } | |
eddeed26 DG |
443 | } |
444 | ||
ce2918cb | 445 | static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba, |
edded454 DG |
446 | target_ulong tce) |
447 | { | |
a84bb436 | 448 | IOMMUTLBEntry entry; |
650f33ad | 449 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
1b8eceee | 450 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
edded454 | 451 | |
1b8eceee | 452 | if (index >= tcet->nb_table) { |
b55519a0 | 453 | hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x" |
edded454 DG |
454 | TARGET_FMT_lx "\n", ioba); |
455 | return H_PARAMETER; | |
456 | } | |
457 | ||
1b8eceee | 458 | tcet->table[index] = tce; |
edded454 | 459 | |
a84bb436 | 460 | entry.target_as = &address_space_memory, |
d78c19b5 | 461 | entry.iova = (ioba - tcet->bus_offset) & page_mask; |
650f33ad AK |
462 | entry.translated_addr = tce & page_mask; |
463 | entry.addr_mask = ~page_mask; | |
5709af3b | 464 | entry.perm = spapr_tce_iommu_access_flags(tce); |
cb1efcf4 | 465 | memory_region_notify_iommu(&tcet->iommu, 0, entry); |
a84bb436 | 466 | |
edded454 DG |
467 | return H_SUCCESS; |
468 | } | |
ad0ebb91 | 469 | |
da95324e | 470 | static target_ulong h_put_tce_indirect(PowerPCCPU *cpu, |
ce2918cb | 471 | SpaprMachineState *spapr, |
da95324e AK |
472 | target_ulong opcode, target_ulong *args) |
473 | { | |
474 | int i; | |
475 | target_ulong liobn = args[0]; | |
476 | target_ulong ioba = args[1]; | |
477 | target_ulong ioba1 = ioba; | |
478 | target_ulong tce_list = args[2]; | |
479 | target_ulong npages = args[3]; | |
f1215ea7 | 480 | target_ulong ret = H_PARAMETER, tce = 0; |
ce2918cb | 481 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
da95324e | 482 | CPUState *cs = CPU(cpu); |
650f33ad | 483 | hwaddr page_mask, page_size; |
da95324e AK |
484 | |
485 | if (!tcet) { | |
486 | return H_PARAMETER; | |
487 | } | |
488 | ||
650f33ad | 489 | if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) { |
da95324e AK |
490 | return H_PARAMETER; |
491 | } | |
492 | ||
650f33ad AK |
493 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
494 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
495 | ioba &= page_mask; | |
496 | ||
497 | for (i = 0; i < npages; ++i, ioba += page_size) { | |
4d9ab7d4 | 498 | tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong)); |
da95324e | 499 | |
da95324e AK |
500 | ret = put_tce_emu(tcet, ioba, tce); |
501 | if (ret) { | |
502 | break; | |
503 | } | |
504 | } | |
505 | ||
506 | /* Trace last successful or the first problematic entry */ | |
507 | i = i ? (i - 1) : 0; | |
d9d96a3c AK |
508 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
509 | trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
510 | } else { | |
511 | trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
512 | } | |
da95324e AK |
513 | return ret; |
514 | } | |
515 | ||
ce2918cb | 516 | static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
da95324e AK |
517 | target_ulong opcode, target_ulong *args) |
518 | { | |
519 | int i; | |
520 | target_ulong liobn = args[0]; | |
521 | target_ulong ioba = args[1]; | |
522 | target_ulong tce_value = args[2]; | |
523 | target_ulong npages = args[3]; | |
524 | target_ulong ret = H_PARAMETER; | |
ce2918cb | 525 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
650f33ad | 526 | hwaddr page_mask, page_size; |
da95324e AK |
527 | |
528 | if (!tcet) { | |
529 | return H_PARAMETER; | |
530 | } | |
531 | ||
532 | if (npages > tcet->nb_table) { | |
533 | return H_PARAMETER; | |
534 | } | |
535 | ||
650f33ad AK |
536 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
537 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
538 | ioba &= page_mask; | |
da95324e | 539 | |
650f33ad | 540 | for (i = 0; i < npages; ++i, ioba += page_size) { |
da95324e AK |
541 | ret = put_tce_emu(tcet, ioba, tce_value); |
542 | if (ret) { | |
543 | break; | |
544 | } | |
545 | } | |
d9d96a3c AK |
546 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
547 | trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret); | |
548 | } else { | |
549 | trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret); | |
550 | } | |
da95324e AK |
551 | |
552 | return ret; | |
553 | } | |
554 | ||
ce2918cb | 555 | static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
ad0ebb91 DG |
556 | target_ulong opcode, target_ulong *args) |
557 | { | |
558 | target_ulong liobn = args[0]; | |
559 | target_ulong ioba = args[1]; | |
560 | target_ulong tce = args[2]; | |
7e472264 | 561 | target_ulong ret = H_PARAMETER; |
ce2918cb | 562 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
ad0ebb91 | 563 | |
edded454 | 564 | if (tcet) { |
650f33ad AK |
565 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
566 | ||
567 | ioba &= page_mask; | |
568 | ||
7e472264 | 569 | ret = put_tce_emu(tcet, ioba, tce); |
edded454 | 570 | } |
d9d96a3c AK |
571 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
572 | trace_spapr_iommu_pci_put(liobn, ioba, tce, ret); | |
573 | } else { | |
574 | trace_spapr_iommu_put(liobn, ioba, tce, ret); | |
575 | } | |
ad0ebb91 | 576 | |
7e472264 | 577 | return ret; |
ad0ebb91 DG |
578 | } |
579 | ||
ce2918cb | 580 | static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba, |
a0fcac9c LD |
581 | target_ulong *tce) |
582 | { | |
1b8eceee AK |
583 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
584 | ||
585 | if (index >= tcet->nb_table) { | |
a0fcac9c LD |
586 | hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x" |
587 | TARGET_FMT_lx "\n", ioba); | |
588 | return H_PARAMETER; | |
589 | } | |
590 | ||
1b8eceee | 591 | *tce = tcet->table[index]; |
a0fcac9c LD |
592 | |
593 | return H_SUCCESS; | |
594 | } | |
595 | ||
ce2918cb | 596 | static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
a0fcac9c LD |
597 | target_ulong opcode, target_ulong *args) |
598 | { | |
599 | target_ulong liobn = args[0]; | |
600 | target_ulong ioba = args[1]; | |
601 | target_ulong tce = 0; | |
602 | target_ulong ret = H_PARAMETER; | |
ce2918cb | 603 | SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn); |
a0fcac9c | 604 | |
a0fcac9c | 605 | if (tcet) { |
650f33ad AK |
606 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
607 | ||
608 | ioba &= page_mask; | |
609 | ||
a0fcac9c LD |
610 | ret = get_tce_emu(tcet, ioba, &tce); |
611 | if (!ret) { | |
612 | args[0] = tce; | |
613 | } | |
614 | } | |
d9d96a3c AK |
615 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
616 | trace_spapr_iommu_pci_get(liobn, ioba, ret, tce); | |
617 | } else { | |
618 | trace_spapr_iommu_get(liobn, ioba, ret, tce); | |
619 | } | |
a0fcac9c LD |
620 | |
621 | return ret; | |
622 | } | |
623 | ||
ad0ebb91 | 624 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
5c4cbcf2 | 625 | uint32_t liobn, uint64_t window, uint32_t size) |
ad0ebb91 | 626 | { |
5c4cbcf2 AK |
627 | uint32_t dma_prop[5]; |
628 | int ret; | |
629 | ||
630 | dma_prop[0] = cpu_to_be32(liobn); | |
631 | dma_prop[1] = cpu_to_be32(window >> 32); | |
632 | dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF); | |
633 | dma_prop[3] = 0; /* window size is 32 bits */ | |
634 | dma_prop[4] = cpu_to_be32(size); | |
635 | ||
636 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2); | |
637 | if (ret < 0) { | |
638 | return ret; | |
639 | } | |
ad0ebb91 | 640 | |
5c4cbcf2 AK |
641 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2); |
642 | if (ret < 0) { | |
643 | return ret; | |
644 | } | |
ad0ebb91 | 645 | |
5c4cbcf2 AK |
646 | ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop)); |
647 | if (ret < 0) { | |
648 | return ret; | |
ad0ebb91 DG |
649 | } |
650 | ||
651 | return 0; | |
652 | } | |
5c4cbcf2 AK |
653 | |
654 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, | |
ce2918cb | 655 | SpaprTceTable *tcet) |
5c4cbcf2 | 656 | { |
2b7dc949 | 657 | if (!tcet) { |
5c4cbcf2 AK |
658 | return 0; |
659 | } | |
660 | ||
2b7dc949 | 661 | return spapr_dma_dt(fdt, node_off, propname, |
650f33ad | 662 | tcet->liobn, 0, tcet->nb_table << tcet->page_shift); |
5c4cbcf2 | 663 | } |
a83000f5 AL |
664 | |
665 | static void spapr_tce_table_class_init(ObjectClass *klass, void *data) | |
666 | { | |
667 | DeviceClass *dc = DEVICE_CLASS(klass); | |
a931ad13 | 668 | dc->realize = spapr_tce_table_realize; |
a83000f5 | 669 | dc->reset = spapr_tce_reset; |
5f9490de | 670 | dc->unrealize = spapr_tce_table_unrealize; |
1f98e553 TH |
671 | /* Reason: This is just an internal device for handling the hypercalls */ |
672 | dc->user_creatable = false; | |
a83000f5 AL |
673 | |
674 | QLIST_INIT(&spapr_tce_tables); | |
675 | ||
676 | /* hcall-tce */ | |
677 | spapr_register_hypercall(H_PUT_TCE, h_put_tce); | |
a0fcac9c | 678 | spapr_register_hypercall(H_GET_TCE, h_get_tce); |
da95324e AK |
679 | spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect); |
680 | spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); | |
a83000f5 AL |
681 | } |
682 | ||
683 | static TypeInfo spapr_tce_table_info = { | |
684 | .name = TYPE_SPAPR_TCE_TABLE, | |
685 | .parent = TYPE_DEVICE, | |
ce2918cb | 686 | .instance_size = sizeof(SpaprTceTable), |
a83000f5 | 687 | .class_init = spapr_tce_table_class_init, |
a83000f5 AL |
688 | }; |
689 | ||
1221a474 AK |
690 | static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data) |
691 | { | |
692 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); | |
693 | ||
694 | imrc->translate = spapr_tce_translate_iommu; | |
5f366667 | 695 | imrc->replay = spapr_tce_replay; |
1221a474 AK |
696 | imrc->get_min_page_size = spapr_tce_get_min_page_size; |
697 | imrc->notify_flag_changed = spapr_tce_notify_flag_changed; | |
9ded780c | 698 | imrc->get_attr = spapr_tce_get_attr; |
1221a474 AK |
699 | } |
700 | ||
701 | static const TypeInfo spapr_iommu_memory_region_info = { | |
702 | .parent = TYPE_IOMMU_MEMORY_REGION, | |
703 | .name = TYPE_SPAPR_IOMMU_MEMORY_REGION, | |
704 | .class_init = spapr_iommu_memory_region_class_init, | |
705 | }; | |
706 | ||
a83000f5 AL |
707 | static void register_types(void) |
708 | { | |
709 | type_register_static(&spapr_tce_table_info); | |
1221a474 | 710 | type_register_static(&spapr_iommu_memory_region_info); |
a83000f5 AL |
711 | } |
712 | ||
713 | type_init(register_types); |