]> git.proxmox.com Git - mirror_qemu.git/blame - hw/ppc/spapr_iommu.c
Merge remote-tracking branch 'jasowang/tags/net-pull-request' into staging
[mirror_qemu.git] / hw / ppc / spapr_iommu.c
CommitLineData
ad0ebb91
DG
1/*
2 * QEMU sPAPR IOMMU (TCE) code
3 *
4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
0d75590d 19#include "qemu/osdep.h"
df7625d4 20#include "qemu/error-report.h"
83c9f4ca 21#include "hw/hw.h"
03dd024f 22#include "qemu/log.h"
9c17d615 23#include "sysemu/kvm.h"
83c9f4ca 24#include "hw/qdev.h"
ad0ebb91 25#include "kvm_ppc.h"
9c17d615 26#include "sysemu/dma.h"
022c62cb 27#include "exec/address-spaces.h"
7e472264 28#include "trace.h"
ad0ebb91 29
0d09e41a 30#include "hw/ppc/spapr.h"
ee9a569a 31#include "hw/ppc/spapr_vio.h"
ad0ebb91
DG
32
33#include <libfdt.h>
34
ad0ebb91
DG
35enum sPAPRTCEAccess {
36 SPAPR_TCE_FAULT = 0,
37 SPAPR_TCE_RO = 1,
38 SPAPR_TCE_WO = 2,
39 SPAPR_TCE_RW = 3,
40};
41
650f33ad
AK
42#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
43#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
44
6a0a70b0 45static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
ad0ebb91 46
f9ce8e0a 47sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
ad0ebb91
DG
48{
49 sPAPRTCETable *tcet;
50
d4261662
DG
51 if (liobn & 0xFFFFFFFF00000000ULL) {
52 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
53 liobn);
54 return NULL;
55 }
56
ad0ebb91 57 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
f9ce8e0a 58 if (tcet->liobn == (uint32_t)liobn) {
ad0ebb91
DG
59 return tcet;
60 }
61 }
62
63 return NULL;
64}
65
5709af3b
GK
66static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
67{
68 switch (tce & SPAPR_TCE_RW) {
69 case SPAPR_TCE_FAULT:
70 return IOMMU_NONE;
71 case SPAPR_TCE_RO:
72 return IOMMU_RO;
73 case SPAPR_TCE_WO:
74 return IOMMU_WO;
75 default: /* SPAPR_TCE_RW */
76 return IOMMU_RW;
77 }
78}
79
fec5d3a1
AK
80static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
81 uint32_t page_shift,
d6ee2a7c 82 uint64_t bus_offset,
fec5d3a1
AK
83 uint32_t nb_table,
84 int *fd,
85 bool need_vfio)
86{
87 uint64_t *table = NULL;
fec5d3a1 88
d6ee2a7c
AK
89 if (kvm_enabled()) {
90 table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
91 fd, need_vfio);
fec5d3a1
AK
92 }
93
94 if (!table) {
95 *fd = -1;
96 table = g_malloc0(nb_table * sizeof(uint64_t));
97 }
98
99 trace_spapr_iommu_new_table(liobn, table, *fd);
100
101 return table;
102}
103
104static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
105{
106 if (!kvm_enabled() ||
107 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
108 g_free(table);
109 }
110}
111
79e2b9ae 112/* Called from RCU critical section */
8d7b8cb9
LT
113static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr,
114 bool is_write)
ad0ebb91 115{
a84bb436 116 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
ad0ebb91 117 uint64_t tce;
7e472264
AK
118 IOMMUTLBEntry ret = {
119 .target_as = &address_space_memory,
120 .iova = 0,
121 .translated_addr = 0,
122 .addr_mask = ~(hwaddr)0,
123 .perm = IOMMU_NONE,
124 };
ad0ebb91 125
ee9a569a 126 if ((addr >> tcet->page_shift) < tcet->nb_table) {
7e472264 127 /* Check if we are in bound */
650f33ad
AK
128 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
129
130 tce = tcet->table[addr >> tcet->page_shift];
131 ret.iova = addr & page_mask;
132 ret.translated_addr = tce & page_mask;
133 ret.addr_mask = ~page_mask;
5709af3b 134 ret.perm = spapr_tce_iommu_access_flags(tce);
ad0ebb91 135 }
7e472264
AK
136 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
137 ret.addr_mask);
ad0ebb91 138
7e472264 139 return ret;
a71bfbfe
PB
140}
141
a26fdf39
AK
142static void spapr_tce_table_pre_save(void *opaque)
143{
144 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
145
146 tcet->mig_table = tcet->table;
147 tcet->mig_nb_table = tcet->nb_table;
148
149 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
150 tcet->bus_offset, tcet->page_shift);
151}
152
f682e9c2
AK
153static uint64_t spapr_tce_get_min_page_size(MemoryRegion *iommu)
154{
155 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
156
157 return 1ULL << tcet->page_shift;
158}
159
5bf3d319
PX
160static void spapr_tce_notify_flag_changed(MemoryRegion *iommu,
161 IOMMUNotifierFlag old,
162 IOMMUNotifierFlag new)
606b5498 163{
5bf3d319 164 struct sPAPRTCETable *tbl = container_of(iommu, sPAPRTCETable, iommu);
606b5498 165
5bf3d319
PX
166 if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
167 spapr_tce_set_need_vfio(tbl, true);
168 } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
169 spapr_tce_set_need_vfio(tbl, false);
170 }
606b5498
AK
171}
172
ee9a569a
AK
173static int spapr_tce_table_post_load(void *opaque, int version_id)
174{
175 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
a26fdf39
AK
176 uint32_t old_nb_table = tcet->nb_table;
177 uint64_t old_bus_offset = tcet->bus_offset;
178 uint32_t old_page_shift = tcet->page_shift;
ee9a569a
AK
179
180 if (tcet->vdev) {
181 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
182 }
183
a26fdf39
AK
184 if (tcet->mig_nb_table != tcet->nb_table) {
185 spapr_tce_table_disable(tcet);
186 }
187
188 if (tcet->mig_nb_table) {
189 if (!tcet->nb_table) {
190 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
191 tcet->mig_nb_table);
192 }
193
194 memcpy(tcet->table, tcet->mig_table,
195 tcet->nb_table * sizeof(tcet->table[0]));
196
197 free(tcet->mig_table);
198 tcet->mig_table = NULL;
199 }
200
201 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
202 tcet->bus_offset, tcet->page_shift);
203
ee9a569a
AK
204 return 0;
205}
206
a26fdf39
AK
207static bool spapr_tce_table_ex_needed(void *opaque)
208{
209 sPAPRTCETable *tcet = opaque;
210
211 return tcet->bus_offset || tcet->page_shift != 0xC;
212}
213
214static const VMStateDescription vmstate_spapr_tce_table_ex = {
215 .name = "spapr_iommu_ex",
216 .version_id = 1,
217 .minimum_version_id = 1,
218 .needed = spapr_tce_table_ex_needed,
219 .fields = (VMStateField[]) {
220 VMSTATE_UINT64(bus_offset, sPAPRTCETable),
221 VMSTATE_UINT32(page_shift, sPAPRTCETable),
222 VMSTATE_END_OF_LIST()
223 },
224};
225
a83000f5
AL
226static const VMStateDescription vmstate_spapr_tce_table = {
227 .name = "spapr_iommu",
523e7b8a
AK
228 .version_id = 2,
229 .minimum_version_id = 2,
a26fdf39 230 .pre_save = spapr_tce_table_pre_save,
ee9a569a 231 .post_load = spapr_tce_table_post_load,
523e7b8a 232 .fields = (VMStateField []) {
a83000f5
AL
233 /* Sanity check */
234 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable),
a83000f5
AL
235
236 /* IOMMU state */
a26fdf39 237 VMSTATE_UINT32(mig_nb_table, sPAPRTCETable),
a83000f5 238 VMSTATE_BOOL(bypass, sPAPRTCETable),
a26fdf39
AK
239 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0,
240 vmstate_info_uint64, uint64_t),
a83000f5
AL
241
242 VMSTATE_END_OF_LIST()
243 },
a26fdf39
AK
244 .subsections = (const VMStateDescription*[]) {
245 &vmstate_spapr_tce_table_ex,
246 NULL
247 }
a83000f5
AL
248};
249
a84bb436
PB
250static MemoryRegionIOMMUOps spapr_iommu_ops = {
251 .translate = spapr_tce_translate_iommu,
f682e9c2 252 .get_min_page_size = spapr_tce_get_min_page_size,
5bf3d319 253 .notify_flag_changed = spapr_tce_notify_flag_changed,
a84bb436 254};
ad0ebb91 255
a83000f5 256static int spapr_tce_table_realize(DeviceState *dev)
ad0ebb91 257{
a83000f5 258 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
b4b6eb77
AK
259 Object *tcetobj = OBJECT(tcet);
260 char tmp[32];
ad0ebb91 261
fec5d3a1 262 tcet->fd = -1;
df7625d4 263 tcet->need_vfio = false;
b4b6eb77
AK
264 snprintf(tmp, sizeof(tmp), "tce-root-%x", tcet->liobn);
265 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
266
267 snprintf(tmp, sizeof(tmp), "tce-iommu-%x", tcet->liobn);
268 memory_region_init_iommu(&tcet->iommu, tcetobj, &spapr_iommu_ops, tmp, 0);
a84bb436 269
ad0ebb91
DG
270 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
271
00d4f525
AK
272 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
273 tcet);
274
a83000f5
AL
275 return 0;
276}
277
c10325d6
DG
278void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
279{
280 size_t table_size = tcet->nb_table * sizeof(uint64_t);
281 void *newtable;
282
283 if (need_vfio == tcet->need_vfio) {
284 /* Nothing to do */
285 return;
286 }
287
288 if (!need_vfio) {
289 /* FIXME: We don't support transition back to KVM accelerated
290 * TCEs yet */
291 return;
292 }
293
294 tcet->need_vfio = true;
295
296 if (tcet->fd < 0) {
297 /* Table is already in userspace, nothing to be do */
298 return;
299 }
300
301 newtable = g_malloc(table_size);
302 memcpy(newtable, tcet->table, table_size);
303
304 kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table);
305
306 tcet->fd = -1;
307 tcet->table = newtable;
308}
309
df7625d4 310sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
a83000f5
AL
311{
312 sPAPRTCETable *tcet;
df7625d4 313 char tmp[32];
a83000f5
AL
314
315 if (spapr_tce_find_by_liobn(liobn)) {
ce9863b7
CLG
316 error_report("Attempted to create TCE table with duplicate"
317 " LIOBN 0x%x", liobn);
a83000f5
AL
318 return NULL;
319 }
320
a83000f5
AL
321 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
322 tcet->liobn = liobn;
a83000f5 323
dea1b3ce
AK
324 snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn);
325 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
a83000f5 326
e4c35b78 327 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
a83000f5 328
2b7dc949 329 return tcet;
ad0ebb91
DG
330}
331
df7625d4
AK
332void spapr_tce_table_enable(sPAPRTCETable *tcet,
333 uint32_t page_shift, uint64_t bus_offset,
334 uint32_t nb_table)
335{
336 if (tcet->nb_table) {
337 error_report("Warning: trying to enable already enabled TCE table");
338 return;
339 }
340
341 tcet->bus_offset = bus_offset;
342 tcet->page_shift = page_shift;
343 tcet->nb_table = nb_table;
344 tcet->table = spapr_tce_alloc_table(tcet->liobn,
345 tcet->page_shift,
d6ee2a7c 346 tcet->bus_offset,
df7625d4
AK
347 tcet->nb_table,
348 &tcet->fd,
349 tcet->need_vfio);
350
351 memory_region_set_size(&tcet->iommu,
352 (uint64_t)tcet->nb_table << tcet->page_shift);
b4b6eb77 353 memory_region_add_subregion(&tcet->root, tcet->bus_offset, &tcet->iommu);
df7625d4
AK
354}
355
a26fdf39 356void spapr_tce_table_disable(sPAPRTCETable *tcet)
df7625d4
AK
357{
358 if (!tcet->nb_table) {
359 return;
360 }
361
b4b6eb77 362 memory_region_del_subregion(&tcet->root, &tcet->iommu);
df7625d4
AK
363 memory_region_set_size(&tcet->iommu, 0);
364
365 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
366 tcet->fd = -1;
367 tcet->table = NULL;
368 tcet->bus_offset = 0;
369 tcet->page_shift = 0;
370 tcet->nb_table = 0;
371}
372
5f9490de 373static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
ad0ebb91 374{
5f9490de 375 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
a83000f5 376
2b7dc949 377 QLIST_REMOVE(tcet, list);
ad0ebb91 378
df7625d4 379 spapr_tce_table_disable(tcet);
ad0ebb91
DG
380}
381
a84bb436
PB
382MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
383{
b4b6eb77 384 return &tcet->root;
a84bb436
PB
385}
386
a83000f5 387static void spapr_tce_reset(DeviceState *dev)
eddeed26 388{
a83000f5 389 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
523e7b8a 390 size_t table_size = tcet->nb_table * sizeof(uint64_t);
eddeed26 391
57c0eb1e
DG
392 if (tcet->nb_table) {
393 memset(tcet->table, 0, table_size);
394 }
eddeed26
DG
395}
396
edded454
DG
397static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
398 target_ulong tce)
399{
a84bb436 400 IOMMUTLBEntry entry;
650f33ad 401 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
1b8eceee 402 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
edded454 403
1b8eceee 404 if (index >= tcet->nb_table) {
b55519a0 405 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
edded454
DG
406 TARGET_FMT_lx "\n", ioba);
407 return H_PARAMETER;
408 }
409
1b8eceee 410 tcet->table[index] = tce;
edded454 411
a84bb436 412 entry.target_as = &address_space_memory,
d78c19b5 413 entry.iova = (ioba - tcet->bus_offset) & page_mask;
650f33ad
AK
414 entry.translated_addr = tce & page_mask;
415 entry.addr_mask = ~page_mask;
5709af3b 416 entry.perm = spapr_tce_iommu_access_flags(tce);
a84bb436
PB
417 memory_region_notify_iommu(&tcet->iommu, entry);
418
edded454
DG
419 return H_SUCCESS;
420}
ad0ebb91 421
da95324e 422static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
28e02042 423 sPAPRMachineState *spapr,
da95324e
AK
424 target_ulong opcode, target_ulong *args)
425{
426 int i;
427 target_ulong liobn = args[0];
428 target_ulong ioba = args[1];
429 target_ulong ioba1 = ioba;
430 target_ulong tce_list = args[2];
431 target_ulong npages = args[3];
f1215ea7 432 target_ulong ret = H_PARAMETER, tce = 0;
da95324e
AK
433 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
434 CPUState *cs = CPU(cpu);
650f33ad 435 hwaddr page_mask, page_size;
da95324e
AK
436
437 if (!tcet) {
438 return H_PARAMETER;
439 }
440
650f33ad 441 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
da95324e
AK
442 return H_PARAMETER;
443 }
444
650f33ad
AK
445 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
446 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
447 ioba &= page_mask;
448
449 for (i = 0; i < npages; ++i, ioba += page_size) {
4d9ab7d4 450 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
da95324e 451
da95324e
AK
452 ret = put_tce_emu(tcet, ioba, tce);
453 if (ret) {
454 break;
455 }
456 }
457
458 /* Trace last successful or the first problematic entry */
459 i = i ? (i - 1) : 0;
d9d96a3c
AK
460 if (SPAPR_IS_PCI_LIOBN(liobn)) {
461 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
462 } else {
463 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
464 }
da95324e
AK
465 return ret;
466}
467
28e02042 468static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
da95324e
AK
469 target_ulong opcode, target_ulong *args)
470{
471 int i;
472 target_ulong liobn = args[0];
473 target_ulong ioba = args[1];
474 target_ulong tce_value = args[2];
475 target_ulong npages = args[3];
476 target_ulong ret = H_PARAMETER;
477 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
650f33ad 478 hwaddr page_mask, page_size;
da95324e
AK
479
480 if (!tcet) {
481 return H_PARAMETER;
482 }
483
484 if (npages > tcet->nb_table) {
485 return H_PARAMETER;
486 }
487
650f33ad
AK
488 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
489 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
490 ioba &= page_mask;
da95324e 491
650f33ad 492 for (i = 0; i < npages; ++i, ioba += page_size) {
da95324e
AK
493 ret = put_tce_emu(tcet, ioba, tce_value);
494 if (ret) {
495 break;
496 }
497 }
d9d96a3c
AK
498 if (SPAPR_IS_PCI_LIOBN(liobn)) {
499 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
500 } else {
501 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
502 }
da95324e
AK
503
504 return ret;
505}
506
28e02042 507static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
ad0ebb91
DG
508 target_ulong opcode, target_ulong *args)
509{
510 target_ulong liobn = args[0];
511 target_ulong ioba = args[1];
512 target_ulong tce = args[2];
7e472264 513 target_ulong ret = H_PARAMETER;
ad0ebb91 514 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
ad0ebb91 515
edded454 516 if (tcet) {
650f33ad
AK
517 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
518
519 ioba &= page_mask;
520
7e472264 521 ret = put_tce_emu(tcet, ioba, tce);
edded454 522 }
d9d96a3c
AK
523 if (SPAPR_IS_PCI_LIOBN(liobn)) {
524 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
525 } else {
526 trace_spapr_iommu_put(liobn, ioba, tce, ret);
527 }
ad0ebb91 528
7e472264 529 return ret;
ad0ebb91
DG
530}
531
a0fcac9c
LD
532static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
533 target_ulong *tce)
534{
1b8eceee
AK
535 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
536
537 if (index >= tcet->nb_table) {
a0fcac9c
LD
538 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
539 TARGET_FMT_lx "\n", ioba);
540 return H_PARAMETER;
541 }
542
1b8eceee 543 *tce = tcet->table[index];
a0fcac9c
LD
544
545 return H_SUCCESS;
546}
547
28e02042 548static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
a0fcac9c
LD
549 target_ulong opcode, target_ulong *args)
550{
551 target_ulong liobn = args[0];
552 target_ulong ioba = args[1];
553 target_ulong tce = 0;
554 target_ulong ret = H_PARAMETER;
555 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
556
a0fcac9c 557 if (tcet) {
650f33ad
AK
558 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
559
560 ioba &= page_mask;
561
a0fcac9c
LD
562 ret = get_tce_emu(tcet, ioba, &tce);
563 if (!ret) {
564 args[0] = tce;
565 }
566 }
d9d96a3c
AK
567 if (SPAPR_IS_PCI_LIOBN(liobn)) {
568 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
569 } else {
570 trace_spapr_iommu_get(liobn, ioba, ret, tce);
571 }
a0fcac9c
LD
572
573 return ret;
574}
575
ad0ebb91 576int spapr_dma_dt(void *fdt, int node_off, const char *propname,
5c4cbcf2 577 uint32_t liobn, uint64_t window, uint32_t size)
ad0ebb91 578{
5c4cbcf2
AK
579 uint32_t dma_prop[5];
580 int ret;
581
582 dma_prop[0] = cpu_to_be32(liobn);
583 dma_prop[1] = cpu_to_be32(window >> 32);
584 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
585 dma_prop[3] = 0; /* window size is 32 bits */
586 dma_prop[4] = cpu_to_be32(size);
587
588 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
589 if (ret < 0) {
590 return ret;
591 }
ad0ebb91 592
5c4cbcf2
AK
593 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
594 if (ret < 0) {
595 return ret;
596 }
ad0ebb91 597
5c4cbcf2
AK
598 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
599 if (ret < 0) {
600 return ret;
ad0ebb91
DG
601 }
602
603 return 0;
604}
5c4cbcf2
AK
605
606int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
2b7dc949 607 sPAPRTCETable *tcet)
5c4cbcf2 608{
2b7dc949 609 if (!tcet) {
5c4cbcf2
AK
610 return 0;
611 }
612
2b7dc949 613 return spapr_dma_dt(fdt, node_off, propname,
650f33ad 614 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
5c4cbcf2 615}
a83000f5
AL
616
617static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
618{
619 DeviceClass *dc = DEVICE_CLASS(klass);
a83000f5
AL
620 dc->init = spapr_tce_table_realize;
621 dc->reset = spapr_tce_reset;
5f9490de 622 dc->unrealize = spapr_tce_table_unrealize;
a83000f5
AL
623
624 QLIST_INIT(&spapr_tce_tables);
625
626 /* hcall-tce */
627 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
a0fcac9c 628 spapr_register_hypercall(H_GET_TCE, h_get_tce);
da95324e
AK
629 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
630 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
a83000f5
AL
631}
632
633static TypeInfo spapr_tce_table_info = {
634 .name = TYPE_SPAPR_TCE_TABLE,
635 .parent = TYPE_DEVICE,
636 .instance_size = sizeof(sPAPRTCETable),
637 .class_init = spapr_tce_table_class_init,
a83000f5
AL
638};
639
640static void register_types(void)
641{
642 type_register_static(&spapr_tce_table_info);
643}
644
645type_init(register_types);