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ad0ebb91
DG
1/*
2 * QEMU sPAPR IOMMU (TCE) code
3 *
4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
0b8fa32f 19
0d75590d 20#include "qemu/osdep.h"
df7625d4 21#include "qemu/error-report.h"
03dd024f 22#include "qemu/log.h"
0b8fa32f 23#include "qemu/module.h"
9c17d615 24#include "sysemu/kvm.h"
ad0ebb91 25#include "kvm_ppc.h"
d6454270 26#include "migration/vmstate.h"
9c17d615 27#include "sysemu/dma.h"
022c62cb 28#include "exec/address-spaces.h"
7e472264 29#include "trace.h"
ad0ebb91 30
0d09e41a 31#include "hw/ppc/spapr.h"
ee9a569a 32#include "hw/ppc/spapr_vio.h"
ad0ebb91
DG
33
34#include <libfdt.h>
35
ce2918cb 36enum SpaprTceAccess {
ad0ebb91
DG
37 SPAPR_TCE_FAULT = 0,
38 SPAPR_TCE_RO = 1,
39 SPAPR_TCE_WO = 2,
40 SPAPR_TCE_RW = 3,
41};
42
650f33ad
AK
43#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
44#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
45
ce2918cb 46static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables;
ad0ebb91 47
ce2918cb 48SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn)
ad0ebb91 49{
ce2918cb 50 SpaprTceTable *tcet;
ad0ebb91 51
d4261662
DG
52 if (liobn & 0xFFFFFFFF00000000ULL) {
53 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
54 liobn);
55 return NULL;
56 }
57
ad0ebb91 58 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
f9ce8e0a 59 if (tcet->liobn == (uint32_t)liobn) {
ad0ebb91
DG
60 return tcet;
61 }
62 }
63
64 return NULL;
65}
66
5709af3b
GK
67static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
68{
69 switch (tce & SPAPR_TCE_RW) {
70 case SPAPR_TCE_FAULT:
71 return IOMMU_NONE;
72 case SPAPR_TCE_RO:
73 return IOMMU_RO;
74 case SPAPR_TCE_WO:
75 return IOMMU_WO;
76 default: /* SPAPR_TCE_RW */
77 return IOMMU_RW;
78 }
79}
80
fec5d3a1
AK
81static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
82 uint32_t page_shift,
d6ee2a7c 83 uint64_t bus_offset,
fec5d3a1
AK
84 uint32_t nb_table,
85 int *fd,
86 bool need_vfio)
87{
88 uint64_t *table = NULL;
fec5d3a1 89
d6ee2a7c
AK
90 if (kvm_enabled()) {
91 table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
92 fd, need_vfio);
fec5d3a1
AK
93 }
94
95 if (!table) {
96 *fd = -1;
dec4ec40 97 table = g_new0(uint64_t, nb_table);
fec5d3a1
AK
98 }
99
100 trace_spapr_iommu_new_table(liobn, table, *fd);
101
102 return table;
103}
104
105static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
106{
107 if (!kvm_enabled() ||
108 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
109 g_free(table);
110 }
111}
112
79e2b9ae 113/* Called from RCU critical section */
3df9d748
AK
114static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
115 hwaddr addr,
2c91bcf2
PM
116 IOMMUAccessFlags flag,
117 int iommu_idx)
ad0ebb91 118{
ce2918cb 119 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
ad0ebb91 120 uint64_t tce;
7e472264
AK
121 IOMMUTLBEntry ret = {
122 .target_as = &address_space_memory,
123 .iova = 0,
124 .translated_addr = 0,
125 .addr_mask = ~(hwaddr)0,
126 .perm = IOMMU_NONE,
127 };
ad0ebb91 128
ee9a569a 129 if ((addr >> tcet->page_shift) < tcet->nb_table) {
7e472264 130 /* Check if we are in bound */
650f33ad
AK
131 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
132
133 tce = tcet->table[addr >> tcet->page_shift];
134 ret.iova = addr & page_mask;
135 ret.translated_addr = tce & page_mask;
136 ret.addr_mask = ~page_mask;
5709af3b 137 ret.perm = spapr_tce_iommu_access_flags(tce);
ad0ebb91 138 }
7e472264
AK
139 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
140 ret.addr_mask);
ad0ebb91 141
7e472264 142 return ret;
a71bfbfe
PB
143}
144
5f366667
AK
145static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
146{
147 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
148 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
149 hwaddr addr, granularity;
150 IOMMUTLBEntry iotlb;
ce2918cb 151 SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu);
5f366667
AK
152
153 if (tcet->skipping_replay) {
154 return;
155 }
156
157 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
158
159 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
160 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
161 if (iotlb.perm != IOMMU_NONE) {
162 n->notify(n, &iotlb);
163 }
164
165 /*
166 * if (2^64 - MR size) < granularity, it's possible to get an
167 * infinite loop here. This should catch such a wraparound.
168 */
169 if ((addr + granularity) < addr) {
170 break;
171 }
172 }
173}
174
44b1ff31 175static int spapr_tce_table_pre_save(void *opaque)
a26fdf39 176{
ce2918cb 177 SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
a26fdf39
AK
178
179 tcet->mig_table = tcet->table;
180 tcet->mig_nb_table = tcet->nb_table;
181
182 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
183 tcet->bus_offset, tcet->page_shift);
44b1ff31
DDAG
184
185 return 0;
a26fdf39
AK
186}
187
3df9d748 188static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
f682e9c2 189{
ce2918cb 190 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
f682e9c2
AK
191
192 return 1ULL << tcet->page_shift;
193}
194
9ded780c
AK
195static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu,
196 enum IOMMUMemoryRegionAttr attr, void *data)
197{
ce2918cb 198 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
9ded780c
AK
199
200 if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) {
201 *(int *) data = tcet->fd;
202 return 0;
203 }
204
205 return -EINVAL;
206}
207
3df9d748 208static void spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
5bf3d319
PX
209 IOMMUNotifierFlag old,
210 IOMMUNotifierFlag new)
606b5498 211{
ce2918cb 212 struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu);
606b5498 213
5bf3d319
PX
214 if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
215 spapr_tce_set_need_vfio(tbl, true);
216 } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
217 spapr_tce_set_need_vfio(tbl, false);
218 }
606b5498
AK
219}
220
ee9a569a
AK
221static int spapr_tce_table_post_load(void *opaque, int version_id)
222{
ce2918cb 223 SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
a26fdf39
AK
224 uint32_t old_nb_table = tcet->nb_table;
225 uint64_t old_bus_offset = tcet->bus_offset;
226 uint32_t old_page_shift = tcet->page_shift;
ee9a569a
AK
227
228 if (tcet->vdev) {
229 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
230 }
231
a26fdf39
AK
232 if (tcet->mig_nb_table != tcet->nb_table) {
233 spapr_tce_table_disable(tcet);
234 }
235
236 if (tcet->mig_nb_table) {
237 if (!tcet->nb_table) {
238 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
239 tcet->mig_nb_table);
240 }
241
242 memcpy(tcet->table, tcet->mig_table,
243 tcet->nb_table * sizeof(tcet->table[0]));
244
245 free(tcet->mig_table);
246 tcet->mig_table = NULL;
247 }
248
249 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
250 tcet->bus_offset, tcet->page_shift);
251
ee9a569a
AK
252 return 0;
253}
254
a26fdf39
AK
255static bool spapr_tce_table_ex_needed(void *opaque)
256{
ce2918cb 257 SpaprTceTable *tcet = opaque;
a26fdf39
AK
258
259 return tcet->bus_offset || tcet->page_shift != 0xC;
260}
261
262static const VMStateDescription vmstate_spapr_tce_table_ex = {
263 .name = "spapr_iommu_ex",
264 .version_id = 1,
265 .minimum_version_id = 1,
266 .needed = spapr_tce_table_ex_needed,
267 .fields = (VMStateField[]) {
ce2918cb
DG
268 VMSTATE_UINT64(bus_offset, SpaprTceTable),
269 VMSTATE_UINT32(page_shift, SpaprTceTable),
a26fdf39
AK
270 VMSTATE_END_OF_LIST()
271 },
272};
273
a83000f5
AL
274static const VMStateDescription vmstate_spapr_tce_table = {
275 .name = "spapr_iommu",
523e7b8a
AK
276 .version_id = 2,
277 .minimum_version_id = 2,
a26fdf39 278 .pre_save = spapr_tce_table_pre_save,
ee9a569a 279 .post_load = spapr_tce_table_post_load,
523e7b8a 280 .fields = (VMStateField []) {
a83000f5 281 /* Sanity check */
ce2918cb 282 VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL),
a83000f5
AL
283
284 /* IOMMU state */
ce2918cb
DG
285 VMSTATE_UINT32(mig_nb_table, SpaprTceTable),
286 VMSTATE_BOOL(bypass, SpaprTceTable),
287 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0,
a26fdf39 288 vmstate_info_uint64, uint64_t),
a83000f5
AL
289
290 VMSTATE_END_OF_LIST()
291 },
a26fdf39
AK
292 .subsections = (const VMStateDescription*[]) {
293 &vmstate_spapr_tce_table_ex,
294 NULL
295 }
a83000f5
AL
296};
297
a931ad13 298static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
ad0ebb91 299{
ce2918cb 300 SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
b4b6eb77 301 Object *tcetobj = OBJECT(tcet);
a205a053 302 gchar *tmp;
ad0ebb91 303
fec5d3a1 304 tcet->fd = -1;
df7625d4 305 tcet->need_vfio = false;
a205a053 306 tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
b4b6eb77 307 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
a205a053 308 g_free(tmp);
b4b6eb77 309
a205a053 310 tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
1221a474
AK
311 memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
312 TYPE_SPAPR_IOMMU_MEMORY_REGION,
313 tcetobj, tmp, 0);
a205a053 314 g_free(tmp);
a84bb436 315
ad0ebb91
DG
316 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
317
00d4f525
AK
318 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
319 tcet);
a83000f5
AL
320}
321
ce2918cb 322void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio)
c10325d6
DG
323{
324 size_t table_size = tcet->nb_table * sizeof(uint64_t);
f5509b6b
AK
325 uint64_t *oldtable;
326 int newfd = -1;
c10325d6 327
f5509b6b 328 g_assert(need_vfio != tcet->need_vfio);
c10325d6 329
f5509b6b 330 tcet->need_vfio = need_vfio;
c10325d6 331
9ded780c
AK
332 if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) {
333 return;
334 }
335
f5509b6b 336 oldtable = tcet->table;
c10325d6 337
f5509b6b
AK
338 tcet->table = spapr_tce_alloc_table(tcet->liobn,
339 tcet->page_shift,
340 tcet->bus_offset,
341 tcet->nb_table,
342 &newfd,
343 need_vfio);
344 memcpy(tcet->table, oldtable, table_size);
c10325d6 345
f5509b6b 346 spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
c10325d6 347
f5509b6b 348 tcet->fd = newfd;
c10325d6
DG
349}
350
ce2918cb 351SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
a83000f5 352{
ce2918cb 353 SpaprTceTable *tcet;
a205a053 354 gchar *tmp;
a83000f5
AL
355
356 if (spapr_tce_find_by_liobn(liobn)) {
ce9863b7
CLG
357 error_report("Attempted to create TCE table with duplicate"
358 " LIOBN 0x%x", liobn);
a83000f5
AL
359 return NULL;
360 }
361
a83000f5
AL
362 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
363 tcet->liobn = liobn;
a83000f5 364
a205a053 365 tmp = g_strdup_printf("tce-table-%x", liobn);
dea1b3ce 366 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
a205a053 367 g_free(tmp);
8dc9785c 368 object_unref(OBJECT(tcet));
a83000f5 369
e4c35b78 370 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
a83000f5 371
2b7dc949 372 return tcet;
ad0ebb91
DG
373}
374
ce2918cb 375void spapr_tce_table_enable(SpaprTceTable *tcet,
df7625d4
AK
376 uint32_t page_shift, uint64_t bus_offset,
377 uint32_t nb_table)
378{
379 if (tcet->nb_table) {
3dc6f869 380 warn_report("trying to enable already enabled TCE table");
df7625d4
AK
381 return;
382 }
383
384 tcet->bus_offset = bus_offset;
385 tcet->page_shift = page_shift;
386 tcet->nb_table = nb_table;
387 tcet->table = spapr_tce_alloc_table(tcet->liobn,
388 tcet->page_shift,
d6ee2a7c 389 tcet->bus_offset,
df7625d4
AK
390 tcet->nb_table,
391 &tcet->fd,
392 tcet->need_vfio);
393
3df9d748 394 memory_region_set_size(MEMORY_REGION(&tcet->iommu),
df7625d4 395 (uint64_t)tcet->nb_table << tcet->page_shift);
3df9d748
AK
396 memory_region_add_subregion(&tcet->root, tcet->bus_offset,
397 MEMORY_REGION(&tcet->iommu));
df7625d4
AK
398}
399
ce2918cb 400void spapr_tce_table_disable(SpaprTceTable *tcet)
df7625d4
AK
401{
402 if (!tcet->nb_table) {
403 return;
404 }
405
3df9d748
AK
406 memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
407 memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
df7625d4
AK
408
409 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
410 tcet->fd = -1;
411 tcet->table = NULL;
412 tcet->bus_offset = 0;
413 tcet->page_shift = 0;
414 tcet->nb_table = 0;
415}
416
5f9490de 417static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
ad0ebb91 418{
ce2918cb 419 SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
a83000f5 420
ea359d20
GK
421 vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet);
422
2b7dc949 423 QLIST_REMOVE(tcet, list);
ad0ebb91 424
df7625d4 425 spapr_tce_table_disable(tcet);
ad0ebb91
DG
426}
427
ce2918cb 428MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet)
a84bb436 429{
b4b6eb77 430 return &tcet->root;
a84bb436
PB
431}
432
a83000f5 433static void spapr_tce_reset(DeviceState *dev)
eddeed26 434{
ce2918cb 435 SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
523e7b8a 436 size_t table_size = tcet->nb_table * sizeof(uint64_t);
eddeed26 437
57c0eb1e
DG
438 if (tcet->nb_table) {
439 memset(tcet->table, 0, table_size);
440 }
eddeed26
DG
441}
442
ce2918cb 443static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
edded454
DG
444 target_ulong tce)
445{
a84bb436 446 IOMMUTLBEntry entry;
650f33ad 447 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
1b8eceee 448 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
edded454 449
1b8eceee 450 if (index >= tcet->nb_table) {
b55519a0 451 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
edded454
DG
452 TARGET_FMT_lx "\n", ioba);
453 return H_PARAMETER;
454 }
455
1b8eceee 456 tcet->table[index] = tce;
edded454 457
a84bb436 458 entry.target_as = &address_space_memory,
d78c19b5 459 entry.iova = (ioba - tcet->bus_offset) & page_mask;
650f33ad
AK
460 entry.translated_addr = tce & page_mask;
461 entry.addr_mask = ~page_mask;
5709af3b 462 entry.perm = spapr_tce_iommu_access_flags(tce);
cb1efcf4 463 memory_region_notify_iommu(&tcet->iommu, 0, entry);
a84bb436 464
edded454
DG
465 return H_SUCCESS;
466}
ad0ebb91 467
da95324e 468static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
ce2918cb 469 SpaprMachineState *spapr,
da95324e
AK
470 target_ulong opcode, target_ulong *args)
471{
472 int i;
473 target_ulong liobn = args[0];
474 target_ulong ioba = args[1];
475 target_ulong ioba1 = ioba;
476 target_ulong tce_list = args[2];
477 target_ulong npages = args[3];
f1215ea7 478 target_ulong ret = H_PARAMETER, tce = 0;
ce2918cb 479 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
da95324e 480 CPUState *cs = CPU(cpu);
650f33ad 481 hwaddr page_mask, page_size;
da95324e
AK
482
483 if (!tcet) {
484 return H_PARAMETER;
485 }
486
650f33ad 487 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
da95324e
AK
488 return H_PARAMETER;
489 }
490
650f33ad
AK
491 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
492 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
493 ioba &= page_mask;
494
495 for (i = 0; i < npages; ++i, ioba += page_size) {
4d9ab7d4 496 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
da95324e 497
da95324e
AK
498 ret = put_tce_emu(tcet, ioba, tce);
499 if (ret) {
500 break;
501 }
502 }
503
504 /* Trace last successful or the first problematic entry */
505 i = i ? (i - 1) : 0;
d9d96a3c
AK
506 if (SPAPR_IS_PCI_LIOBN(liobn)) {
507 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
508 } else {
509 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
510 }
da95324e
AK
511 return ret;
512}
513
ce2918cb 514static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
da95324e
AK
515 target_ulong opcode, target_ulong *args)
516{
517 int i;
518 target_ulong liobn = args[0];
519 target_ulong ioba = args[1];
520 target_ulong tce_value = args[2];
521 target_ulong npages = args[3];
522 target_ulong ret = H_PARAMETER;
ce2918cb 523 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
650f33ad 524 hwaddr page_mask, page_size;
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525
526 if (!tcet) {
527 return H_PARAMETER;
528 }
529
530 if (npages > tcet->nb_table) {
531 return H_PARAMETER;
532 }
533
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534 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
535 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
536 ioba &= page_mask;
da95324e 537
650f33ad 538 for (i = 0; i < npages; ++i, ioba += page_size) {
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539 ret = put_tce_emu(tcet, ioba, tce_value);
540 if (ret) {
541 break;
542 }
543 }
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544 if (SPAPR_IS_PCI_LIOBN(liobn)) {
545 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
546 } else {
547 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
548 }
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549
550 return ret;
551}
552
ce2918cb 553static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
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554 target_ulong opcode, target_ulong *args)
555{
556 target_ulong liobn = args[0];
557 target_ulong ioba = args[1];
558 target_ulong tce = args[2];
7e472264 559 target_ulong ret = H_PARAMETER;
ce2918cb 560 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
ad0ebb91 561
edded454 562 if (tcet) {
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563 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
564
565 ioba &= page_mask;
566
7e472264 567 ret = put_tce_emu(tcet, ioba, tce);
edded454 568 }
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569 if (SPAPR_IS_PCI_LIOBN(liobn)) {
570 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
571 } else {
572 trace_spapr_iommu_put(liobn, ioba, tce, ret);
573 }
ad0ebb91 574
7e472264 575 return ret;
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576}
577
ce2918cb 578static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
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579 target_ulong *tce)
580{
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581 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
582
583 if (index >= tcet->nb_table) {
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584 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
585 TARGET_FMT_lx "\n", ioba);
586 return H_PARAMETER;
587 }
588
1b8eceee 589 *tce = tcet->table[index];
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590
591 return H_SUCCESS;
592}
593
ce2918cb 594static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
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595 target_ulong opcode, target_ulong *args)
596{
597 target_ulong liobn = args[0];
598 target_ulong ioba = args[1];
599 target_ulong tce = 0;
600 target_ulong ret = H_PARAMETER;
ce2918cb 601 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
a0fcac9c 602
a0fcac9c 603 if (tcet) {
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604 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
605
606 ioba &= page_mask;
607
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608 ret = get_tce_emu(tcet, ioba, &tce);
609 if (!ret) {
610 args[0] = tce;
611 }
612 }
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613 if (SPAPR_IS_PCI_LIOBN(liobn)) {
614 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
615 } else {
616 trace_spapr_iommu_get(liobn, ioba, ret, tce);
617 }
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618
619 return ret;
620}
621
ad0ebb91 622int spapr_dma_dt(void *fdt, int node_off, const char *propname,
5c4cbcf2 623 uint32_t liobn, uint64_t window, uint32_t size)
ad0ebb91 624{
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625 uint32_t dma_prop[5];
626 int ret;
627
628 dma_prop[0] = cpu_to_be32(liobn);
629 dma_prop[1] = cpu_to_be32(window >> 32);
630 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
631 dma_prop[3] = 0; /* window size is 32 bits */
632 dma_prop[4] = cpu_to_be32(size);
633
634 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
635 if (ret < 0) {
636 return ret;
637 }
ad0ebb91 638
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639 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
640 if (ret < 0) {
641 return ret;
642 }
ad0ebb91 643
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644 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
645 if (ret < 0) {
646 return ret;
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647 }
648
649 return 0;
650}
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651
652int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
ce2918cb 653 SpaprTceTable *tcet)
5c4cbcf2 654{
2b7dc949 655 if (!tcet) {
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656 return 0;
657 }
658
2b7dc949 659 return spapr_dma_dt(fdt, node_off, propname,
650f33ad 660 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
5c4cbcf2 661}
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662
663static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
664{
665 DeviceClass *dc = DEVICE_CLASS(klass);
a931ad13 666 dc->realize = spapr_tce_table_realize;
a83000f5 667 dc->reset = spapr_tce_reset;
5f9490de 668 dc->unrealize = spapr_tce_table_unrealize;
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669 /* Reason: This is just an internal device for handling the hypercalls */
670 dc->user_creatable = false;
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671
672 QLIST_INIT(&spapr_tce_tables);
673
674 /* hcall-tce */
675 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
a0fcac9c 676 spapr_register_hypercall(H_GET_TCE, h_get_tce);
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677 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
678 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
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679}
680
681static TypeInfo spapr_tce_table_info = {
682 .name = TYPE_SPAPR_TCE_TABLE,
683 .parent = TYPE_DEVICE,
ce2918cb 684 .instance_size = sizeof(SpaprTceTable),
a83000f5 685 .class_init = spapr_tce_table_class_init,
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686};
687
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688static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
689{
690 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
691
692 imrc->translate = spapr_tce_translate_iommu;
5f366667 693 imrc->replay = spapr_tce_replay;
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694 imrc->get_min_page_size = spapr_tce_get_min_page_size;
695 imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
9ded780c 696 imrc->get_attr = spapr_tce_get_attr;
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697}
698
699static const TypeInfo spapr_iommu_memory_region_info = {
700 .parent = TYPE_IOMMU_MEMORY_REGION,
701 .name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
702 .class_init = spapr_iommu_memory_region_class_init,
703};
704
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705static void register_types(void)
706{
707 type_register_static(&spapr_tce_table_info);
1221a474 708 type_register_static(&spapr_iommu_memory_region_info);
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709}
710
711type_init(register_types);