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Commit | Line | Data |
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ad0ebb91 DG |
1 | /* |
2 | * QEMU sPAPR IOMMU (TCE) code | |
3 | * | |
4 | * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
83c9f4ca | 20 | #include "hw/hw.h" |
9c17d615 | 21 | #include "sysemu/kvm.h" |
83c9f4ca | 22 | #include "hw/qdev.h" |
ad0ebb91 | 23 | #include "kvm_ppc.h" |
9c17d615 | 24 | #include "sysemu/dma.h" |
022c62cb | 25 | #include "exec/address-spaces.h" |
7e472264 | 26 | #include "trace.h" |
ad0ebb91 | 27 | |
0d09e41a | 28 | #include "hw/ppc/spapr.h" |
ee9a569a | 29 | #include "hw/ppc/spapr_vio.h" |
ad0ebb91 DG |
30 | |
31 | #include <libfdt.h> | |
32 | ||
ad0ebb91 DG |
33 | enum sPAPRTCEAccess { |
34 | SPAPR_TCE_FAULT = 0, | |
35 | SPAPR_TCE_RO = 1, | |
36 | SPAPR_TCE_WO = 2, | |
37 | SPAPR_TCE_RW = 3, | |
38 | }; | |
39 | ||
650f33ad AK |
40 | #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift)) |
41 | #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1)) | |
42 | ||
6a0a70b0 | 43 | static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables; |
ad0ebb91 | 44 | |
f9ce8e0a | 45 | sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn) |
ad0ebb91 DG |
46 | { |
47 | sPAPRTCETable *tcet; | |
48 | ||
d4261662 DG |
49 | if (liobn & 0xFFFFFFFF00000000ULL) { |
50 | hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n", | |
51 | liobn); | |
52 | return NULL; | |
53 | } | |
54 | ||
ad0ebb91 | 55 | QLIST_FOREACH(tcet, &spapr_tce_tables, list) { |
f9ce8e0a | 56 | if (tcet->liobn == (uint32_t)liobn) { |
ad0ebb91 DG |
57 | return tcet; |
58 | } | |
59 | } | |
60 | ||
61 | return NULL; | |
62 | } | |
63 | ||
5709af3b GK |
64 | static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce) |
65 | { | |
66 | switch (tce & SPAPR_TCE_RW) { | |
67 | case SPAPR_TCE_FAULT: | |
68 | return IOMMU_NONE; | |
69 | case SPAPR_TCE_RO: | |
70 | return IOMMU_RO; | |
71 | case SPAPR_TCE_WO: | |
72 | return IOMMU_WO; | |
73 | default: /* SPAPR_TCE_RW */ | |
74 | return IOMMU_RW; | |
75 | } | |
76 | } | |
77 | ||
79e2b9ae | 78 | /* Called from RCU critical section */ |
8d7b8cb9 LT |
79 | static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr, |
80 | bool is_write) | |
ad0ebb91 | 81 | { |
a84bb436 | 82 | sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); |
ad0ebb91 | 83 | uint64_t tce; |
7e472264 AK |
84 | IOMMUTLBEntry ret = { |
85 | .target_as = &address_space_memory, | |
86 | .iova = 0, | |
87 | .translated_addr = 0, | |
88 | .addr_mask = ~(hwaddr)0, | |
89 | .perm = IOMMU_NONE, | |
90 | }; | |
ad0ebb91 | 91 | |
ee9a569a | 92 | if ((addr >> tcet->page_shift) < tcet->nb_table) { |
7e472264 | 93 | /* Check if we are in bound */ |
650f33ad AK |
94 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
95 | ||
96 | tce = tcet->table[addr >> tcet->page_shift]; | |
97 | ret.iova = addr & page_mask; | |
98 | ret.translated_addr = tce & page_mask; | |
99 | ret.addr_mask = ~page_mask; | |
5709af3b | 100 | ret.perm = spapr_tce_iommu_access_flags(tce); |
ad0ebb91 | 101 | } |
7e472264 AK |
102 | trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm, |
103 | ret.addr_mask); | |
ad0ebb91 | 104 | |
7e472264 | 105 | return ret; |
a71bfbfe PB |
106 | } |
107 | ||
ee9a569a AK |
108 | static int spapr_tce_table_post_load(void *opaque, int version_id) |
109 | { | |
110 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); | |
111 | ||
112 | if (tcet->vdev) { | |
113 | spapr_vio_set_bypass(tcet->vdev, tcet->bypass); | |
114 | } | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
a83000f5 AL |
119 | static const VMStateDescription vmstate_spapr_tce_table = { |
120 | .name = "spapr_iommu", | |
523e7b8a AK |
121 | .version_id = 2, |
122 | .minimum_version_id = 2, | |
ee9a569a | 123 | .post_load = spapr_tce_table_post_load, |
523e7b8a | 124 | .fields = (VMStateField []) { |
a83000f5 AL |
125 | /* Sanity check */ |
126 | VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable), | |
523e7b8a | 127 | VMSTATE_UINT32_EQUAL(nb_table, sPAPRTCETable), |
a83000f5 AL |
128 | |
129 | /* IOMMU state */ | |
130 | VMSTATE_BOOL(bypass, sPAPRTCETable), | |
131 | VMSTATE_VARRAY_UINT32(table, sPAPRTCETable, nb_table, 0, vmstate_info_uint64, uint64_t), | |
132 | ||
133 | VMSTATE_END_OF_LIST() | |
134 | }, | |
135 | }; | |
136 | ||
a84bb436 PB |
137 | static MemoryRegionIOMMUOps spapr_iommu_ops = { |
138 | .translate = spapr_tce_translate_iommu, | |
139 | }; | |
ad0ebb91 | 140 | |
a83000f5 | 141 | static int spapr_tce_table_realize(DeviceState *dev) |
ad0ebb91 | 142 | { |
a83000f5 | 143 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); |
12fd2853 | 144 | uint64_t window_size = (uint64_t)tcet->nb_table << tcet->page_shift; |
ad0ebb91 | 145 | |
12fd2853 | 146 | if (kvm_enabled() && !(window_size >> 32)) { |
a83000f5 | 147 | tcet->table = kvmppc_create_spapr_tce(tcet->liobn, |
12fd2853 | 148 | window_size, |
9bb62a07 | 149 | &tcet->fd, |
6a81dd17 | 150 | tcet->need_vfio); |
ad0ebb91 DG |
151 | } |
152 | ||
153 | if (!tcet->table) { | |
523e7b8a | 154 | size_t table_size = tcet->nb_table * sizeof(uint64_t); |
ad0ebb91 DG |
155 | tcet->table = g_malloc0(table_size); |
156 | } | |
157 | ||
7e472264 | 158 | trace_spapr_iommu_new_table(tcet->liobn, tcet, tcet->table, tcet->fd); |
ad0ebb91 | 159 | |
a83000f5 | 160 | memory_region_init_iommu(&tcet->iommu, OBJECT(dev), &spapr_iommu_ops, |
ee9a569a AK |
161 | "iommu-spapr", |
162 | (uint64_t)tcet->nb_table << tcet->page_shift); | |
a84bb436 | 163 | |
ad0ebb91 DG |
164 | QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); |
165 | ||
00d4f525 AK |
166 | vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table, |
167 | tcet); | |
168 | ||
a83000f5 AL |
169 | return 0; |
170 | } | |
171 | ||
c10325d6 DG |
172 | void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio) |
173 | { | |
174 | size_t table_size = tcet->nb_table * sizeof(uint64_t); | |
175 | void *newtable; | |
176 | ||
177 | if (need_vfio == tcet->need_vfio) { | |
178 | /* Nothing to do */ | |
179 | return; | |
180 | } | |
181 | ||
182 | if (!need_vfio) { | |
183 | /* FIXME: We don't support transition back to KVM accelerated | |
184 | * TCEs yet */ | |
185 | return; | |
186 | } | |
187 | ||
188 | tcet->need_vfio = true; | |
189 | ||
190 | if (tcet->fd < 0) { | |
191 | /* Table is already in userspace, nothing to be do */ | |
192 | return; | |
193 | } | |
194 | ||
195 | newtable = g_malloc(table_size); | |
196 | memcpy(newtable, tcet->table, table_size); | |
197 | ||
198 | kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table); | |
199 | ||
200 | tcet->fd = -1; | |
201 | tcet->table = newtable; | |
202 | } | |
203 | ||
523e7b8a | 204 | sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, |
1b8eceee | 205 | uint64_t bus_offset, |
650f33ad | 206 | uint32_t page_shift, |
9bb62a07 | 207 | uint32_t nb_table, |
6a81dd17 | 208 | bool need_vfio) |
a83000f5 AL |
209 | { |
210 | sPAPRTCETable *tcet; | |
dea1b3ce | 211 | char tmp[64]; |
a83000f5 AL |
212 | |
213 | if (spapr_tce_find_by_liobn(liobn)) { | |
214 | fprintf(stderr, "Attempted to create TCE table with duplicate" | |
215 | " LIOBN 0x%x\n", liobn); | |
216 | return NULL; | |
217 | } | |
218 | ||
523e7b8a | 219 | if (!nb_table) { |
a83000f5 AL |
220 | return NULL; |
221 | } | |
222 | ||
223 | tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); | |
224 | tcet->liobn = liobn; | |
1b8eceee | 225 | tcet->bus_offset = bus_offset; |
650f33ad | 226 | tcet->page_shift = page_shift; |
523e7b8a | 227 | tcet->nb_table = nb_table; |
6a81dd17 | 228 | tcet->need_vfio = need_vfio; |
a83000f5 | 229 | |
dea1b3ce AK |
230 | snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn); |
231 | object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); | |
a83000f5 | 232 | |
e4c35b78 | 233 | object_property_set_bool(OBJECT(tcet), true, "realized", NULL); |
a83000f5 | 234 | |
2b7dc949 | 235 | return tcet; |
ad0ebb91 DG |
236 | } |
237 | ||
5f9490de | 238 | static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) |
ad0ebb91 | 239 | { |
5f9490de | 240 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); |
a83000f5 | 241 | |
2b7dc949 | 242 | QLIST_REMOVE(tcet, list); |
ad0ebb91 | 243 | |
2b7dc949 PB |
244 | if (!kvm_enabled() || |
245 | (kvmppc_remove_spapr_tce(tcet->table, tcet->fd, | |
523e7b8a | 246 | tcet->nb_table) != 0)) { |
2b7dc949 | 247 | g_free(tcet->table); |
ad0ebb91 DG |
248 | } |
249 | } | |
250 | ||
a84bb436 PB |
251 | MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet) |
252 | { | |
253 | return &tcet->iommu; | |
254 | } | |
255 | ||
a83000f5 | 256 | static void spapr_tce_reset(DeviceState *dev) |
eddeed26 | 257 | { |
a83000f5 | 258 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); |
523e7b8a | 259 | size_t table_size = tcet->nb_table * sizeof(uint64_t); |
eddeed26 | 260 | |
53724ee5 | 261 | memset(tcet->table, 0, table_size); |
eddeed26 DG |
262 | } |
263 | ||
edded454 DG |
264 | static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, |
265 | target_ulong tce) | |
266 | { | |
a84bb436 | 267 | IOMMUTLBEntry entry; |
650f33ad | 268 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
1b8eceee | 269 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
edded454 | 270 | |
1b8eceee | 271 | if (index >= tcet->nb_table) { |
b55519a0 | 272 | hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x" |
edded454 DG |
273 | TARGET_FMT_lx "\n", ioba); |
274 | return H_PARAMETER; | |
275 | } | |
276 | ||
1b8eceee | 277 | tcet->table[index] = tce; |
edded454 | 278 | |
a84bb436 | 279 | entry.target_as = &address_space_memory, |
650f33ad AK |
280 | entry.iova = ioba & page_mask; |
281 | entry.translated_addr = tce & page_mask; | |
282 | entry.addr_mask = ~page_mask; | |
5709af3b | 283 | entry.perm = spapr_tce_iommu_access_flags(tce); |
a84bb436 PB |
284 | memory_region_notify_iommu(&tcet->iommu, entry); |
285 | ||
edded454 DG |
286 | return H_SUCCESS; |
287 | } | |
ad0ebb91 | 288 | |
da95324e | 289 | static target_ulong h_put_tce_indirect(PowerPCCPU *cpu, |
28e02042 | 290 | sPAPRMachineState *spapr, |
da95324e AK |
291 | target_ulong opcode, target_ulong *args) |
292 | { | |
293 | int i; | |
294 | target_ulong liobn = args[0]; | |
295 | target_ulong ioba = args[1]; | |
296 | target_ulong ioba1 = ioba; | |
297 | target_ulong tce_list = args[2]; | |
298 | target_ulong npages = args[3]; | |
f1215ea7 | 299 | target_ulong ret = H_PARAMETER, tce = 0; |
da95324e AK |
300 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); |
301 | CPUState *cs = CPU(cpu); | |
650f33ad | 302 | hwaddr page_mask, page_size; |
da95324e AK |
303 | |
304 | if (!tcet) { | |
305 | return H_PARAMETER; | |
306 | } | |
307 | ||
650f33ad | 308 | if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) { |
da95324e AK |
309 | return H_PARAMETER; |
310 | } | |
311 | ||
650f33ad AK |
312 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
313 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
314 | ioba &= page_mask; | |
315 | ||
316 | for (i = 0; i < npages; ++i, ioba += page_size) { | |
4d9ab7d4 | 317 | tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong)); |
da95324e | 318 | |
da95324e AK |
319 | ret = put_tce_emu(tcet, ioba, tce); |
320 | if (ret) { | |
321 | break; | |
322 | } | |
323 | } | |
324 | ||
325 | /* Trace last successful or the first problematic entry */ | |
326 | i = i ? (i - 1) : 0; | |
d9d96a3c AK |
327 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
328 | trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
329 | } else { | |
330 | trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
331 | } | |
da95324e AK |
332 | return ret; |
333 | } | |
334 | ||
28e02042 | 335 | static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
da95324e AK |
336 | target_ulong opcode, target_ulong *args) |
337 | { | |
338 | int i; | |
339 | target_ulong liobn = args[0]; | |
340 | target_ulong ioba = args[1]; | |
341 | target_ulong tce_value = args[2]; | |
342 | target_ulong npages = args[3]; | |
343 | target_ulong ret = H_PARAMETER; | |
344 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); | |
650f33ad | 345 | hwaddr page_mask, page_size; |
da95324e AK |
346 | |
347 | if (!tcet) { | |
348 | return H_PARAMETER; | |
349 | } | |
350 | ||
351 | if (npages > tcet->nb_table) { | |
352 | return H_PARAMETER; | |
353 | } | |
354 | ||
650f33ad AK |
355 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
356 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
357 | ioba &= page_mask; | |
da95324e | 358 | |
650f33ad | 359 | for (i = 0; i < npages; ++i, ioba += page_size) { |
da95324e AK |
360 | ret = put_tce_emu(tcet, ioba, tce_value); |
361 | if (ret) { | |
362 | break; | |
363 | } | |
364 | } | |
d9d96a3c AK |
365 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
366 | trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret); | |
367 | } else { | |
368 | trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret); | |
369 | } | |
da95324e AK |
370 | |
371 | return ret; | |
372 | } | |
373 | ||
28e02042 | 374 | static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ad0ebb91 DG |
375 | target_ulong opcode, target_ulong *args) |
376 | { | |
377 | target_ulong liobn = args[0]; | |
378 | target_ulong ioba = args[1]; | |
379 | target_ulong tce = args[2]; | |
7e472264 | 380 | target_ulong ret = H_PARAMETER; |
ad0ebb91 | 381 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); |
ad0ebb91 | 382 | |
edded454 | 383 | if (tcet) { |
650f33ad AK |
384 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
385 | ||
386 | ioba &= page_mask; | |
387 | ||
7e472264 | 388 | ret = put_tce_emu(tcet, ioba, tce); |
edded454 | 389 | } |
d9d96a3c AK |
390 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
391 | trace_spapr_iommu_pci_put(liobn, ioba, tce, ret); | |
392 | } else { | |
393 | trace_spapr_iommu_put(liobn, ioba, tce, ret); | |
394 | } | |
ad0ebb91 | 395 | |
7e472264 | 396 | return ret; |
ad0ebb91 DG |
397 | } |
398 | ||
a0fcac9c LD |
399 | static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, |
400 | target_ulong *tce) | |
401 | { | |
1b8eceee AK |
402 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
403 | ||
404 | if (index >= tcet->nb_table) { | |
a0fcac9c LD |
405 | hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x" |
406 | TARGET_FMT_lx "\n", ioba); | |
407 | return H_PARAMETER; | |
408 | } | |
409 | ||
1b8eceee | 410 | *tce = tcet->table[index]; |
a0fcac9c LD |
411 | |
412 | return H_SUCCESS; | |
413 | } | |
414 | ||
28e02042 | 415 | static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a0fcac9c LD |
416 | target_ulong opcode, target_ulong *args) |
417 | { | |
418 | target_ulong liobn = args[0]; | |
419 | target_ulong ioba = args[1]; | |
420 | target_ulong tce = 0; | |
421 | target_ulong ret = H_PARAMETER; | |
422 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); | |
423 | ||
a0fcac9c | 424 | if (tcet) { |
650f33ad AK |
425 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
426 | ||
427 | ioba &= page_mask; | |
428 | ||
a0fcac9c LD |
429 | ret = get_tce_emu(tcet, ioba, &tce); |
430 | if (!ret) { | |
431 | args[0] = tce; | |
432 | } | |
433 | } | |
d9d96a3c AK |
434 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
435 | trace_spapr_iommu_pci_get(liobn, ioba, ret, tce); | |
436 | } else { | |
437 | trace_spapr_iommu_get(liobn, ioba, ret, tce); | |
438 | } | |
a0fcac9c LD |
439 | |
440 | return ret; | |
441 | } | |
442 | ||
ad0ebb91 | 443 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
5c4cbcf2 | 444 | uint32_t liobn, uint64_t window, uint32_t size) |
ad0ebb91 | 445 | { |
5c4cbcf2 AK |
446 | uint32_t dma_prop[5]; |
447 | int ret; | |
448 | ||
449 | dma_prop[0] = cpu_to_be32(liobn); | |
450 | dma_prop[1] = cpu_to_be32(window >> 32); | |
451 | dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF); | |
452 | dma_prop[3] = 0; /* window size is 32 bits */ | |
453 | dma_prop[4] = cpu_to_be32(size); | |
454 | ||
455 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2); | |
456 | if (ret < 0) { | |
457 | return ret; | |
458 | } | |
ad0ebb91 | 459 | |
5c4cbcf2 AK |
460 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2); |
461 | if (ret < 0) { | |
462 | return ret; | |
463 | } | |
ad0ebb91 | 464 | |
5c4cbcf2 AK |
465 | ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop)); |
466 | if (ret < 0) { | |
467 | return ret; | |
ad0ebb91 DG |
468 | } |
469 | ||
470 | return 0; | |
471 | } | |
5c4cbcf2 AK |
472 | |
473 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, | |
2b7dc949 | 474 | sPAPRTCETable *tcet) |
5c4cbcf2 | 475 | { |
2b7dc949 | 476 | if (!tcet) { |
5c4cbcf2 AK |
477 | return 0; |
478 | } | |
479 | ||
2b7dc949 | 480 | return spapr_dma_dt(fdt, node_off, propname, |
650f33ad | 481 | tcet->liobn, 0, tcet->nb_table << tcet->page_shift); |
5c4cbcf2 | 482 | } |
a83000f5 AL |
483 | |
484 | static void spapr_tce_table_class_init(ObjectClass *klass, void *data) | |
485 | { | |
486 | DeviceClass *dc = DEVICE_CLASS(klass); | |
a83000f5 AL |
487 | dc->init = spapr_tce_table_realize; |
488 | dc->reset = spapr_tce_reset; | |
5f9490de | 489 | dc->unrealize = spapr_tce_table_unrealize; |
a83000f5 AL |
490 | |
491 | QLIST_INIT(&spapr_tce_tables); | |
492 | ||
493 | /* hcall-tce */ | |
494 | spapr_register_hypercall(H_PUT_TCE, h_put_tce); | |
a0fcac9c | 495 | spapr_register_hypercall(H_GET_TCE, h_get_tce); |
da95324e AK |
496 | spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect); |
497 | spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); | |
a83000f5 AL |
498 | } |
499 | ||
500 | static TypeInfo spapr_tce_table_info = { | |
501 | .name = TYPE_SPAPR_TCE_TABLE, | |
502 | .parent = TYPE_DEVICE, | |
503 | .instance_size = sizeof(sPAPRTCETable), | |
504 | .class_init = spapr_tce_table_class_init, | |
a83000f5 AL |
505 | }; |
506 | ||
507 | static void register_types(void) | |
508 | { | |
509 | type_register_static(&spapr_tce_table_info); | |
510 | } | |
511 | ||
512 | type_init(register_types); |