[mirror_qemu.git] / hw / ppc / spapr_irq.c

/*
 * QEMU PowerPC sPAPR IRQ interface
 *
 * Copyright (c) 2018, IBM Corporation.
 *
 * This code is licensed under the GPL version 2 or later. See the
 * COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_xive.h"
#include "hw/ppc/xics.h"
#include "sysemu/kvm.h"

#include "trace.h"

void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
{
    spapr->irq_map_nr = nr_msis;
    spapr->irq_map = bitmap_new(spapr->irq_map_nr);
}

int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
                        Error **errp)
{
    int irq;

    /*
     * The 'align_mask' parameter of bitmap_find_next_zero_area()
     * should be one less than a power of 2; 0 means no
     * alignment. Adapt the 'align' value of the former allocator
     * to fit the requirements of bitmap_find_next_zero_area()
     */
    align -= 1;

    irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
                                     align);
    if (irq == spapr->irq_map_nr) {
        error_setg(errp, "can't find a free %d-IRQ block", num);
        return -1;
    }

    bitmap_set(spapr->irq_map, irq, num);

    return irq + SPAPR_IRQ_MSI;
}

void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
{
    bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
}

void spapr_irq_msi_reset(sPAPRMachineState *spapr)
{
    bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
}


/*
 * XICS IRQ backend.
 */

static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
                                  const char *type_ics,
                                  int nr_irqs, Error **errp)
{
    Error *local_err = NULL;
    Object *obj;

    obj = object_new(type_ics);
    object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
    object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
                                   &error_abort);
    object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
    if (local_err) {
        goto error;
    }
    object_property_set_bool(obj, true, "realized", &local_err);
    if (local_err) {
        goto error;
    }

    return ICS_BASE(obj);

error:
    error_propagate(errp, local_err);
    return NULL;
}

static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
{
    MachineState *machine = MACHINE(spapr);
    int nr_irqs = spapr->irq->nr_irqs;
    Error *local_err = NULL;

    if (kvm_enabled()) {
        if (machine_kernel_irqchip_allowed(machine) &&
            !xics_kvm_init(spapr, &local_err)) {
            spapr->icp_type = TYPE_KVM_ICP;
            spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
                                          &local_err);
        }
        if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
            error_prepend(&local_err,
                          "kernel_irqchip requested but unavailable: ");
            goto error;
        }
        error_free(local_err);
        local_err = NULL;
    }

    if (!spapr->ics) {
        xics_spapr_init(spapr);
        spapr->icp_type = TYPE_ICP;
        spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
                                      &local_err);
    }

error:
    error_propagate(errp, local_err);
}

#define ICS_IRQ_FREE(ics, srcno)   \
    (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))

static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
                                Error **errp)
{
    ICSState *ics = spapr->ics;

    assert(ics);

    if (!ics_valid_irq(ics, irq)) {
        error_setg(errp, "IRQ %d is invalid", irq);
        return -1;
    }

    if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
        error_setg(errp, "IRQ %d is not free", irq);
        return -1;
    }

    ics_set_irq_type(ics, irq - ics->offset, lsi);
    return 0;
}

static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
{
    ICSState *ics = spapr->ics;
    uint32_t srcno = irq - ics->offset;
    int i;

    if (ics_valid_irq(ics, irq)) {
        trace_spapr_irq_free(0, irq, num);
        for (i = srcno; i < srcno + num; ++i) {
            if (ICS_IRQ_FREE(ics, i)) {
                trace_spapr_irq_free_warn(0, i);
            }
            memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
        }
    }
}

static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
{
    ICSState *ics = spapr->ics;
    uint32_t srcno = irq - ics->offset;

    if (ics_valid_irq(ics, irq)) {
        return ics->qirqs[srcno];
    }

    return NULL;
}

static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
{
    CPUState *cs;

    CPU_FOREACH(cs) {
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        icp_pic_print_info(cpu->icp, mon);
    }

    ics_pic_print_info(spapr->ics, mon);
}

static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
                                           PowerPCCPU *cpu, Error **errp)
{
    Error *local_err = NULL;
    Object *obj;

    obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
                     &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    cpu->icp = ICP(obj);
}

static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
{
    if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
        CPUState *cs;
        CPU_FOREACH(cs) {
            PowerPCCPU *cpu = POWERPC_CPU(cs);
            icp_resend(cpu->icp);
        }
    }
    return 0;
}

#define SPAPR_IRQ_XICS_NR_IRQS     0x1000
#define SPAPR_IRQ_XICS_NR_MSIS     \
    (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)

sPAPRIrq spapr_irq_xics = {
    .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
    .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
    .ov5         = SPAPR_OV5_XIVE_LEGACY,

    .init        = spapr_irq_init_xics,
    .claim       = spapr_irq_claim_xics,
    .free        = spapr_irq_free_xics,
    .qirq        = spapr_qirq_xics,
    .print_info  = spapr_irq_print_info_xics,
    .dt_populate = spapr_dt_xics,
    .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
    .post_load   = spapr_irq_post_load_xics,
};

/*
 * XIVE IRQ backend.
 */
static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
{
    MachineState *machine = MACHINE(spapr);
    uint32_t nr_servers = spapr_max_server_number(spapr);
    DeviceState *dev;
    int i;

    /* KVM XIVE device not yet available */
    if (kvm_enabled()) {
        if (machine_kernel_irqchip_required(machine)) {
            error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
            return;
        }
    }

    dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
    qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
    /*
     * 8 XIVE END structures per CPU. One for each available priority
     */
    qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
    qdev_init_nofail(dev);

    spapr->xive = SPAPR_XIVE(dev);

    /* Enable the CPU IPIs */
    for (i = 0; i < nr_servers; ++i) {
        spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
    }

    spapr_xive_hcall_init(spapr);
}

static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
                                Error **errp)
{
    if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
        error_setg(errp, "IRQ %d is invalid", irq);
        return -1;
    }
    return 0;
}

static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
{
    int i;

    for (i = irq; i < irq + num; ++i) {
        spapr_xive_irq_free(spapr->xive, i);
    }
}

static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
{
    sPAPRXive *xive = spapr->xive;
    XiveSource *xsrc = &xive->source;

    if (irq >= xive->nr_irqs) {
        return NULL;
    }

    /* The sPAPR machine/device should have claimed the IRQ before */
    assert(xive_eas_is_valid(&xive->eat[irq]));

    return xsrc->qirqs[irq];
}

static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
                                      Monitor *mon)
{
    CPUState *cs;

    CPU_FOREACH(cs) {
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        xive_tctx_pic_print_info(cpu->tctx, mon);
    }

    spapr_xive_pic_print_info(spapr->xive, mon);
}

static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
                                           PowerPCCPU *cpu, Error **errp)
{
    Error *local_err = NULL;
    Object *obj;

    obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    cpu->tctx = XIVE_TCTX(obj);

    /*
     * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
     * don't beneficiate from the reset of the XIVE IRQ backend
     */
    spapr_xive_set_tctx_os_cam(cpu->tctx);
}

static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
{
    return 0;
}

static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
{
    CPUState *cs;

    CPU_FOREACH(cs) {
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        /* (TCG) Set the OS CAM line of the thread interrupt context. */
        spapr_xive_set_tctx_os_cam(cpu->tctx);
    }
}

/*
 * XIVE uses the full IRQ number space. Set it to 8K to be compatible
 * with XICS.
 */

#define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
#define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)

sPAPRIrq spapr_irq_xive = {
    .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
    .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
    .ov5         = SPAPR_OV5_XIVE_EXPLOIT,

    .init        = spapr_irq_init_xive,
    .claim       = spapr_irq_claim_xive,
    .free        = spapr_irq_free_xive,
    .qirq        = spapr_qirq_xive,
    .print_info  = spapr_irq_print_info_xive,
    .dt_populate = spapr_dt_xive,
    .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
    .post_load   = spapr_irq_post_load_xive,
    .reset       = spapr_irq_reset_xive,
};

/*
 * sPAPR IRQ frontend routines for devices
 */
void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
{
    /* Initialize the MSI IRQ allocator. */
    if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
        spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
    }

    spapr->irq->init(spapr, errp);
}

int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
{
    return spapr->irq->claim(spapr, irq, lsi, errp);
}

void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
{
    spapr->irq->free(spapr, irq, num);
}

qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
{
    return spapr->irq->qirq(spapr, irq);
}

int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
{
    return spapr->irq->post_load(spapr, version_id);
}

void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp)
{
    if (spapr->irq->reset) {
        spapr->irq->reset(spapr, errp);
    }
}

/*
 * XICS legacy routines - to deprecate one day
 */

static int ics_find_free_block(ICSState *ics, int num, int alignnum)
{
    int first, i;

    for (first = 0; first < ics->nr_irqs; first += alignnum) {
        if (num > (ics->nr_irqs - first)) {
            return -1;
        }
        for (i = first; i < first + num; ++i) {
            if (!ICS_IRQ_FREE(ics, i)) {
                break;
            }
        }
        if (i == (first + num)) {
            return first;
        }
    }

    return -1;
}

int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
{
    ICSState *ics = spapr->ics;
    int first = -1;

    assert(ics);

    /*
     * MSIMesage::data is used for storing VIRQ so
     * it has to be aligned to num to support multiple
     * MSI vectors. MSI-X is not affected by this.
     * The hint is used for the first IRQ, the rest should
     * be allocated continuously.
     */
    if (align) {
        assert((num == 1) || (num == 2) || (num == 4) ||
               (num == 8) || (num == 16) || (num == 32));
        first = ics_find_free_block(ics, num, num);
    } else {
        first = ics_find_free_block(ics, num, 1);
    }

    if (first < 0) {
        error_setg(errp, "can't find a free %d-IRQ block", num);
        return -1;
    }

    return first + ics->offset;
}

#define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400

sPAPRIrq spapr_irq_xics_legacy = {
    .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
    .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
    .ov5         = SPAPR_OV5_XIVE_LEGACY,

    .init        = spapr_irq_init_xics,
    .claim       = spapr_irq_claim_xics,
    .free        = spapr_irq_free_xics,
    .qirq        = spapr_qirq_xics,
    .print_info  = spapr_irq_print_info_xics,
    .dt_populate = spapr_dt_xics,
    .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
    .post_load   = spapr_irq_post_load_xics,
};
Commit	Line	Data
82cffa2e CLG	1	/*
	2	* QEMU PowerPC sPAPR IRQ interface
	3	*
	4	* Copyright (c) 2018, IBM Corporation.
	5	*
	6	* This code is licensed under the GPL version 2 or later. See the
	7	* COPYING file in the top-level directory.
	8	*/
	9
	10	#include "qemu/osdep.h"
	11	#include "qemu/log.h"
	12	#include "qemu/error-report.h"
	13	#include "qapi/error.h"
	14	#include "hw/ppc/spapr.h"
dcc345b6	15	#include "hw/ppc/spapr_xive.h"
82cffa2e	16	#include "hw/ppc/xics.h"
ef01ed9d CLG	17	#include "sysemu/kvm.h"
	18
	19	#include "trace.h"
82cffa2e CLG	20
	21	void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
	22	{
	23	spapr->irq_map_nr = nr_msis;
	24	spapr->irq_map = bitmap_new(spapr->irq_map_nr);
	25	}
	26
	27	int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
	28	Error **errp)
	29	{
	30	int irq;
	31
	32	/*
	33	* The 'align_mask' parameter of bitmap_find_next_zero_area()
	34	* should be one less than a power of 2; 0 means no
	35	* alignment. Adapt the 'align' value of the former allocator
	36	* to fit the requirements of bitmap_find_next_zero_area()
	37	*/
	38	align -= 1;
	39
	40	irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
	41	align);
	42	if (irq == spapr->irq_map_nr) {
	43	error_setg(errp, "can't find a free %d-IRQ block", num);
	44	return -1;
	45	}
	46
	47	bitmap_set(spapr->irq_map, irq, num);
	48
	49	return irq + SPAPR_IRQ_MSI;
	50	}
	51
	52	void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
	53	{
	54	bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
	55	}
	56
	57	void spapr_irq_msi_reset(sPAPRMachineState *spapr)
	58	{
	59	bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
	60	}
ef01ed9d CLG	61
	62
	63	/*
	64	* XICS IRQ backend.
	65	*/
	66
	67	static ICSState spapr_ics_create(sPAPRMachineState spapr,
	68	const char *type_ics,
	69	int nr_irqs, Error **errp)
	70	{
	71	Error *local_err = NULL;
	72	Object *obj;
	73
	74	obj = object_new(type_ics);
	75	object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
	76	object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
	77	&error_abort);
	78	object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
	79	if (local_err) {
	80	goto error;
	81	}
	82	object_property_set_bool(obj, true, "realized", &local_err);
	83	if (local_err) {
	84	goto error;
	85	}
	86
	87	return ICS_BASE(obj);
	88
	89	error:
	90	error_propagate(errp, local_err);
	91	return NULL;
	92	}
	93
	94	static void spapr_irq_init_xics(sPAPRMachineState spapr, Error *errp)
	95	{
	96	MachineState *machine = MACHINE(spapr);
3ba3d0bc	97	int nr_irqs = spapr->irq->nr_irqs;
ef01ed9d CLG	98	Error *local_err = NULL;
ef01ed9d CLG	99
ef01ed9d CLG	100	if (kvm_enabled()) {
	101	if (machine_kernel_irqchip_allowed(machine) &&
	102	!xics_kvm_init(spapr, &local_err)) {
	103	spapr->icp_type = TYPE_KVM_ICP;
	104	spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
	105	&local_err);
	106	}
	107	if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
	108	error_prepend(&local_err,
	109	"kernel_irqchip requested but unavailable: ");
	110	goto error;
	111	}
	112	error_free(local_err);
	113	local_err = NULL;
	114	}
	115
	116	if (!spapr->ics) {
	117	xics_spapr_init(spapr);
	118	spapr->icp_type = TYPE_ICP;
	119	spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
	120	&local_err);
	121	}
	122
	123	error:
	124	error_propagate(errp, local_err);
	125	}
	126
	127	#define ICS_IRQ_FREE(ics, srcno) \
	128	(!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
	129
	130	static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
	131	Error **errp)
	132	{
	133	ICSState *ics = spapr->ics;
	134
	135	assert(ics);
	136
	137	if (!ics_valid_irq(ics, irq)) {
	138	error_setg(errp, "IRQ %d is invalid", irq);
	139	return -1;
	140	}
	141
	142	if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
	143	error_setg(errp, "IRQ %d is not free", irq);
	144	return -1;
	145	}
	146
	147	ics_set_irq_type(ics, irq - ics->offset, lsi);
	148	return 0;
	149	}
	150
	151	static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
	152	{
	153	ICSState *ics = spapr->ics;
	154	uint32_t srcno = irq - ics->offset;
	155	int i;
	156
	157	if (ics_valid_irq(ics, irq)) {
	158	trace_spapr_irq_free(0, irq, num);
	159	for (i = srcno; i < srcno + num; ++i) {
	160	if (ICS_IRQ_FREE(ics, i)) {
	161	trace_spapr_irq_free_warn(0, i);
	162	}
	163	memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
164	}
165	}
166	}
167
168	static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
169	{
170	ICSState *ics = spapr->ics;
171	uint32_t srcno = irq - ics->offset;
172
173	if (ics_valid_irq(ics, irq)) {
174	return ics->qirqs[srcno];
175	}
176
177	return NULL;
178	}
179
180	static void spapr_irq_print_info_xics(sPAPRMachineState spapr, Monitor mon)
181	{
182	CPUState *cs;
183
184	CPU_FOREACH(cs) {
185	PowerPCCPU *cpu = POWERPC_CPU(cs);
186
3ff73aa2	187	icp_pic_print_info(cpu->icp, mon);
ef01ed9d CLG	188	}
	189
	190	ics_pic_print_info(spapr->ics, mon);
	191	}
	192
8fa1f4ef CLG	193	static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
8fa1f4ef CLG	194	PowerPCCPU cpu, Error *errp)
1a937ad7	195	{
8fa1f4ef CLG	196	Error *local_err = NULL;
	197	Object *obj;
	198
	199	obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
	200	&local_err);
	201	if (local_err) {
	202	error_propagate(errp, local_err);
	203	return;
	204	}
	205
3ff73aa2	206	cpu->icp = ICP(obj);
1a937ad7 CLG	207	}
1a937ad7 CLG	208
1c53b06c CLG	209	static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
	210	{
	211	if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
	212	CPUState *cs;
	213	CPU_FOREACH(cs) {
	214	PowerPCCPU *cpu = POWERPC_CPU(cs);
3ff73aa2	215	icp_resend(cpu->icp);
1c53b06c CLG	216	}
	217	}
	218	return 0;
	219	}
	220
ae837402	221	#define SPAPR_IRQ_XICS_NR_IRQS 0x1000
e39de895 CLG	222	#define SPAPR_IRQ_XICS_NR_MSIS \
	223	(XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
	224
ef01ed9d	225	sPAPRIrq spapr_irq_xics = {
e39de895 CLG	226	.nr_irqs = SPAPR_IRQ_XICS_NR_IRQS,
e39de895 CLG	227	.nr_msis = SPAPR_IRQ_XICS_NR_MSIS,
db592b5b	228	.ov5 = SPAPR_OV5_XIVE_LEGACY,
ef01ed9d CLG	229
	230	.init = spapr_irq_init_xics,
	231	.claim = spapr_irq_claim_xics,
	232	.free = spapr_irq_free_xics,
	233	.qirq = spapr_qirq_xics,
	234	.print_info = spapr_irq_print_info_xics,
6e21de4a	235	.dt_populate = spapr_dt_xics,
1a937ad7	236	.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
1c53b06c	237	.post_load = spapr_irq_post_load_xics,
ef01ed9d CLG	238	};
ef01ed9d CLG	239
dcc345b6 CLG	240	/*
	241	* XIVE IRQ backend.
	242	*/
	243	static void spapr_irq_init_xive(sPAPRMachineState spapr, Error *errp)
	244	{
	245	MachineState *machine = MACHINE(spapr);
dcc345b6 CLG	246	uint32_t nr_servers = spapr_max_server_number(spapr);
	247	DeviceState *dev;
	248	int i;
	249
	250	/* KVM XIVE device not yet available */
	251	if (kvm_enabled()) {
	252	if (machine_kernel_irqchip_required(machine)) {
	253	error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
	254	return;
	255	}
	256	}
	257
	258	dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
3ba3d0bc	259	qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
dcc345b6 CLG	260	/*
	261	* 8 XIVE END structures per CPU. One for each available priority
	262	*/
	263	qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
	264	qdev_init_nofail(dev);
	265
	266	spapr->xive = SPAPR_XIVE(dev);
	267
	268	/* Enable the CPU IPIs */
	269	for (i = 0; i < nr_servers; ++i) {
	270	spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
	271	}
23bcd5eb CLG	272
23bcd5eb CLG	273	spapr_xive_hcall_init(spapr);
dcc345b6 CLG	274	}
	275
	276	static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
	277	Error **errp)
	278	{
	279	if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
	280	error_setg(errp, "IRQ %d is invalid", irq);
	281	return -1;
	282	}
	283	return 0;
	284	}
	285
	286	static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
	287	{
	288	int i;
	289
	290	for (i = irq; i < irq + num; ++i) {
	291	spapr_xive_irq_free(spapr->xive, i);
	292	}
	293	}
	294
	295	static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
	296	{
a0c493ae CLG	297	sPAPRXive *xive = spapr->xive;
	298	XiveSource *xsrc = &xive->source;
	299
	300	if (irq >= xive->nr_irqs) {
	301	return NULL;
	302	}
	303
	304	/* The sPAPR machine/device should have claimed the IRQ before */
	305	assert(xive_eas_is_valid(&xive->eat[irq]));
	306
	307	return xsrc->qirqs[irq];
dcc345b6 CLG	308	}
	309
	310	static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
	311	Monitor *mon)
	312	{
	313	CPUState *cs;
	314
	315	CPU_FOREACH(cs) {
	316	PowerPCCPU *cpu = POWERPC_CPU(cs);
	317
129dbe69	318	xive_tctx_pic_print_info(cpu->tctx, mon);
dcc345b6 CLG	319	}
	320
	321	spapr_xive_pic_print_info(spapr->xive, mon);
	322	}
	323
8fa1f4ef CLG	324	static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
8fa1f4ef CLG	325	PowerPCCPU cpu, Error *errp)
1a937ad7	326	{
8fa1f4ef CLG	327	Error *local_err = NULL;
	328	Object *obj;
	329
	330	obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
	331	if (local_err) {
	332	error_propagate(errp, local_err);
	333	return;
	334	}
	335
129dbe69	336	cpu->tctx = XIVE_TCTX(obj);
b2e22477 CLG	337
	338	/*
	339	* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
8fa1f4ef	340	* don't beneficiate from the reset of the XIVE IRQ backend
b2e22477	341	*/
129dbe69	342	spapr_xive_set_tctx_os_cam(cpu->tctx);
1a937ad7 CLG	343	}
1a937ad7 CLG	344
1c53b06c CLG	345	static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
	346	{
	347	return 0;
	348	}
	349
b2e22477 CLG	350	static void spapr_irq_reset_xive(sPAPRMachineState spapr, Error *errp)
	351	{
	352	CPUState *cs;
	353
	354	CPU_FOREACH(cs) {
	355	PowerPCCPU *cpu = POWERPC_CPU(cs);
	356
	357	/* (TCG) Set the OS CAM line of the thread interrupt context. */
129dbe69	358	spapr_xive_set_tctx_os_cam(cpu->tctx);
b2e22477 CLG	359	}
	360	}
	361
dcc345b6 CLG	362	/*
	363	* XIVE uses the full IRQ number space. Set it to 8K to be compatible
	364	* with XICS.
	365	*/
	366
	367	#define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
	368	#define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
	369
	370	sPAPRIrq spapr_irq_xive = {
	371	.nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS,
	372	.nr_msis = SPAPR_IRQ_XIVE_NR_MSIS,
db592b5b	373	.ov5 = SPAPR_OV5_XIVE_EXPLOIT,
dcc345b6 CLG	374
	375	.init = spapr_irq_init_xive,
	376	.claim = spapr_irq_claim_xive,
	377	.free = spapr_irq_free_xive,
	378	.qirq = spapr_qirq_xive,
	379	.print_info = spapr_irq_print_info_xive,
6e21de4a	380	.dt_populate = spapr_dt_xive,
1a937ad7	381	.cpu_intc_create = spapr_irq_cpu_intc_create_xive,
1c53b06c	382	.post_load = spapr_irq_post_load_xive,
b2e22477	383	.reset = spapr_irq_reset_xive,
dcc345b6 CLG	384	};
dcc345b6 CLG	385
ef01ed9d CLG	386	/*
	387	* sPAPR IRQ frontend routines for devices
	388	*/
fab397d8 CLG	389	void spapr_irq_init(sPAPRMachineState spapr, Error *errp)
fab397d8 CLG	390	{
fab397d8 CLG	391	/* Initialize the MSI IRQ allocator. */
fab397d8 CLG	392	if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3ba3d0bc	393	spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
fab397d8 CLG	394	}
fab397d8 CLG	395
3ba3d0bc	396	spapr->irq->init(spapr, errp);
fab397d8	397	}
ef01ed9d CLG	398
	399	int spapr_irq_claim(sPAPRMachineState spapr, int irq, bool lsi, Error *errp)
	400	{
3ba3d0bc	401	return spapr->irq->claim(spapr, irq, lsi, errp);
ef01ed9d CLG	402	}
	403
	404	void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
	405	{
3ba3d0bc	406	spapr->irq->free(spapr, irq, num);
ef01ed9d CLG	407	}
	408
	409	qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
	410	{
3ba3d0bc	411	return spapr->irq->qirq(spapr, irq);
ef01ed9d CLG	412	}
ef01ed9d CLG	413
1c53b06c CLG	414	int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
1c53b06c CLG	415	{
3ba3d0bc	416	return spapr->irq->post_load(spapr, version_id);
1c53b06c CLG	417	}
1c53b06c CLG	418
b2e22477 CLG	419	void spapr_irq_reset(sPAPRMachineState spapr, Error *errp)
b2e22477 CLG	420	{
3ba3d0bc CLG	421	if (spapr->irq->reset) {
3ba3d0bc CLG	422	spapr->irq->reset(spapr, errp);
b2e22477 CLG	423	}
	424	}
	425
ef01ed9d CLG	426	/*
	427	* XICS legacy routines - to deprecate one day
	428	*/
	429
	430	static int ics_find_free_block(ICSState *ics, int num, int alignnum)
	431	{
	432	int first, i;
	433
	434	for (first = 0; first < ics->nr_irqs; first += alignnum) {
	435	if (num > (ics->nr_irqs - first)) {
	436	return -1;
	437	}
	438	for (i = first; i < first + num; ++i) {
	439	if (!ICS_IRQ_FREE(ics, i)) {
	440	break;
	441	}
	442	}
	443	if (i == (first + num)) {
	444	return first;
	445	}
	446	}
	447
	448	return -1;
	449	}
	450
	451	int spapr_irq_find(sPAPRMachineState spapr, int num, bool align, Error *errp)
	452	{
	453	ICSState *ics = spapr->ics;
	454	int first = -1;
	455
	456	assert(ics);
	457
	458	/*
	459	* MSIMesage::data is used for storing VIRQ so
	460	* it has to be aligned to num to support multiple
	461	* MSI vectors. MSI-X is not affected by this.
	462	* The hint is used for the first IRQ, the rest should
	463	* be allocated continuously.
	464	*/
	465	if (align) {
	466	assert((num == 1) \|\| (num == 2) \|\| (num == 4) \|\|
	467	(num == 8) \|\| (num == 16) \|\| (num == 32));
	468	first = ics_find_free_block(ics, num, num);
	469	} else {
	470	first = ics_find_free_block(ics, num, 1);
	471	}
	472
	473	if (first < 0) {
	474	error_setg(errp, "can't find a free %d-IRQ block", num);
	475	return -1;
	476	}
	477
	478	return first + ics->offset;
	479	}
ae837402 CLG	480
	481	#define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
	482
	483	sPAPRIrq spapr_irq_xics_legacy = {
	484	.nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
	485	.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
db592b5b	486	.ov5 = SPAPR_OV5_XIVE_LEGACY,
ae837402 CLG	487
	488	.init = spapr_irq_init_xics,
	489	.claim = spapr_irq_claim_xics,
	490	.free = spapr_irq_free_xics,
	491	.qirq = spapr_qirq_xics,
	492	.print_info = spapr_irq_print_info_xics,
6e21de4a	493	.dt_populate = spapr_dt_xics,
1a937ad7	494	.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
1c53b06c	495	.post_load = spapr_irq_post_load_xics,
ae837402	496	};