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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0d75590d | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 PB |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" | |
83c9f4ca | 29 | #include "hw/hw.h" |
1d2d9742 | 30 | #include "hw/sysbus.h" |
83c9f4ca PB |
31 | #include "hw/pci/pci.h" |
32 | #include "hw/pci/msi.h" | |
33 | #include "hw/pci/msix.h" | |
34 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
35 | #include "hw/ppc/spapr.h" |
36 | #include "hw/pci-host/spapr.h" | |
022c62cb | 37 | #include "exec/address-spaces.h" |
ae4de14c | 38 | #include "exec/ram_addr.h" |
3384f95c | 39 | #include <libfdt.h> |
a2950fb6 | 40 | #include "trace.h" |
295d51aa | 41 | #include "qemu/error-report.h" |
7454c7af | 42 | #include "qapi/qmp/qerror.h" |
99372e78 | 43 | #include "hw/ppc/fdt.h" |
1d2d9742 | 44 | #include "hw/pci/pci_bridge.h" |
06aac7bd | 45 | #include "hw/pci/pci_bus.h" |
2530a1a5 | 46 | #include "hw/pci/pci_ids.h" |
62083979 | 47 | #include "hw/ppc/spapr_drc.h" |
7454c7af | 48 | #include "sysemu/device_tree.h" |
77ac58dd | 49 | #include "sysemu/kvm.h" |
ae4de14c | 50 | #include "sysemu/hostmem.h" |
4814401f | 51 | #include "sysemu/numa.h" |
3384f95c | 52 | |
0ee2c058 AK |
53 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
54 | #define RTAS_QUERY_FN 0 | |
55 | #define RTAS_CHANGE_FN 1 | |
56 | #define RTAS_RESET_FN 2 | |
57 | #define RTAS_CHANGE_MSI_FN 3 | |
58 | #define RTAS_CHANGE_MSIX_FN 4 | |
59 | ||
60 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
61 | #define RTAS_TYPE_MSI 1 | |
62 | #define RTAS_TYPE_MSIX 2 | |
63 | ||
ce2918cb | 64 | SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) |
3384f95c | 65 | { |
ce2918cb | 66 | SpaprPhbState *sphb; |
3384f95c | 67 | |
8c9f64df AF |
68 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
69 | if (sphb->buid != buid) { | |
3384f95c DG |
70 | continue; |
71 | } | |
8c9f64df | 72 | return sphb; |
9894c5d4 AK |
73 | } |
74 | ||
75 | return NULL; | |
76 | } | |
77 | ||
ce2918cb | 78 | PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, |
46c5874e | 79 | uint32_t config_addr) |
9894c5d4 | 80 | { |
ce2918cb | 81 | SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 82 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 83 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
84 | int devfn = (config_addr >> 8) & 0xFF; |
85 | ||
86 | if (!phb) { | |
87 | return NULL; | |
88 | } | |
3384f95c | 89 | |
5dac82ce | 90 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
91 | } |
92 | ||
3f7565c9 BH |
93 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
94 | { | |
92615a5a | 95 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
96 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
97 | } | |
98 | ||
ce2918cb | 99 | static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, |
92615a5a DG |
100 | uint32_t addr, uint32_t size, |
101 | target_ulong rets) | |
88045ac5 | 102 | { |
92615a5a DG |
103 | PCIDevice *pci_dev; |
104 | uint32_t val; | |
105 | ||
106 | if ((size != 1) && (size != 2) && (size != 4)) { | |
107 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 108 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 109 | return; |
88045ac5 | 110 | } |
88045ac5 | 111 | |
46c5874e | 112 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
113 | addr = rtas_pci_cfgaddr(addr); |
114 | ||
115 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
116 | /* Access must be to a valid device, within bounds and | |
117 | * naturally aligned */ | |
a64d325d | 118 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 119 | return; |
88045ac5 | 120 | } |
92615a5a DG |
121 | |
122 | val = pci_host_config_read_common(pci_dev, addr, | |
123 | pci_config_size(pci_dev), size); | |
124 | ||
a64d325d | 125 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 126 | rtas_st(rets, 1, val); |
88045ac5 AG |
127 | } |
128 | ||
ce2918cb | 129 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
130 | uint32_t token, uint32_t nargs, |
131 | target_ulong args, | |
132 | uint32_t nret, target_ulong rets) | |
133 | { | |
92615a5a DG |
134 | uint64_t buid; |
135 | uint32_t size, addr; | |
3384f95c | 136 | |
92615a5a | 137 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 138 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
139 | return; |
140 | } | |
92615a5a | 141 | |
a14aa92b | 142 | buid = rtas_ldq(args, 1); |
3384f95c | 143 | size = rtas_ld(args, 3); |
92615a5a DG |
144 | addr = rtas_ld(args, 0); |
145 | ||
146 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
147 | } |
148 | ||
ce2918cb | 149 | static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
150 | uint32_t token, uint32_t nargs, |
151 | target_ulong args, | |
152 | uint32_t nret, target_ulong rets) | |
153 | { | |
92615a5a | 154 | uint32_t size, addr; |
3384f95c | 155 | |
92615a5a | 156 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 157 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
158 | return; |
159 | } | |
92615a5a | 160 | |
3384f95c | 161 | size = rtas_ld(args, 1); |
92615a5a DG |
162 | addr = rtas_ld(args, 0); |
163 | ||
164 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
165 | } | |
166 | ||
ce2918cb | 167 | static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, |
92615a5a DG |
168 | uint32_t addr, uint32_t size, |
169 | uint32_t val, target_ulong rets) | |
170 | { | |
171 | PCIDevice *pci_dev; | |
172 | ||
173 | if ((size != 1) && (size != 2) && (size != 4)) { | |
174 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 175 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
176 | return; |
177 | } | |
178 | ||
46c5874e | 179 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
180 | addr = rtas_pci_cfgaddr(addr); |
181 | ||
182 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
183 | /* Access must be to a valid device, within bounds and | |
184 | * naturally aligned */ | |
a64d325d | 185 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
186 | return; |
187 | } | |
188 | ||
189 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
190 | val, size); | |
191 | ||
a64d325d | 192 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
193 | } |
194 | ||
ce2918cb | 195 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
196 | uint32_t token, uint32_t nargs, |
197 | target_ulong args, | |
198 | uint32_t nret, target_ulong rets) | |
199 | { | |
92615a5a | 200 | uint64_t buid; |
3384f95c | 201 | uint32_t val, size, addr; |
3384f95c | 202 | |
92615a5a | 203 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 204 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
205 | return; |
206 | } | |
92615a5a | 207 | |
a14aa92b | 208 | buid = rtas_ldq(args, 1); |
3384f95c DG |
209 | val = rtas_ld(args, 4); |
210 | size = rtas_ld(args, 3); | |
92615a5a DG |
211 | addr = rtas_ld(args, 0); |
212 | ||
213 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
214 | } |
215 | ||
ce2918cb | 216 | static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
217 | uint32_t token, uint32_t nargs, |
218 | target_ulong args, | |
219 | uint32_t nret, target_ulong rets) | |
220 | { | |
221 | uint32_t val, size, addr; | |
3384f95c | 222 | |
92615a5a | 223 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 224 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
225 | return; |
226 | } | |
92615a5a DG |
227 | |
228 | ||
3384f95c DG |
229 | val = rtas_ld(args, 2); |
230 | size = rtas_ld(args, 1); | |
92615a5a DG |
231 | addr = rtas_ld(args, 0); |
232 | ||
233 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
234 | } |
235 | ||
0ee2c058 AK |
236 | /* |
237 | * Set MSI/MSIX message data. | |
238 | * This is required for msi_notify()/msix_notify() which | |
239 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
240 | * |
241 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
242 | * table will be reset. | |
0ee2c058 | 243 | */ |
f1c2dc7c AK |
244 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
245 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
246 | { |
247 | unsigned i; | |
f1c2dc7c | 248 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
249 | |
250 | if (!msix) { | |
251 | msi_set_message(pdev, msg); | |
252 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
253 | return; | |
254 | } | |
255 | ||
9a321e92 | 256 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
257 | msix_set_message(pdev, i, msg); |
258 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
259 | if (addr) { |
260 | ++msg.data; | |
261 | } | |
0ee2c058 AK |
262 | } |
263 | } | |
264 | ||
ce2918cb | 265 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, |
0ee2c058 AK |
266 | uint32_t token, uint32_t nargs, |
267 | target_ulong args, uint32_t nret, | |
268 | target_ulong rets) | |
269 | { | |
ce2918cb | 270 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
0ee2c058 | 271 | uint32_t config_addr = rtas_ld(args, 0); |
a14aa92b | 272 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 AK |
273 | unsigned int func = rtas_ld(args, 3); |
274 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
275 | unsigned int seq_num = rtas_ld(args, 5); | |
276 | unsigned int ret_intr_type; | |
d4a63ac8 | 277 | unsigned int irq, max_irqs = 0; |
ce2918cb | 278 | SpaprPhbState *phb = NULL; |
0ee2c058 | 279 | PCIDevice *pdev = NULL; |
9a321e92 AK |
280 | spapr_pci_msi *msi; |
281 | int *config_addr_key; | |
a005b3ef | 282 | Error *err = NULL; |
4fe75a8c | 283 | int i; |
0ee2c058 | 284 | |
ce2918cb | 285 | /* Fins SpaprPhbState */ |
9cbe305b GK |
286 | phb = spapr_pci_find_phb(spapr, buid); |
287 | if (phb) { | |
288 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); | |
289 | } | |
290 | if (!phb || !pdev) { | |
291 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
292 | return; | |
293 | } | |
294 | ||
0ee2c058 | 295 | switch (func) { |
0ee2c058 | 296 | case RTAS_CHANGE_FN: |
9cbe305b GK |
297 | if (msi_present(pdev)) { |
298 | ret_intr_type = RTAS_TYPE_MSI; | |
299 | } else if (msix_present(pdev)) { | |
300 | ret_intr_type = RTAS_TYPE_MSIX; | |
301 | } else { | |
302 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
303 | return; | |
304 | } | |
305 | break; | |
306 | case RTAS_CHANGE_MSI_FN: | |
307 | if (msi_present(pdev)) { | |
308 | ret_intr_type = RTAS_TYPE_MSI; | |
309 | } else { | |
310 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
311 | return; | |
312 | } | |
0ee2c058 AK |
313 | break; |
314 | case RTAS_CHANGE_MSIX_FN: | |
9cbe305b GK |
315 | if (msix_present(pdev)) { |
316 | ret_intr_type = RTAS_TYPE_MSIX; | |
317 | } else { | |
318 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
319 | return; | |
320 | } | |
0ee2c058 AK |
321 | break; |
322 | default: | |
295d51aa | 323 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 324 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
325 | return; |
326 | } | |
327 | ||
ce266b75 GK |
328 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
329 | ||
0ee2c058 AK |
330 | /* Releasing MSIs */ |
331 | if (!req_num) { | |
9a321e92 AK |
332 | if (!msi) { |
333 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 334 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
335 | return; |
336 | } | |
9a321e92 | 337 | |
2c88b098 | 338 | if (!smc->legacy_irq_allocation) { |
82cffa2e CLG |
339 | spapr_irq_msi_free(spapr, msi->first_irq, msi->num); |
340 | } | |
60c6823b | 341 | spapr_irq_free(spapr, msi->first_irq, msi->num); |
32420522 | 342 | if (msi_present(pdev)) { |
d4a63ac8 | 343 | spapr_msi_setmsg(pdev, 0, false, 0, 0); |
32420522 AK |
344 | } |
345 | if (msix_present(pdev)) { | |
d4a63ac8 | 346 | spapr_msi_setmsg(pdev, 0, true, 0, 0); |
32420522 | 347 | } |
9a321e92 AK |
348 | g_hash_table_remove(phb->msi, &config_addr); |
349 | ||
350 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 351 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
352 | rtas_st(rets, 1, 0); |
353 | return; | |
354 | } | |
355 | ||
356 | /* Enabling MSI */ | |
357 | ||
28668b5f AK |
358 | /* Check if the device supports as many IRQs as requested */ |
359 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
360 | max_irqs = msi_nr_vectors_allocated(pdev); | |
361 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
362 | max_irqs = pdev->msix_entries_nr; | |
363 | } | |
364 | if (!max_irqs) { | |
9a321e92 AK |
365 | error_report("Requested interrupt type %d is not enabled for device %x", |
366 | ret_intr_type, config_addr); | |
28668b5f AK |
367 | rtas_st(rets, 0, -1); /* Hardware error */ |
368 | return; | |
369 | } | |
370 | /* Correct the number if the guest asked for too many */ | |
371 | if (req_num > max_irqs) { | |
9a321e92 | 372 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 373 | req_num = max_irqs; |
9a321e92 AK |
374 | irq = 0; /* to avoid misleading trace */ |
375 | goto out; | |
28668b5f AK |
376 | } |
377 | ||
9a321e92 | 378 | /* Allocate MSIs */ |
2c88b098 | 379 | if (smc->legacy_irq_allocation) { |
82cffa2e CLG |
380 | irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, |
381 | &err); | |
382 | } else { | |
383 | irq = spapr_irq_msi_alloc(spapr, req_num, | |
384 | ret_intr_type == RTAS_TYPE_MSI, &err); | |
385 | } | |
a005b3ef GK |
386 | if (err) { |
387 | error_reportf_err(err, "Can't allocate MSIs for device %x: ", | |
388 | config_addr); | |
a64d325d | 389 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
390 | return; |
391 | } | |
392 | ||
4fe75a8c CLG |
393 | for (i = 0; i < req_num; i++) { |
394 | spapr_irq_claim(spapr, irq + i, false, &err); | |
395 | if (err) { | |
925969c3 GK |
396 | if (i) { |
397 | spapr_irq_free(spapr, irq, i); | |
398 | } | |
399 | if (!smc->legacy_irq_allocation) { | |
400 | spapr_irq_msi_free(spapr, irq, req_num); | |
401 | } | |
4fe75a8c CLG |
402 | error_reportf_err(err, "Can't allocate MSIs for device %x: ", |
403 | config_addr); | |
404 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); | |
405 | return; | |
406 | } | |
407 | } | |
408 | ||
ce266b75 GK |
409 | /* Release previous MSIs */ |
410 | if (msi) { | |
2c88b098 | 411 | if (!smc->legacy_irq_allocation) { |
82cffa2e CLG |
412 | spapr_irq_msi_free(spapr, msi->first_irq, msi->num); |
413 | } | |
60c6823b | 414 | spapr_irq_free(spapr, msi->first_irq, msi->num); |
ce266b75 GK |
415 | g_hash_table_remove(phb->msi, &config_addr); |
416 | } | |
417 | ||
0ee2c058 | 418 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 419 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 420 | irq, req_num); |
0ee2c058 | 421 | |
9a321e92 AK |
422 | /* Add MSI device to cache */ |
423 | msi = g_new(spapr_pci_msi, 1); | |
424 | msi->first_irq = irq; | |
425 | msi->num = req_num; | |
426 | config_addr_key = g_new(int, 1); | |
427 | *config_addr_key = config_addr; | |
428 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
429 | ||
430 | out: | |
a64d325d | 431 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
432 | rtas_st(rets, 1, req_num); |
433 | rtas_st(rets, 2, ++seq_num); | |
b359bd6a SB |
434 | if (nret > 3) { |
435 | rtas_st(rets, 3, ret_intr_type); | |
436 | } | |
0ee2c058 | 437 | |
9a321e92 | 438 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
439 | } |
440 | ||
210b580b | 441 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
ce2918cb | 442 | SpaprMachineState *spapr, |
0ee2c058 AK |
443 | uint32_t token, |
444 | uint32_t nargs, | |
445 | target_ulong args, | |
446 | uint32_t nret, | |
447 | target_ulong rets) | |
448 | { | |
449 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 450 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 | 451 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); |
ce2918cb | 452 | SpaprPhbState *phb = NULL; |
9a321e92 AK |
453 | PCIDevice *pdev = NULL; |
454 | spapr_pci_msi *msi; | |
0ee2c058 | 455 | |
ce2918cb | 456 | /* Find SpaprPhbState */ |
46c5874e | 457 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 458 | if (phb) { |
46c5874e | 459 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
460 | } |
461 | if (!phb || !pdev) { | |
a64d325d | 462 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
463 | return; |
464 | } | |
465 | ||
466 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
467 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
468 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
469 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 470 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
471 | return; |
472 | } | |
9a321e92 | 473 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
474 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
475 | intr_src_num); | |
476 | ||
a64d325d | 477 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
478 | rtas_st(rets, 1, intr_src_num); |
479 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
480 | } | |
481 | ||
ee954280 | 482 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
ce2918cb | 483 | SpaprMachineState *spapr, |
ee954280 GS |
484 | uint32_t token, uint32_t nargs, |
485 | target_ulong args, uint32_t nret, | |
486 | target_ulong rets) | |
487 | { | |
ce2918cb | 488 | SpaprPhbState *sphb; |
ee954280 GS |
489 | uint32_t addr, option; |
490 | uint64_t buid; | |
491 | int ret; | |
492 | ||
493 | if ((nargs != 4) || (nret != 1)) { | |
494 | goto param_error_exit; | |
495 | } | |
496 | ||
a14aa92b | 497 | buid = rtas_ldq(args, 1); |
ee954280 GS |
498 | addr = rtas_ld(args, 0); |
499 | option = rtas_ld(args, 3); | |
500 | ||
46c5874e | 501 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
502 | if (!sphb) { |
503 | goto param_error_exit; | |
504 | } | |
505 | ||
fbb4e983 | 506 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
507 | goto param_error_exit; |
508 | } | |
509 | ||
fbb4e983 | 510 | ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); |
ee954280 GS |
511 | rtas_st(rets, 0, ret); |
512 | return; | |
513 | ||
514 | param_error_exit: | |
515 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
516 | } | |
517 | ||
518 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
ce2918cb | 519 | SpaprMachineState *spapr, |
ee954280 GS |
520 | uint32_t token, uint32_t nargs, |
521 | target_ulong args, uint32_t nret, | |
522 | target_ulong rets) | |
523 | { | |
ce2918cb | 524 | SpaprPhbState *sphb; |
ee954280 GS |
525 | PCIDevice *pdev; |
526 | uint32_t addr, option; | |
527 | uint64_t buid; | |
528 | ||
529 | if ((nargs != 4) || (nret != 2)) { | |
530 | goto param_error_exit; | |
531 | } | |
532 | ||
a14aa92b | 533 | buid = rtas_ldq(args, 1); |
46c5874e | 534 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
535 | if (!sphb) { |
536 | goto param_error_exit; | |
537 | } | |
538 | ||
fbb4e983 | 539 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
540 | goto param_error_exit; |
541 | } | |
542 | ||
543 | /* | |
544 | * We always have PE address of form "00BB0001". "BB" | |
545 | * represents the bus number of PE's primary bus. | |
546 | */ | |
547 | option = rtas_ld(args, 3); | |
548 | switch (option) { | |
549 | case RTAS_GET_PE_ADDR: | |
550 | addr = rtas_ld(args, 0); | |
46c5874e | 551 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
552 | if (!pdev) { |
553 | goto param_error_exit; | |
554 | } | |
555 | ||
fd56e061 | 556 | rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); |
ee954280 GS |
557 | break; |
558 | case RTAS_GET_PE_MODE: | |
559 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
560 | break; | |
561 | default: | |
562 | goto param_error_exit; | |
563 | } | |
564 | ||
565 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
566 | return; | |
567 | ||
568 | param_error_exit: | |
569 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
570 | } | |
571 | ||
572 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
ce2918cb | 573 | SpaprMachineState *spapr, |
ee954280 GS |
574 | uint32_t token, uint32_t nargs, |
575 | target_ulong args, uint32_t nret, | |
576 | target_ulong rets) | |
577 | { | |
ce2918cb | 578 | SpaprPhbState *sphb; |
ee954280 GS |
579 | uint64_t buid; |
580 | int state, ret; | |
581 | ||
582 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
583 | goto param_error_exit; | |
584 | } | |
585 | ||
a14aa92b | 586 | buid = rtas_ldq(args, 1); |
46c5874e | 587 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
588 | if (!sphb) { |
589 | goto param_error_exit; | |
590 | } | |
591 | ||
fbb4e983 | 592 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
593 | goto param_error_exit; |
594 | } | |
595 | ||
fbb4e983 | 596 | ret = spapr_phb_vfio_eeh_get_state(sphb, &state); |
ee954280 GS |
597 | rtas_st(rets, 0, ret); |
598 | if (ret != RTAS_OUT_SUCCESS) { | |
599 | return; | |
600 | } | |
601 | ||
602 | rtas_st(rets, 1, state); | |
603 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
604 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
605 | if (nret >= 5) { | |
606 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
607 | } | |
608 | return; | |
609 | ||
610 | param_error_exit: | |
611 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
612 | } | |
613 | ||
614 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
ce2918cb | 615 | SpaprMachineState *spapr, |
ee954280 GS |
616 | uint32_t token, uint32_t nargs, |
617 | target_ulong args, uint32_t nret, | |
618 | target_ulong rets) | |
619 | { | |
ce2918cb | 620 | SpaprPhbState *sphb; |
ee954280 GS |
621 | uint32_t option; |
622 | uint64_t buid; | |
623 | int ret; | |
624 | ||
625 | if ((nargs != 4) || (nret != 1)) { | |
626 | goto param_error_exit; | |
627 | } | |
628 | ||
a14aa92b | 629 | buid = rtas_ldq(args, 1); |
ee954280 | 630 | option = rtas_ld(args, 3); |
46c5874e | 631 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
632 | if (!sphb) { |
633 | goto param_error_exit; | |
634 | } | |
635 | ||
fbb4e983 | 636 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
637 | goto param_error_exit; |
638 | } | |
639 | ||
fbb4e983 | 640 | ret = spapr_phb_vfio_eeh_reset(sphb, option); |
ee954280 GS |
641 | rtas_st(rets, 0, ret); |
642 | return; | |
643 | ||
644 | param_error_exit: | |
645 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
646 | } | |
647 | ||
648 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
ce2918cb | 649 | SpaprMachineState *spapr, |
ee954280 GS |
650 | uint32_t token, uint32_t nargs, |
651 | target_ulong args, uint32_t nret, | |
652 | target_ulong rets) | |
653 | { | |
ce2918cb | 654 | SpaprPhbState *sphb; |
ee954280 GS |
655 | uint64_t buid; |
656 | int ret; | |
657 | ||
658 | if ((nargs != 3) || (nret != 1)) { | |
659 | goto param_error_exit; | |
660 | } | |
661 | ||
a14aa92b | 662 | buid = rtas_ldq(args, 1); |
46c5874e | 663 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
664 | if (!sphb) { |
665 | goto param_error_exit; | |
666 | } | |
667 | ||
fbb4e983 | 668 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
669 | goto param_error_exit; |
670 | } | |
671 | ||
fbb4e983 | 672 | ret = spapr_phb_vfio_eeh_configure(sphb); |
ee954280 GS |
673 | rtas_st(rets, 0, ret); |
674 | return; | |
675 | ||
676 | param_error_exit: | |
677 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
678 | } | |
679 | ||
680 | /* To support it later */ | |
681 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
ce2918cb | 682 | SpaprMachineState *spapr, |
ee954280 GS |
683 | uint32_t token, uint32_t nargs, |
684 | target_ulong args, uint32_t nret, | |
685 | target_ulong rets) | |
686 | { | |
ce2918cb | 687 | SpaprPhbState *sphb; |
ee954280 GS |
688 | int option; |
689 | uint64_t buid; | |
690 | ||
691 | if ((nargs != 8) || (nret != 1)) { | |
692 | goto param_error_exit; | |
693 | } | |
694 | ||
a14aa92b | 695 | buid = rtas_ldq(args, 1); |
46c5874e | 696 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
697 | if (!sphb) { |
698 | goto param_error_exit; | |
699 | } | |
700 | ||
fbb4e983 | 701 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
702 | goto param_error_exit; |
703 | } | |
704 | ||
705 | option = rtas_ld(args, 7); | |
706 | switch (option) { | |
707 | case RTAS_SLOT_TEMP_ERR_LOG: | |
708 | case RTAS_SLOT_PERM_ERR_LOG: | |
709 | break; | |
710 | default: | |
711 | goto param_error_exit; | |
712 | } | |
713 | ||
714 | /* We don't have error log yet */ | |
715 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
716 | return; | |
717 | ||
718 | param_error_exit: | |
719 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
720 | } | |
721 | ||
3384f95c DG |
722 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) |
723 | { | |
724 | /* | |
e8ec4adf | 725 | * Here we use the number returned by pci_swizzle_map_irq_fn to find a |
3384f95c DG |
726 | * corresponding qemu_irq. |
727 | */ | |
ce2918cb | 728 | SpaprPhbState *phb = opaque; |
3384f95c | 729 | |
caae58cb | 730 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 731 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
732 | } |
733 | ||
5cc7a967 AK |
734 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
735 | { | |
ce2918cb | 736 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); |
5cc7a967 AK |
737 | PCIINTxRoute route; |
738 | ||
739 | route.mode = PCI_INTX_ENABLED; | |
740 | route.irq = sphb->lsi_table[pin].irq; | |
741 | ||
742 | return route; | |
743 | } | |
744 | ||
0ee2c058 AK |
745 | /* |
746 | * MSI/MSIX memory region implementation. | |
747 | * The handler handles both MSI and MSIX. | |
18f2330e | 748 | * The vector number is encoded in least bits in data. |
0ee2c058 | 749 | */ |
a8170e5e | 750 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
751 | uint64_t data, unsigned size) |
752 | { | |
ce2918cb | 753 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
f1c2dc7c | 754 | uint32_t irq = data; |
0ee2c058 AK |
755 | |
756 | trace_spapr_pci_msi_write(addr, data, irq); | |
757 | ||
77183755 | 758 | qemu_irq_pulse(spapr_qirq(spapr, irq)); |
0ee2c058 AK |
759 | } |
760 | ||
761 | static const MemoryRegionOps spapr_msi_ops = { | |
762 | /* There is no .read as the read result is undefined by PCI spec */ | |
763 | .read = NULL, | |
764 | .write = spapr_msi_write, | |
765 | .endianness = DEVICE_LITTLE_ENDIAN | |
766 | }; | |
767 | ||
298a9710 DG |
768 | /* |
769 | * PHB PCI device | |
770 | */ | |
e00387d5 | 771 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 | 772 | { |
ce2918cb | 773 | SpaprPhbState *phb = opaque; |
edded454 | 774 | |
e00387d5 | 775 | return &phb->iommu_as; |
edded454 DG |
776 | } |
777 | ||
ce2918cb | 778 | static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) |
16b0ea1d ND |
779 | { |
780 | char *path = NULL, *buf = NULL, *host = NULL; | |
781 | ||
782 | /* Get the PCI VFIO host id */ | |
783 | host = object_property_get_str(OBJECT(pdev), "host", NULL); | |
784 | if (!host) { | |
785 | goto err_out; | |
786 | } | |
787 | ||
788 | /* Construct the path of the file that will give us the DT location */ | |
789 | path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); | |
790 | g_free(host); | |
8f687605 | 791 | if (!g_file_get_contents(path, &buf, NULL, NULL)) { |
16b0ea1d ND |
792 | goto err_out; |
793 | } | |
794 | g_free(path); | |
795 | ||
796 | /* Construct and read from host device tree the loc-code */ | |
797 | path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); | |
798 | g_free(buf); | |
8f687605 | 799 | if (!g_file_get_contents(path, &buf, NULL, NULL)) { |
16b0ea1d ND |
800 | goto err_out; |
801 | } | |
802 | return buf; | |
803 | ||
804 | err_out: | |
805 | g_free(path); | |
806 | return NULL; | |
807 | } | |
808 | ||
ce2918cb | 809 | static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) |
16b0ea1d ND |
810 | { |
811 | char *buf; | |
812 | const char *devtype = "qemu"; | |
813 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
814 | ||
815 | if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
816 | buf = spapr_phb_vfio_get_loc_code(sphb, pdev); | |
817 | if (buf) { | |
818 | return buf; | |
819 | } | |
820 | devtype = "vfio"; | |
821 | } | |
822 | /* | |
823 | * For emulated devices and VFIO-failure case, make up | |
824 | * the loc-code. | |
825 | */ | |
826 | buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", | |
827 | devtype, pdev->name, sphb->index, busnr, | |
828 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
829 | return buf; | |
830 | } | |
831 | ||
7454c7af MR |
832 | /* Macros to operate with address in OF binding to PCI */ |
833 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
834 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
835 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
836 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
837 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
838 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
839 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
840 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
841 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
842 | ||
843 | /* for 'reg'/'assigned-addresses' OF properties */ | |
844 | #define RESOURCE_CELLS_SIZE 2 | |
845 | #define RESOURCE_CELLS_ADDRESS 3 | |
846 | ||
847 | typedef struct ResourceFields { | |
848 | uint32_t phys_hi; | |
849 | uint32_t phys_mid; | |
850 | uint32_t phys_lo; | |
851 | uint32_t size_hi; | |
852 | uint32_t size_lo; | |
853 | } QEMU_PACKED ResourceFields; | |
854 | ||
855 | typedef struct ResourceProps { | |
856 | ResourceFields reg[8]; | |
857 | ResourceFields assigned[7]; | |
858 | uint32_t reg_len; | |
859 | uint32_t assigned_len; | |
860 | } ResourceProps; | |
861 | ||
862 | /* fill in the 'reg'/'assigned-resources' OF properties for | |
863 | * a PCI device. 'reg' describes resource requirements for a | |
864 | * device's IO/MEM regions, 'assigned-addresses' describes the | |
865 | * actual resource assignments. | |
866 | * | |
867 | * the properties are arrays of ('phys-addr', 'size') pairs describing | |
868 | * the addressable regions of the PCI device, where 'phys-addr' is a | |
869 | * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to | |
870 | * (phys.hi, phys.mid, phys.lo), and 'size' is a | |
871 | * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). | |
872 | * | |
873 | * phys.hi = 0xYYXXXXZZ, where: | |
874 | * 0xYY = npt000ss | |
875 | * ||| | | |
72187935 ND |
876 | * ||| +-- space code |
877 | * ||| | | |
878 | * ||| + 00 if configuration space | |
879 | * ||| + 01 if IO region, | |
880 | * ||| + 10 if 32-bit MEM region | |
881 | * ||| + 11 if 64-bit MEM region | |
882 | * ||| | |
7454c7af MR |
883 | * ||+------ for non-relocatable IO: 1 if aliased |
884 | * || for relocatable IO: 1 if below 64KB | |
885 | * || for MEM: 1 if below 1MB | |
886 | * |+------- 1 if region is prefetchable | |
887 | * +-------- 1 if region is non-relocatable | |
888 | * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function | |
889 | * bits respectively | |
890 | * 0xZZ = rrrrrrrr, the register number of the BAR corresponding | |
891 | * to the region | |
892 | * | |
893 | * phys.mid and phys.lo correspond respectively to the hi/lo portions | |
894 | * of the actual address of the region. | |
895 | * | |
896 | * how the phys-addr/size values are used differ slightly between | |
897 | * 'reg' and 'assigned-addresses' properties. namely, 'reg' has | |
898 | * an additional description for the config space region of the | |
899 | * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 | |
900 | * to describe the region as relocatable, with an address-mapping | |
901 | * that corresponds directly to the PHB's address space for the | |
902 | * resource. 'assigned-addresses' always has n=1 set with an absolute | |
903 | * address assigned for the resource. in general, 'assigned-addresses' | |
904 | * won't be populated, since addresses for PCI devices are generally | |
905 | * unmapped initially and left to the guest to assign. | |
906 | * | |
907 | * note also that addresses defined in these properties are, at least | |
908 | * for PAPR guests, relative to the PHBs IO/MEM windows, and | |
909 | * correspond directly to the addresses in the BARs. | |
910 | * | |
911 | * in accordance with PCI Bus Binding to Open Firmware, | |
912 | * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, | |
913 | * Appendix C. | |
914 | */ | |
915 | static void populate_resource_props(PCIDevice *d, ResourceProps *rp) | |
916 | { | |
917 | int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); | |
918 | uint32_t dev_id = (b_bbbbbbbb(bus_num) | | |
919 | b_ddddd(PCI_SLOT(d->devfn)) | | |
920 | b_fff(PCI_FUNC(d->devfn))); | |
921 | ResourceFields *reg, *assigned; | |
922 | int i, reg_idx = 0, assigned_idx = 0; | |
923 | ||
924 | /* config space region */ | |
925 | reg = &rp->reg[reg_idx++]; | |
926 | reg->phys_hi = cpu_to_be32(dev_id); | |
927 | reg->phys_mid = 0; | |
928 | reg->phys_lo = 0; | |
929 | reg->size_hi = 0; | |
930 | reg->size_lo = 0; | |
931 | ||
932 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
933 | if (!d->io_regions[i].size) { | |
934 | continue; | |
935 | } | |
936 | ||
937 | reg = &rp->reg[reg_idx++]; | |
938 | ||
939 | reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); | |
940 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
941 | reg->phys_hi |= cpu_to_be32(b_ss(1)); | |
72187935 ND |
942 | } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
943 | reg->phys_hi |= cpu_to_be32(b_ss(3)); | |
7454c7af MR |
944 | } else { |
945 | reg->phys_hi |= cpu_to_be32(b_ss(2)); | |
946 | } | |
947 | reg->phys_mid = 0; | |
948 | reg->phys_lo = 0; | |
949 | reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); | |
950 | reg->size_lo = cpu_to_be32(d->io_regions[i].size); | |
951 | ||
952 | if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { | |
953 | continue; | |
954 | } | |
955 | ||
956 | assigned = &rp->assigned[assigned_idx++]; | |
382b6f22 | 957 | assigned->phys_hi = cpu_to_be32(be32_to_cpu(reg->phys_hi) | b_n(1)); |
7454c7af MR |
958 | assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); |
959 | assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); | |
960 | assigned->size_hi = reg->size_hi; | |
961 | assigned->size_lo = reg->size_lo; | |
962 | } | |
963 | ||
964 | rp->reg_len = reg_idx * sizeof(ResourceFields); | |
965 | rp->assigned_len = assigned_idx * sizeof(ResourceFields); | |
966 | } | |
967 | ||
2530a1a5 LV |
968 | typedef struct PCIClass PCIClass; |
969 | typedef struct PCISubClass PCISubClass; | |
970 | typedef struct PCIIFace PCIIFace; | |
971 | ||
972 | struct PCIIFace { | |
973 | int iface; | |
974 | const char *name; | |
975 | }; | |
976 | ||
977 | struct PCISubClass { | |
978 | int subclass; | |
979 | const char *name; | |
980 | const PCIIFace *iface; | |
981 | }; | |
982 | ||
983 | struct PCIClass { | |
984 | const char *name; | |
985 | const PCISubClass *subc; | |
986 | }; | |
987 | ||
988 | static const PCISubClass undef_subclass[] = { | |
989 | { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, | |
990 | { 0xFF, NULL, NULL }, | |
991 | }; | |
992 | ||
993 | static const PCISubClass mass_subclass[] = { | |
994 | { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, | |
995 | { PCI_CLASS_STORAGE_IDE, "ide", NULL }, | |
996 | { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, | |
997 | { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, | |
998 | { PCI_CLASS_STORAGE_RAID, "raid", NULL }, | |
999 | { PCI_CLASS_STORAGE_ATA, "ata", NULL }, | |
1000 | { PCI_CLASS_STORAGE_SATA, "sata", NULL }, | |
1001 | { PCI_CLASS_STORAGE_SAS, "sas", NULL }, | |
1002 | { 0xFF, NULL, NULL }, | |
1003 | }; | |
1004 | ||
1005 | static const PCISubClass net_subclass[] = { | |
1006 | { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, | |
1007 | { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, | |
1008 | { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, | |
1009 | { PCI_CLASS_NETWORK_ATM, "atm", NULL }, | |
1010 | { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, | |
1011 | { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, | |
1012 | { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, | |
1013 | { 0xFF, NULL, NULL }, | |
1014 | }; | |
1015 | ||
1016 | static const PCISubClass displ_subclass[] = { | |
1017 | { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, | |
1018 | { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, | |
1019 | { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, | |
1020 | { 0xFF, NULL, NULL }, | |
1021 | }; | |
1022 | ||
1023 | static const PCISubClass media_subclass[] = { | |
1024 | { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, | |
1025 | { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, | |
1026 | { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, | |
1027 | { 0xFF, NULL, NULL }, | |
1028 | }; | |
1029 | ||
1030 | static const PCISubClass mem_subclass[] = { | |
1031 | { PCI_CLASS_MEMORY_RAM, "memory", NULL }, | |
1032 | { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, | |
1033 | { 0xFF, NULL, NULL }, | |
1034 | }; | |
1035 | ||
1036 | static const PCISubClass bridg_subclass[] = { | |
1037 | { PCI_CLASS_BRIDGE_HOST, "host", NULL }, | |
1038 | { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, | |
1039 | { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, | |
1040 | { PCI_CLASS_BRIDGE_MC, "mca", NULL }, | |
1041 | { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, | |
1042 | { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, | |
1043 | { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, | |
1044 | { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, | |
1045 | { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, | |
1046 | { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, | |
1047 | { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, | |
1048 | { 0xFF, NULL, NULL }, | |
1049 | }; | |
1050 | ||
1051 | static const PCISubClass comm_subclass[] = { | |
1052 | { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, | |
1053 | { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, | |
1054 | { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, | |
1055 | { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, | |
1056 | { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, | |
1057 | { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, | |
1058 | { 0xFF, NULL, NULL, }, | |
1059 | }; | |
1060 | ||
1061 | static const PCIIFace pic_iface[] = { | |
1062 | { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, | |
1063 | { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, | |
1064 | { 0xFF, NULL }, | |
1065 | }; | |
1066 | ||
1067 | static const PCISubClass sys_subclass[] = { | |
1068 | { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, | |
1069 | { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, | |
1070 | { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, | |
1071 | { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, | |
1072 | { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, | |
1073 | { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, | |
1074 | { 0xFF, NULL, NULL }, | |
1075 | }; | |
1076 | ||
1077 | static const PCISubClass inp_subclass[] = { | |
1078 | { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, | |
1079 | { PCI_CLASS_INPUT_PEN, "pen", NULL }, | |
1080 | { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, | |
1081 | { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, | |
1082 | { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, | |
1083 | { 0xFF, NULL, NULL }, | |
1084 | }; | |
1085 | ||
1086 | static const PCISubClass dock_subclass[] = { | |
1087 | { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, | |
1088 | { 0xFF, NULL, NULL }, | |
1089 | }; | |
1090 | ||
1091 | static const PCISubClass cpu_subclass[] = { | |
1092 | { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, | |
1093 | { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, | |
1094 | { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, | |
1095 | { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, | |
1096 | { 0xFF, NULL, NULL }, | |
1097 | }; | |
1098 | ||
1099 | static const PCIIFace usb_iface[] = { | |
1100 | { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, | |
1101 | { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, | |
1102 | { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, | |
1103 | { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, | |
1104 | { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, | |
1105 | { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, | |
1106 | { 0xFF, NULL }, | |
1107 | }; | |
1108 | ||
1109 | static const PCISubClass ser_subclass[] = { | |
1110 | { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, | |
1111 | { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, | |
1112 | { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, | |
1113 | { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, | |
1114 | { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, | |
1115 | { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, | |
1116 | { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, | |
1117 | { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, | |
1118 | { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, | |
1119 | { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, | |
1120 | { 0xFF, NULL, NULL }, | |
1121 | }; | |
1122 | ||
1123 | static const PCISubClass wrl_subclass[] = { | |
1124 | { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, | |
1125 | { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, | |
1126 | { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, | |
1127 | { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, | |
1128 | { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, | |
1129 | { 0xFF, NULL, NULL }, | |
1130 | }; | |
1131 | ||
1132 | static const PCISubClass sat_subclass[] = { | |
1133 | { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, | |
1134 | { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, | |
1135 | { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, | |
1136 | { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, | |
1137 | { 0xFF, NULL, NULL }, | |
1138 | }; | |
1139 | ||
1140 | static const PCISubClass crypt_subclass[] = { | |
1141 | { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, | |
1142 | { PCI_CLASS_CRYPT_ENTERTAINMENT, | |
1143 | "entertainment-encryption", NULL }, | |
1144 | { 0xFF, NULL, NULL }, | |
1145 | }; | |
1146 | ||
1147 | static const PCISubClass spc_subclass[] = { | |
1148 | { PCI_CLASS_SP_DPIO, "dpio", NULL }, | |
1149 | { PCI_CLASS_SP_PERF, "counter", NULL }, | |
1150 | { PCI_CLASS_SP_SYNCH, "measurement", NULL }, | |
1151 | { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, | |
1152 | { 0xFF, NULL, NULL }, | |
1153 | }; | |
1154 | ||
1155 | static const PCIClass pci_classes[] = { | |
1156 | { "legacy-device", undef_subclass }, | |
1157 | { "mass-storage", mass_subclass }, | |
1158 | { "network", net_subclass }, | |
1159 | { "display", displ_subclass, }, | |
1160 | { "multimedia-device", media_subclass }, | |
1161 | { "memory-controller", mem_subclass }, | |
1162 | { "unknown-bridge", bridg_subclass }, | |
1163 | { "communication-controller", comm_subclass}, | |
1164 | { "system-peripheral", sys_subclass }, | |
1165 | { "input-controller", inp_subclass }, | |
1166 | { "docking-station", dock_subclass }, | |
1167 | { "cpu", cpu_subclass }, | |
1168 | { "serial-bus", ser_subclass }, | |
1169 | { "wireless-controller", wrl_subclass }, | |
1170 | { "intelligent-io", NULL }, | |
1171 | { "satellite-device", sat_subclass }, | |
1172 | { "encryption", crypt_subclass }, | |
1173 | { "data-processing-controller", spc_subclass }, | |
1174 | }; | |
1175 | ||
4782a8bb DG |
1176 | static const char *dt_name_from_class(uint8_t class, uint8_t subclass, |
1177 | uint8_t iface) | |
2530a1a5 LV |
1178 | { |
1179 | const PCIClass *pclass; | |
1180 | const PCISubClass *psubclass; | |
1181 | const PCIIFace *piface; | |
1182 | const char *name; | |
1183 | ||
1184 | if (class >= ARRAY_SIZE(pci_classes)) { | |
1185 | return "pci"; | |
1186 | } | |
1187 | ||
1188 | pclass = pci_classes + class; | |
1189 | name = pclass->name; | |
1190 | ||
1191 | if (pclass->subc == NULL) { | |
1192 | return name; | |
1193 | } | |
1194 | ||
1195 | psubclass = pclass->subc; | |
1196 | while ((psubclass->subclass & 0xff) != 0xff) { | |
1197 | if ((psubclass->subclass & 0xff) == subclass) { | |
1198 | name = psubclass->name; | |
1199 | break; | |
1200 | } | |
1201 | psubclass++; | |
1202 | } | |
1203 | ||
1204 | piface = psubclass->iface; | |
1205 | if (piface == NULL) { | |
1206 | return name; | |
1207 | } | |
1208 | while ((piface->iface & 0xff) != 0xff) { | |
1209 | if ((piface->iface & 0xff) == iface) { | |
1210 | name = piface->name; | |
1211 | break; | |
1212 | } | |
1213 | piface++; | |
1214 | } | |
1215 | ||
1216 | return name; | |
1217 | } | |
1218 | ||
ce2918cb | 1219 | static uint32_t spapr_phb_get_pci_drc_index(SpaprPhbState *phb, |
e634b89c ND |
1220 | PCIDevice *pdev); |
1221 | ||
9ba25536 | 1222 | static void spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, |
ce2918cb | 1223 | SpaprPhbState *sphb) |
7454c7af MR |
1224 | { |
1225 | ResourceProps rp; | |
1226 | bool is_bridge = false; | |
9ba25536 | 1227 | int pci_status; |
16b0ea1d | 1228 | char *buf = NULL; |
e634b89c | 1229 | uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); |
2530a1a5 | 1230 | uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); |
a8ad731a | 1231 | uint32_t max_msi, max_msix; |
7454c7af MR |
1232 | |
1233 | if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == | |
1234 | PCI_HEADER_TYPE_BRIDGE) { | |
1235 | is_bridge = true; | |
1236 | } | |
1237 | ||
1238 | /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ | |
1239 | _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", | |
1240 | pci_default_read_config(dev, PCI_VENDOR_ID, 2))); | |
1241 | _FDT(fdt_setprop_cell(fdt, offset, "device-id", | |
1242 | pci_default_read_config(dev, PCI_DEVICE_ID, 2))); | |
1243 | _FDT(fdt_setprop_cell(fdt, offset, "revision-id", | |
1244 | pci_default_read_config(dev, PCI_REVISION_ID, 1))); | |
2530a1a5 | 1245 | _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); |
7454c7af MR |
1246 | if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { |
1247 | _FDT(fdt_setprop_cell(fdt, offset, "interrupts", | |
1248 | pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); | |
1249 | } | |
1250 | ||
1251 | if (!is_bridge) { | |
1252 | _FDT(fdt_setprop_cell(fdt, offset, "min-grant", | |
1253 | pci_default_read_config(dev, PCI_MIN_GNT, 1))); | |
1254 | _FDT(fdt_setprop_cell(fdt, offset, "max-latency", | |
1255 | pci_default_read_config(dev, PCI_MAX_LAT, 1))); | |
1256 | } | |
1257 | ||
1258 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { | |
1259 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", | |
1260 | pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); | |
1261 | } | |
1262 | ||
1263 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { | |
1264 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", | |
1265 | pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); | |
1266 | } | |
1267 | ||
1268 | _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", | |
1269 | pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); | |
1270 | ||
1271 | /* the following fdt cells are masked off the pci status register */ | |
1272 | pci_status = pci_default_read_config(dev, PCI_STATUS, 2); | |
1273 | _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", | |
1274 | PCI_STATUS_DEVSEL_MASK & pci_status)); | |
1275 | ||
1276 | if (pci_status & PCI_STATUS_FAST_BACK) { | |
1277 | _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); | |
1278 | } | |
1279 | if (pci_status & PCI_STATUS_66MHZ) { | |
1280 | _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); | |
1281 | } | |
1282 | if (pci_status & PCI_STATUS_UDF) { | |
1283 | _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); | |
1284 | } | |
1285 | ||
d049bde6 | 1286 | buf = spapr_phb_get_loc_code(sphb, dev); |
9ba25536 | 1287 | _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", buf)); |
16b0ea1d | 1288 | g_free(buf); |
16b0ea1d | 1289 | |
e634b89c ND |
1290 | if (drc_index) { |
1291 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); | |
1292 | } | |
7454c7af MR |
1293 | |
1294 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", | |
1295 | RESOURCE_CELLS_ADDRESS)); | |
1296 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", | |
1297 | RESOURCE_CELLS_SIZE)); | |
a8ad731a | 1298 | |
9cbe305b GK |
1299 | if (msi_present(dev)) { |
1300 | max_msi = msi_nr_vectors_allocated(dev); | |
1301 | if (max_msi) { | |
1302 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); | |
1303 | } | |
a8ad731a | 1304 | } |
9cbe305b GK |
1305 | if (msix_present(dev)) { |
1306 | max_msix = dev->msix_entries_nr; | |
1307 | if (max_msix) { | |
1308 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); | |
1309 | } | |
a8ad731a | 1310 | } |
7454c7af MR |
1311 | |
1312 | populate_resource_props(dev, &rp); | |
1313 | _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); | |
1314 | _FDT(fdt_setprop(fdt, offset, "assigned-addresses", | |
1315 | (uint8_t *)rp.assigned, rp.assigned_len)); | |
1316 | ||
82516263 | 1317 | if (sphb->pcie_ecs && pci_is_express(dev)) { |
bb998645 DG |
1318 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); |
1319 | } | |
ec132efa AK |
1320 | |
1321 | spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); | |
7454c7af MR |
1322 | } |
1323 | ||
1324 | /* create OF node for pci device and required OF DT properties */ | |
ce2918cb | 1325 | static int spapr_create_pci_child_dt(SpaprPhbState *phb, PCIDevice *dev, |
1d2d9742 | 1326 | void *fdt, int node_offset) |
7454c7af | 1327 | { |
9ba25536 | 1328 | int offset; |
4782a8bb | 1329 | const gchar *basename; |
549ce59e | 1330 | gchar *nodename; |
4782a8bb DG |
1331 | int slot = PCI_SLOT(dev->devfn); |
1332 | int func = PCI_FUNC(dev->devfn); | |
1333 | uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); | |
1334 | ||
1335 | basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, | |
1336 | ccode & 0xff); | |
1337 | ||
1338 | if (func != 0) { | |
1339 | nodename = g_strdup_printf("%s@%x,%x", basename, slot, func); | |
1340 | } else { | |
1341 | nodename = g_strdup_printf("%s@%x", basename, slot); | |
1342 | } | |
7454c7af | 1343 | |
9ba25536 | 1344 | _FDT(offset = fdt_add_subnode(fdt, node_offset, nodename)); |
4782a8bb | 1345 | |
549ce59e GK |
1346 | g_free(nodename); |
1347 | ||
9ba25536 | 1348 | spapr_populate_pci_child_dt(dev, fdt, offset, phb); |
e634b89c | 1349 | |
1d2d9742 | 1350 | return offset; |
7454c7af MR |
1351 | } |
1352 | ||
31834723 DHB |
1353 | /* Callback to be called during DRC release. */ |
1354 | void spapr_phb_remove_pci_device_cb(DeviceState *dev) | |
7454c7af | 1355 | { |
27c1da51 DH |
1356 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
1357 | ||
1358 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
07578b0a | 1359 | object_unparent(OBJECT(dev)); |
7454c7af MR |
1360 | } |
1361 | ||
ce2918cb | 1362 | static SpaprDrc *spapr_phb_get_pci_func_drc(SpaprPhbState *phb, |
788d2599 MR |
1363 | uint32_t busnr, |
1364 | int32_t devfn) | |
7454c7af | 1365 | { |
fbf55397 DG |
1366 | return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, |
1367 | (phb->index << 16) | (busnr << 8) | devfn); | |
788d2599 MR |
1368 | } |
1369 | ||
ce2918cb | 1370 | static SpaprDrc *spapr_phb_get_pci_drc(SpaprPhbState *phb, |
788d2599 MR |
1371 | PCIDevice *pdev) |
1372 | { | |
1373 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
1374 | return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn); | |
7454c7af MR |
1375 | } |
1376 | ||
ce2918cb | 1377 | static uint32_t spapr_phb_get_pci_drc_index(SpaprPhbState *phb, |
1d2d9742 ND |
1378 | PCIDevice *pdev) |
1379 | { | |
ce2918cb | 1380 | SpaprDrc *drc = spapr_phb_get_pci_drc(phb, pdev); |
1d2d9742 ND |
1381 | |
1382 | if (!drc) { | |
1383 | return 0; | |
1384 | } | |
1385 | ||
0b55aa91 | 1386 | return spapr_drc_index(drc); |
1d2d9742 ND |
1387 | } |
1388 | ||
ce2918cb | 1389 | int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
46fd0299 GK |
1390 | void *fdt, int *fdt_start_offset, Error **errp) |
1391 | { | |
1392 | HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); | |
ce2918cb | 1393 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); |
46fd0299 GK |
1394 | PCIDevice *pdev = PCI_DEVICE(drc->dev); |
1395 | ||
1396 | *fdt_start_offset = spapr_create_pci_child_dt(sphb, pdev, fdt, 0); | |
1397 | return 0; | |
1398 | } | |
1399 | ||
3340e5c4 DG |
1400 | static void spapr_pci_plug(HotplugHandler *plug_handler, |
1401 | DeviceState *plugged_dev, Error **errp) | |
7454c7af | 1402 | { |
ce2918cb | 1403 | SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); |
7454c7af | 1404 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); |
ce2918cb | 1405 | SpaprDrc *drc = spapr_phb_get_pci_drc(phb, pdev); |
7454c7af | 1406 | Error *local_err = NULL; |
788d2599 MR |
1407 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); |
1408 | uint32_t slotnr = PCI_SLOT(pdev->devfn); | |
7454c7af MR |
1409 | |
1410 | /* if DR is disabled we don't need to do anything in the case of | |
1411 | * hotplug or coldplug callbacks | |
1412 | */ | |
1413 | if (!phb->dr_enabled) { | |
1414 | /* if this is a hotplug operation initiated by the user | |
1415 | * we need to let them know it's not enabled | |
1416 | */ | |
1417 | if (plugged_dev->hotplugged) { | |
6304fd27 | 1418 | error_setg(&local_err, QERR_BUS_NO_HOTPLUG, |
c6bd8c70 | 1419 | object_get_typename(OBJECT(phb))); |
7454c7af | 1420 | } |
6304fd27 | 1421 | goto out; |
7454c7af MR |
1422 | } |
1423 | ||
1424 | g_assert(drc); | |
1425 | ||
788d2599 MR |
1426 | /* Following the QEMU convention used for PCIe multifunction |
1427 | * hotplug, we do not allow functions to be hotplugged to a | |
1428 | * slot that already has function 0 present | |
1429 | */ | |
1430 | if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && | |
1431 | PCI_FUNC(pdev->devfn) != 0) { | |
6304fd27 | 1432 | error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s," |
788d2599 MR |
1433 | " additional functions can no longer be exposed to guest.", |
1434 | slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); | |
6304fd27 DG |
1435 | goto out; |
1436 | } | |
1437 | ||
09d876ce | 1438 | spapr_drc_attach(drc, DEVICE(pdev), &local_err); |
7454c7af | 1439 | if (local_err) { |
6304fd27 | 1440 | goto out; |
7454c7af | 1441 | } |
788d2599 MR |
1442 | |
1443 | /* If this is function 0, signal hotplug for all the device functions. | |
1444 | * Otherwise defer sending the hotplug event. | |
1445 | */ | |
94fd9cba LV |
1446 | if (!spapr_drc_hotplugged(plugged_dev)) { |
1447 | spapr_drc_reset(drc); | |
1448 | } else if (PCI_FUNC(pdev->devfn) == 0) { | |
788d2599 MR |
1449 | int i; |
1450 | ||
1451 | for (i = 0; i < 8; i++) { | |
ce2918cb DG |
1452 | SpaprDrc *func_drc; |
1453 | SpaprDrcClass *func_drck; | |
1454 | SpaprDREntitySense state; | |
788d2599 MR |
1455 | |
1456 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1457 | PCI_DEVFN(slotnr, i)); | |
1458 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
f224d35b | 1459 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 MR |
1460 | |
1461 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { | |
1462 | spapr_hotplug_req_add_by_index(func_drc); | |
1463 | } | |
1464 | } | |
c5bc152b | 1465 | } |
6304fd27 DG |
1466 | |
1467 | out: | |
e366d181 | 1468 | error_propagate(errp, local_err); |
7454c7af MR |
1469 | } |
1470 | ||
27c1da51 DH |
1471 | static void spapr_pci_unplug(HotplugHandler *plug_handler, |
1472 | DeviceState *plugged_dev, Error **errp) | |
1473 | { | |
1474 | /* some version guests do not wait for completion of a device | |
1475 | * cleanup (generally done asynchronously by the kernel) before | |
1476 | * signaling to QEMU that the device is safe, but instead sleep | |
1477 | * for some 'safe' period of time. unfortunately on a busy host | |
1478 | * this sleep isn't guaranteed to be long enough, resulting in | |
1479 | * bad things like IRQ lines being left asserted during final | |
1480 | * device removal. to deal with this we call reset just prior | |
1481 | * to finalizing the device, which will put the device back into | |
1482 | * an 'idle' state, as the device cleanup code expects. | |
1483 | */ | |
1484 | pci_device_reset(PCI_DEVICE(plugged_dev)); | |
07578b0a | 1485 | object_property_set_bool(OBJECT(plugged_dev), false, "realized", NULL); |
27c1da51 DH |
1486 | } |
1487 | ||
3340e5c4 DG |
1488 | static void spapr_pci_unplug_request(HotplugHandler *plug_handler, |
1489 | DeviceState *plugged_dev, Error **errp) | |
7454c7af | 1490 | { |
ce2918cb | 1491 | SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); |
7454c7af | 1492 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); |
ce2918cb | 1493 | SpaprDrc *drc = spapr_phb_get_pci_drc(phb, pdev); |
7454c7af MR |
1494 | |
1495 | if (!phb->dr_enabled) { | |
c6bd8c70 MA |
1496 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1497 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1498 | return; |
1499 | } | |
1500 | ||
1501 | g_assert(drc); | |
3340e5c4 | 1502 | g_assert(drc->dev == plugged_dev); |
7454c7af | 1503 | |
f1c52354 | 1504 | if (!spapr_drc_unplug_requested(drc)) { |
788d2599 MR |
1505 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); |
1506 | uint32_t slotnr = PCI_SLOT(pdev->devfn); | |
ce2918cb DG |
1507 | SpaprDrc *func_drc; |
1508 | SpaprDrcClass *func_drck; | |
1509 | SpaprDREntitySense state; | |
788d2599 MR |
1510 | int i; |
1511 | ||
1512 | /* ensure any other present functions are pending unplug */ | |
1513 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1514 | for (i = 1; i < 8; i++) { | |
1515 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1516 | PCI_DEVFN(slotnr, i)); | |
1517 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
f224d35b | 1518 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 | 1519 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT |
f1c52354 | 1520 | && !spapr_drc_unplug_requested(func_drc)) { |
788d2599 MR |
1521 | error_setg(errp, |
1522 | "PCI: slot %d, function %d still present. " | |
1523 | "Must unplug all non-0 functions first.", | |
1524 | slotnr, i); | |
1525 | return; | |
1526 | } | |
1527 | } | |
1528 | } | |
1529 | ||
a8dc47fd | 1530 | spapr_drc_detach(drc); |
788d2599 MR |
1531 | |
1532 | /* if this isn't func 0, defer unplug event. otherwise signal removal | |
1533 | * for all present functions | |
1534 | */ | |
1535 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1536 | for (i = 7; i >= 0; i--) { | |
1537 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1538 | PCI_DEVFN(slotnr, i)); | |
1539 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
f224d35b | 1540 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 MR |
1541 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { |
1542 | spapr_hotplug_req_remove_by_index(func_drc); | |
1543 | } | |
1544 | } | |
1545 | } | |
7454c7af MR |
1546 | } |
1547 | } | |
1548 | ||
ef28b98d GK |
1549 | static void spapr_phb_finalizefn(Object *obj) |
1550 | { | |
ce2918cb | 1551 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); |
ef28b98d GK |
1552 | |
1553 | g_free(sphb->dtbusname); | |
1554 | sphb->dtbusname = NULL; | |
1555 | } | |
1556 | ||
1557 | static void spapr_phb_unrealize(DeviceState *dev, Error **errp) | |
1558 | { | |
ce2918cb | 1559 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
ef28b98d GK |
1560 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
1561 | PCIHostState *phb = PCI_HOST_BRIDGE(s); | |
ce2918cb DG |
1562 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); |
1563 | SpaprTceTable *tcet; | |
ef28b98d GK |
1564 | int i; |
1565 | const unsigned windows_supported = spapr_phb_windows_supported(sphb); | |
1566 | ||
ec132efa AK |
1567 | spapr_phb_nvgpu_free(sphb); |
1568 | ||
ef28b98d GK |
1569 | if (sphb->msi) { |
1570 | g_hash_table_unref(sphb->msi); | |
1571 | sphb->msi = NULL; | |
1572 | } | |
1573 | ||
1574 | /* | |
1575 | * Remove IO/MMIO subregions and aliases, rest should get cleaned | |
1576 | * via PHB's unrealize->object_finalize | |
1577 | */ | |
1578 | for (i = windows_supported - 1; i >= 0; i--) { | |
1579 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); | |
1580 | if (tcet) { | |
1581 | memory_region_del_subregion(&sphb->iommu_root, | |
1582 | spapr_tce_get_iommu(tcet)); | |
1583 | } | |
1584 | } | |
1585 | ||
1586 | if (sphb->dr_enabled) { | |
1587 | for (i = PCI_SLOT_MAX * 8 - 1; i >= 0; i--) { | |
ce2918cb | 1588 | SpaprDrc *drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, |
ef28b98d GK |
1589 | (sphb->index << 16) | i); |
1590 | ||
1591 | if (drc) { | |
1592 | object_unparent(OBJECT(drc)); | |
1593 | } | |
1594 | } | |
1595 | } | |
1596 | ||
1597 | for (i = PCI_NUM_PINS - 1; i >= 0; i--) { | |
1598 | if (sphb->lsi_table[i].irq) { | |
1599 | spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); | |
1600 | sphb->lsi_table[i].irq = 0; | |
1601 | } | |
1602 | } | |
1603 | ||
1604 | QLIST_REMOVE(sphb, list); | |
1605 | ||
1606 | memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); | |
1607 | ||
1608 | address_space_destroy(&sphb->iommu_as); | |
1609 | ||
1610 | qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort); | |
1611 | pci_unregister_root_bus(phb->bus); | |
1612 | ||
1613 | memory_region_del_subregion(get_system_memory(), &sphb->iowindow); | |
1614 | if (sphb->mem64_win_pciaddr != (hwaddr)-1) { | |
1615 | memory_region_del_subregion(get_system_memory(), &sphb->mem64window); | |
1616 | } | |
1617 | memory_region_del_subregion(get_system_memory(), &sphb->mem32window); | |
1618 | } | |
1619 | ||
c6ba42f6 | 1620 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 1621 | { |
f7d6bfcd GK |
1622 | /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user |
1623 | * tries to add a sPAPR PHB to a non-pseries machine. | |
1624 | */ | |
ce2918cb DG |
1625 | SpaprMachineState *spapr = |
1626 | (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), | |
f7d6bfcd | 1627 | TYPE_SPAPR_MACHINE); |
ce2918cb | 1628 | SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; |
c6ba42f6 | 1629 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
ce2918cb | 1630 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 1631 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
298a9710 DG |
1632 | char *namebuf; |
1633 | int i; | |
3384f95c | 1634 | PCIBus *bus; |
8c46f7ec | 1635 | uint64_t msi_window_size = 4096; |
ce2918cb | 1636 | SpaprTceTable *tcet; |
ef28b98d | 1637 | const unsigned windows_supported = spapr_phb_windows_supported(sphb); |
3384f95c | 1638 | |
f7d6bfcd GK |
1639 | if (!spapr) { |
1640 | error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); | |
1641 | return; | |
1642 | } | |
1643 | ||
bb2bdd81 | 1644 | assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ |
caae58cb | 1645 | |
daa23699 | 1646 | if (sphb->mem64_win_size != 0) { |
daa23699 DG |
1647 | if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { |
1648 | error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx | |
1649 | " (max 2 GiB)", sphb->mem_win_size); | |
1650 | return; | |
1651 | } | |
1652 | ||
30b3bc5a GK |
1653 | /* 64-bit window defaults to identity mapping */ |
1654 | sphb->mem64_win_pciaddr = sphb->mem64_win_addr; | |
daa23699 DG |
1655 | } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { |
1656 | /* | |
1657 | * For compatibility with old configuration, if no 64-bit MMIO | |
1658 | * window is specified, but the ordinary (32-bit) memory | |
1659 | * window is specified as > 2GiB, we treat it as a 2GiB 32-bit | |
1660 | * window, with a 64-bit MMIO window following on immediately | |
1661 | * afterwards | |
1662 | */ | |
1663 | sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; | |
1664 | sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; | |
1665 | sphb->mem64_win_pciaddr = | |
1666 | SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; | |
1667 | sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; | |
1668 | } | |
1669 | ||
46c5874e | 1670 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
70282930 GK |
1671 | SpaprPhbState *s; |
1672 | ||
1673 | error_setg(errp, "PCI host bridges must have unique indexes"); | |
1674 | error_append_hint(errp, "The following indexes are already in use:"); | |
1675 | QLIST_FOREACH(s, &spapr->phbs, list) { | |
1676 | error_append_hint(errp, " %d", s->index); | |
1677 | } | |
1678 | error_append_hint(errp, "\nTry another value for the index property\n"); | |
c6ba42f6 | 1679 | return; |
caae58cb DG |
1680 | } |
1681 | ||
4bcfa56c MR |
1682 | if (sphb->numa_node != -1 && |
1683 | (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) { | |
1684 | error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); | |
1685 | return; | |
1686 | } | |
1687 | ||
8c9f64df | 1688 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 1689 | |
298a9710 | 1690 | /* Initialize memory regions */ |
1d36da76 | 1691 | namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); |
92b8e39c | 1692 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
1d36da76 | 1693 | g_free(namebuf); |
3384f95c | 1694 | |
1d36da76 | 1695 | namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); |
daa23699 | 1696 | memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), |
40c5dce9 | 1697 | namebuf, &sphb->memspace, |
8c9f64df | 1698 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
1d36da76 | 1699 | g_free(namebuf); |
8c9f64df | 1700 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, |
daa23699 DG |
1701 | &sphb->mem32window); |
1702 | ||
30b3bc5a | 1703 | if (sphb->mem64_win_size != 0) { |
96dbc9af GK |
1704 | namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); |
1705 | memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), | |
1706 | namebuf, &sphb->memspace, | |
1707 | sphb->mem64_win_pciaddr, sphb->mem64_win_size); | |
1708 | g_free(namebuf); | |
1709 | ||
30b3bc5a GK |
1710 | memory_region_add_subregion(get_system_memory(), |
1711 | sphb->mem64_win_addr, | |
1712 | &sphb->mem64window); | |
96dbc9af | 1713 | } |
3384f95c | 1714 | |
fabe9ee1 | 1715 | /* Initialize IO regions */ |
1d36da76 | 1716 | namebuf = g_strdup_printf("%s.io", sphb->dtbusname); |
40c5dce9 PB |
1717 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
1718 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
1d36da76 | 1719 | g_free(namebuf); |
3384f95c | 1720 | |
1d36da76 | 1721 | namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); |
66aab867 | 1722 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 1723 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
1d36da76 | 1724 | g_free(namebuf); |
8c9f64df | 1725 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 1726 | &sphb->iowindow); |
1b8601b0 | 1727 | |
4560116e | 1728 | bus = pci_register_root_bus(dev, NULL, |
e8ec4adf | 1729 | pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, |
1115ff6d | 1730 | &sphb->memspace, &sphb->iospace, |
5cf0d326 | 1731 | PCI_DEVFN(0, 0), PCI_NUM_PINS, |
2f57db8a DG |
1732 | TYPE_PCI_BUS); |
1733 | ||
1734 | /* | |
1735 | * Despite resembling a vanilla PCI bus in most ways, the PAPR | |
1736 | * para-virtualized PCI bus *does* permit PCI-E extended config | |
1737 | * space access | |
1738 | */ | |
1739 | if (sphb->pcie_ecs) { | |
1740 | bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; | |
1741 | } | |
8c9f64df | 1742 | phb->bus = bus; |
94d1cc5f | 1743 | qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); |
298a9710 | 1744 | |
cca7fad5 AK |
1745 | /* |
1746 | * Initialize PHB address space. | |
1747 | * By default there will be at least one subregion for default | |
1748 | * 32bit DMA window. | |
1749 | * Later the guest might want to create another DMA window | |
1750 | * which will become another memory subregion. | |
1751 | */ | |
1d36da76 | 1752 | namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); |
cca7fad5 AK |
1753 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), |
1754 | namebuf, UINT64_MAX); | |
1d36da76 | 1755 | g_free(namebuf); |
cca7fad5 AK |
1756 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, |
1757 | sphb->dtbusname); | |
1758 | ||
8c46f7ec GK |
1759 | /* |
1760 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
1761 | * we need to allocate some memory to catch those writes coming | |
1762 | * from msi_notify()/msix_notify(). | |
1763 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
1764 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
1765 | * be used. | |
1766 | * | |
1767 | * For KVM we want to ensure that this memory is a full page so that | |
1768 | * our memory slot is of page size granularity. | |
1769 | */ | |
1770 | #ifdef CONFIG_KVM | |
1771 | if (kvm_enabled()) { | |
1772 | msi_window_size = getpagesize(); | |
1773 | } | |
1774 | #endif | |
1775 | ||
dba95ebb | 1776 | memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, |
8c46f7ec GK |
1777 | "msi", msi_window_size); |
1778 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
1779 | &sphb->msiwindow); | |
1780 | ||
e00387d5 | 1781 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 1782 | |
5cc7a967 AK |
1783 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
1784 | ||
8c9f64df | 1785 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
1786 | |
1787 | /* Initialize the LSI table */ | |
7fb0bd34 | 1788 | for (i = 0; i < PCI_NUM_PINS; i++) { |
82cffa2e | 1789 | uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; |
a005b3ef | 1790 | Error *local_err = NULL; |
298a9710 | 1791 | |
2c88b098 | 1792 | if (smc->legacy_irq_allocation) { |
82cffa2e CLG |
1793 | irq = spapr_irq_findone(spapr, &local_err); |
1794 | if (local_err) { | |
4b576648 MA |
1795 | error_propagate_prepend(errp, local_err, |
1796 | "can't allocate LSIs: "); | |
ef28b98d GK |
1797 | /* |
1798 | * Older machines will never support PHB hotplug, ie, this is an | |
1799 | * init only path and QEMU will terminate. No need to rollback. | |
1800 | */ | |
82cffa2e CLG |
1801 | return; |
1802 | } | |
4fe75a8c CLG |
1803 | } |
1804 | ||
1805 | spapr_irq_claim(spapr, irq, true, &local_err); | |
a005b3ef | 1806 | if (local_err) { |
4b576648 | 1807 | error_propagate_prepend(errp, local_err, "can't allocate LSIs: "); |
ef28b98d | 1808 | goto unrealize; |
298a9710 DG |
1809 | } |
1810 | ||
8c9f64df | 1811 | sphb->lsi_table[i].irq = irq; |
298a9710 | 1812 | } |
da6ccee4 | 1813 | |
62083979 MR |
1814 | /* allocate connectors for child PCI devices */ |
1815 | if (sphb->dr_enabled) { | |
1816 | for (i = 0; i < PCI_SLOT_MAX * 8; i++) { | |
2d335818 | 1817 | spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI, |
62083979 MR |
1818 | (sphb->index << 16) | i); |
1819 | } | |
1820 | } | |
1821 | ||
ae4de14c AK |
1822 | /* DMA setup */ |
1823 | for (i = 0; i < windows_supported; ++i) { | |
1824 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); | |
1825 | if (!tcet) { | |
1826 | error_setg(errp, "Creating window#%d failed for %s", | |
1827 | i, sphb->dtbusname); | |
ef28b98d | 1828 | goto unrealize; |
ae4de14c | 1829 | } |
5c3d70e9 GK |
1830 | memory_region_add_subregion(&sphb->iommu_root, 0, |
1831 | spapr_tce_get_iommu(tcet)); | |
da6ccee4 | 1832 | } |
cca7fad5 | 1833 | |
a36304fd | 1834 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); |
ef28b98d GK |
1835 | return; |
1836 | ||
1837 | unrealize: | |
1838 | spapr_phb_unrealize(dev, NULL); | |
298a9710 DG |
1839 | } |
1840 | ||
e28c16f6 | 1841 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 1842 | { |
e28c16f6 AK |
1843 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
1844 | ||
1845 | if (dev) { | |
1846 | device_reset(dev); | |
1847 | } | |
eddeed26 | 1848 | |
e28c16f6 AK |
1849 | return 0; |
1850 | } | |
1851 | ||
ce2918cb | 1852 | void spapr_phb_dma_reset(SpaprPhbState *sphb) |
e28c16f6 | 1853 | { |
ae4de14c | 1854 | int i; |
ce2918cb | 1855 | SpaprTceTable *tcet; |
ae4de14c AK |
1856 | |
1857 | for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { | |
1858 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); | |
acf1b6dd | 1859 | |
ae4de14c AK |
1860 | if (tcet && tcet->nb_table) { |
1861 | spapr_tce_table_disable(tcet); | |
1862 | } | |
acf1b6dd AK |
1863 | } |
1864 | ||
1865 | /* Register default 32bit DMA window */ | |
ae4de14c | 1866 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); |
acf1b6dd AK |
1867 | spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, |
1868 | sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); | |
b3162f22 AK |
1869 | } |
1870 | ||
1871 | static void spapr_phb_reset(DeviceState *qdev) | |
1872 | { | |
ce2918cb | 1873 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); |
ec132efa | 1874 | Error *errp = NULL; |
b3162f22 AK |
1875 | |
1876 | spapr_phb_dma_reset(sphb); | |
ec132efa AK |
1877 | spapr_phb_nvgpu_free(sphb); |
1878 | spapr_phb_nvgpu_setup(sphb, &errp); | |
1879 | if (errp) { | |
1880 | error_report_err(errp); | |
1881 | } | |
acf1b6dd | 1882 | |
eddeed26 | 1883 | /* Reset the IOMMU state */ |
e28c16f6 | 1884 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
fbb4e983 DG |
1885 | |
1886 | if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { | |
1887 | spapr_phb_vfio_reset(qdev); | |
1888 | } | |
eddeed26 DG |
1889 | } |
1890 | ||
298a9710 | 1891 | static Property spapr_phb_properties[] = { |
ce2918cb DG |
1892 | DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), |
1893 | DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, | |
357d1e3b | 1894 | SPAPR_PCI_MEM32_WIN_SIZE), |
ce2918cb | 1895 | DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, |
357d1e3b | 1896 | SPAPR_PCI_MEM64_WIN_SIZE), |
ce2918cb | 1897 | DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, |
c7bcc85d | 1898 | SPAPR_PCI_IO_WIN_SIZE), |
ce2918cb | 1899 | DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, |
7619c7b0 | 1900 | true), |
f93caaac | 1901 | /* Default DMA window is 0..1GB */ |
ce2918cb DG |
1902 | DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), |
1903 | DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), | |
1904 | DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, | |
ae4de14c | 1905 | 0x800000000000000ULL), |
ce2918cb DG |
1906 | DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), |
1907 | DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, | |
ae4de14c | 1908 | (1ULL << 12) | (1ULL << 16)), |
ce2918cb DG |
1909 | DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), |
1910 | DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, | |
5c4537bd | 1911 | pre_2_8_migration, false), |
ce2918cb | 1912 | DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, |
82516263 | 1913 | pcie_ecs, true), |
ec132efa AK |
1914 | DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), |
1915 | DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), | |
298a9710 DG |
1916 | DEFINE_PROP_END_OF_LIST(), |
1917 | }; | |
1918 | ||
1112cf94 DG |
1919 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
1920 | .name = "spapr_pci/lsi", | |
1921 | .version_id = 1, | |
1922 | .minimum_version_id = 1, | |
3aff6c2f | 1923 | .fields = (VMStateField[]) { |
d2164ad3 | 1924 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL), |
1112cf94 DG |
1925 | |
1926 | VMSTATE_END_OF_LIST() | |
1927 | }, | |
1928 | }; | |
1929 | ||
1930 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 1931 | .name = "spapr_pci/msi", |
1112cf94 DG |
1932 | .version_id = 1, |
1933 | .minimum_version_id = 1, | |
9a321e92 AK |
1934 | .fields = (VMStateField []) { |
1935 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
1936 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
1937 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
1938 | VMSTATE_END_OF_LIST() |
1939 | }, | |
1940 | }; | |
1941 | ||
44b1ff31 | 1942 | static int spapr_pci_pre_save(void *opaque) |
9a321e92 | 1943 | { |
ce2918cb | 1944 | SpaprPhbState *sphb = opaque; |
708414f0 MA |
1945 | GHashTableIter iter; |
1946 | gpointer key, value; | |
1947 | int i; | |
9a321e92 | 1948 | |
5c4537bd DG |
1949 | if (sphb->pre_2_8_migration) { |
1950 | sphb->mig_liobn = sphb->dma_liobn[0]; | |
1951 | sphb->mig_mem_win_addr = sphb->mem_win_addr; | |
1952 | sphb->mig_mem_win_size = sphb->mem_win_size; | |
1953 | sphb->mig_io_win_addr = sphb->io_win_addr; | |
1954 | sphb->mig_io_win_size = sphb->io_win_size; | |
1955 | ||
1956 | if ((sphb->mem64_win_size != 0) | |
1957 | && (sphb->mem64_win_addr | |
1958 | == (sphb->mem_win_addr + sphb->mem_win_size))) { | |
1959 | sphb->mig_mem_win_size += sphb->mem64_win_size; | |
1960 | } | |
1961 | } | |
e806b4db LV |
1962 | |
1963 | g_free(sphb->msi_devs); | |
1964 | sphb->msi_devs = NULL; | |
1965 | sphb->msi_devs_num = g_hash_table_size(sphb->msi); | |
1966 | if (!sphb->msi_devs_num) { | |
44b1ff31 | 1967 | return 0; |
e806b4db | 1968 | } |
4fc4c6a5 | 1969 | sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num); |
e806b4db LV |
1970 | |
1971 | g_hash_table_iter_init(&iter, sphb->msi); | |
1972 | for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { | |
1973 | sphb->msi_devs[i].key = *(uint32_t *) key; | |
1974 | sphb->msi_devs[i].value = *(spapr_pci_msi *) value; | |
1975 | } | |
44b1ff31 DDAG |
1976 | |
1977 | return 0; | |
9a321e92 AK |
1978 | } |
1979 | ||
1980 | static int spapr_pci_post_load(void *opaque, int version_id) | |
1981 | { | |
ce2918cb | 1982 | SpaprPhbState *sphb = opaque; |
9a321e92 AK |
1983 | gpointer key, value; |
1984 | int i; | |
1985 | ||
1986 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
1987 | key = g_memdup(&sphb->msi_devs[i].key, | |
1988 | sizeof(sphb->msi_devs[i].key)); | |
1989 | value = g_memdup(&sphb->msi_devs[i].value, | |
1990 | sizeof(sphb->msi_devs[i].value)); | |
1991 | g_hash_table_insert(sphb->msi, key, value); | |
1992 | } | |
012aef07 MA |
1993 | g_free(sphb->msi_devs); |
1994 | sphb->msi_devs = NULL; | |
9a321e92 AK |
1995 | sphb->msi_devs_num = 0; |
1996 | ||
1997 | return 0; | |
1998 | } | |
1999 | ||
5c4537bd DG |
2000 | static bool pre_2_8_migration(void *opaque, int version_id) |
2001 | { | |
ce2918cb | 2002 | SpaprPhbState *sphb = opaque; |
5c4537bd DG |
2003 | |
2004 | return sphb->pre_2_8_migration; | |
2005 | } | |
2006 | ||
1112cf94 DG |
2007 | static const VMStateDescription vmstate_spapr_pci = { |
2008 | .name = "spapr_pci", | |
5a78b821 | 2009 | .version_id = 2, |
9a321e92 AK |
2010 | .minimum_version_id = 2, |
2011 | .pre_save = spapr_pci_pre_save, | |
2012 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 2013 | .fields = (VMStateField[]) { |
ce2918cb DG |
2014 | VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), |
2015 | VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), | |
2016 | VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), | |
2017 | VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), | |
2018 | VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), | |
2019 | VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), | |
2020 | VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, | |
1112cf94 | 2021 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), |
ce2918cb DG |
2022 | VMSTATE_INT32(msi_devs_num, SpaprPhbState), |
2023 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, | |
9a321e92 | 2024 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), |
1112cf94 DG |
2025 | VMSTATE_END_OF_LIST() |
2026 | }, | |
2027 | }; | |
2028 | ||
568f0690 DG |
2029 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
2030 | PCIBus *rootbus) | |
2031 | { | |
ce2918cb | 2032 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); |
568f0690 DG |
2033 | |
2034 | return sphb->dtbusname; | |
2035 | } | |
2036 | ||
298a9710 DG |
2037 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
2038 | { | |
568f0690 | 2039 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 2040 | DeviceClass *dc = DEVICE_CLASS(klass); |
7454c7af | 2041 | HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); |
298a9710 | 2042 | |
568f0690 | 2043 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 2044 | dc->realize = spapr_phb_realize; |
ef28b98d | 2045 | dc->unrealize = spapr_phb_unrealize; |
298a9710 | 2046 | dc->props = spapr_phb_properties; |
eddeed26 | 2047 | dc->reset = spapr_phb_reset; |
1112cf94 | 2048 | dc->vmsd = &vmstate_spapr_pci; |
e4f4fb1e EH |
2049 | /* Supported by TYPE_SPAPR_MACHINE */ |
2050 | dc->user_creatable = true; | |
09aa9a52 | 2051 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
3340e5c4 | 2052 | hp->plug = spapr_pci_plug; |
27c1da51 | 2053 | hp->unplug = spapr_pci_unplug; |
3340e5c4 | 2054 | hp->unplug_request = spapr_pci_unplug_request; |
298a9710 | 2055 | } |
3384f95c | 2056 | |
4240abff | 2057 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 2058 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 2059 | .parent = TYPE_PCI_HOST_BRIDGE, |
ce2918cb | 2060 | .instance_size = sizeof(SpaprPhbState), |
ef28b98d | 2061 | .instance_finalize = spapr_phb_finalizefn, |
298a9710 | 2062 | .class_init = spapr_phb_class_init, |
7454c7af MR |
2063 | .interfaces = (InterfaceInfo[]) { |
2064 | { TYPE_HOTPLUG_HANDLER }, | |
2065 | { } | |
2066 | } | |
298a9710 DG |
2067 | }; |
2068 | ||
ce2918cb | 2069 | typedef struct SpaprFdt { |
1d2d9742 ND |
2070 | void *fdt; |
2071 | int node_off; | |
ce2918cb DG |
2072 | SpaprPhbState *sphb; |
2073 | } SpaprFdt; | |
1d2d9742 ND |
2074 | |
2075 | static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, | |
2076 | void *opaque) | |
2077 | { | |
2078 | PCIBus *sec_bus; | |
ce2918cb | 2079 | SpaprFdt *p = opaque; |
1d2d9742 | 2080 | int offset; |
ce2918cb | 2081 | SpaprFdt s_fdt; |
1d2d9742 | 2082 | |
e634b89c | 2083 | offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); |
1d2d9742 ND |
2084 | if (!offset) { |
2085 | error_report("Failed to create pci child device tree node"); | |
2086 | return; | |
2087 | } | |
2088 | ||
2089 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
2090 | PCI_HEADER_TYPE_BRIDGE)) { | |
2091 | return; | |
2092 | } | |
2093 | ||
2094 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
2095 | if (!sec_bus) { | |
2096 | return; | |
2097 | } | |
2098 | ||
2099 | s_fdt.fdt = p->fdt; | |
2100 | s_fdt.node_off = offset; | |
2101 | s_fdt.sphb = p->sphb; | |
a8eeafda GK |
2102 | pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus), |
2103 | spapr_populate_pci_devices_dt, | |
2104 | &s_fdt); | |
1d2d9742 ND |
2105 | } |
2106 | ||
2107 | static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, | |
2108 | void *opaque) | |
2109 | { | |
2110 | unsigned int *bus_no = opaque; | |
1d2d9742 ND |
2111 | PCIBus *sec_bus = NULL; |
2112 | ||
2113 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
2114 | PCI_HEADER_TYPE_BRIDGE)) { | |
2115 | return; | |
2116 | } | |
2117 | ||
2118 | (*bus_no)++; | |
d8e81d6e | 2119 | pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); |
1d2d9742 ND |
2120 | pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); |
2121 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2122 | ||
2123 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
2124 | if (!sec_bus) { | |
2125 | return; | |
2126 | } | |
2127 | ||
1d2d9742 ND |
2128 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), |
2129 | spapr_phb_pci_enumerate_bridge, bus_no); | |
2130 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2131 | } | |
2132 | ||
ce2918cb | 2133 | static void spapr_phb_pci_enumerate(SpaprPhbState *phb) |
1d2d9742 ND |
2134 | { |
2135 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; | |
2136 | unsigned int bus_no = 0; | |
2137 | ||
2138 | pci_for_each_device(bus, pci_bus_num(bus), | |
2139 | spapr_phb_pci_enumerate_bridge, | |
2140 | &bus_no); | |
2141 | ||
2142 | } | |
2143 | ||
ce2918cb | 2144 | int spapr_populate_pci_dt(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt, |
0a0a66cd | 2145 | uint32_t nr_msis, int *node_offset) |
3384f95c | 2146 | { |
62083979 | 2147 | int bus_off, i, j, ret; |
3384f95c DG |
2148 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
2149 | struct { | |
2150 | uint32_t hi; | |
2151 | uint64_t child; | |
2152 | uint64_t parent; | |
2153 | uint64_t size; | |
c4889f54 | 2154 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
2155 | { |
2156 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
2157 | cpu_to_be64(phb->io_win_addr), | |
2158 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
2159 | }, | |
2160 | { | |
2161 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
2162 | cpu_to_be64(phb->mem_win_addr), | |
daa23699 | 2163 | cpu_to_be64(phb->mem_win_size), |
b194df47 AK |
2164 | }, |
2165 | { | |
daa23699 DG |
2166 | cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), |
2167 | cpu_to_be64(phb->mem64_win_addr), | |
2168 | cpu_to_be64(phb->mem64_win_size), | |
3384f95c DG |
2169 | }, |
2170 | }; | |
daa23699 DG |
2171 | const unsigned sizeof_ranges = |
2172 | (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); | |
3384f95c DG |
2173 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
2174 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
2175 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
2176 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
ae4de14c AK |
2177 | uint32_t ddw_applicable[] = { |
2178 | cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), | |
2179 | cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), | |
2180 | cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) | |
2181 | }; | |
2182 | uint32_t ddw_extensions[] = { | |
2183 | cpu_to_be32(1), | |
2184 | cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) | |
2185 | }; | |
4814401f AK |
2186 | uint32_t associativity[] = {cpu_to_be32(0x4), |
2187 | cpu_to_be32(0x0), | |
2188 | cpu_to_be32(0x0), | |
2189 | cpu_to_be32(0x0), | |
2190 | cpu_to_be32(phb->numa_node)}; | |
ce2918cb | 2191 | SpaprTceTable *tcet; |
1d2d9742 | 2192 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; |
ce2918cb DG |
2193 | SpaprFdt s_fdt; |
2194 | SpaprDrc *drc; | |
ec132efa | 2195 | Error *errp = NULL; |
3384f95c DG |
2196 | |
2197 | /* Start populating the FDT */ | |
c413605b | 2198 | _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); |
0a0a66cd MR |
2199 | if (node_offset) { |
2200 | *node_offset = bus_off; | |
2201 | } | |
3384f95c | 2202 | |
3384f95c DG |
2203 | /* Write PHB properties */ |
2204 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
2205 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
2206 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
2207 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
2208 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
2209 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
2210 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 2211 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 2212 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 2213 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
0976efd5 | 2214 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis)); |
3384f95c | 2215 | |
ae4de14c AK |
2216 | /* Dynamic DMA window */ |
2217 | if (phb->ddw_enabled) { | |
2218 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, | |
2219 | sizeof(ddw_applicable))); | |
2220 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", | |
2221 | &ddw_extensions, sizeof(ddw_extensions))); | |
2222 | } | |
2223 | ||
4814401f | 2224 | /* Advertise NUMA via ibm,associativity */ |
4bcfa56c | 2225 | if (phb->numa_node != -1) { |
4814401f AK |
2226 | _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, |
2227 | sizeof(associativity))); | |
2228 | } | |
2229 | ||
4d8d5467 | 2230 | /* Build the interrupt-map, this must matches what is done |
e8ec4adf | 2231 | * in pci_swizzle_map_irq_fn |
4d8d5467 BH |
2232 | */ |
2233 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
2234 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
2235 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
2236 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
2237 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
e8ec4adf | 2238 | int lsi_num = pci_swizzle(i, j); |
7fb0bd34 DG |
2239 | |
2240 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
2241 | irqmap[1] = 0; | |
2242 | irqmap[2] = 0; | |
2243 | irqmap[3] = cpu_to_be32(j+1); | |
5c7adcf4 GK |
2244 | irqmap[4] = cpu_to_be32(intc_phandle); |
2245 | spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); | |
7fb0bd34 | 2246 | } |
3384f95c | 2247 | } |
3384f95c DG |
2248 | /* Write interrupt map */ |
2249 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 2250 | sizeof(interrupt_map))); |
3384f95c | 2251 | |
ae4de14c | 2252 | tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); |
da34fed7 TH |
2253 | if (!tcet) { |
2254 | return -1; | |
2255 | } | |
ccf9ff85 AK |
2256 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", |
2257 | tcet->liobn, tcet->bus_offset, | |
2258 | tcet->nb_table << tcet->page_shift); | |
edded454 | 2259 | |
f130928d MR |
2260 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); |
2261 | if (drc) { | |
2262 | uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); | |
2263 | ||
2264 | _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, | |
2265 | sizeof(drc_index))); | |
2266 | } | |
2267 | ||
1d2d9742 ND |
2268 | /* Walk the bridges and program the bus numbers*/ |
2269 | spapr_phb_pci_enumerate(phb); | |
2270 | _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); | |
2271 | ||
2272 | /* Populate tree nodes with PCI devices attached */ | |
2273 | s_fdt.fdt = fdt; | |
2274 | s_fdt.node_off = bus_off; | |
2275 | s_fdt.sphb = phb; | |
a8eeafda GK |
2276 | pci_for_each_device_reverse(bus, pci_bus_num(bus), |
2277 | spapr_populate_pci_devices_dt, | |
2278 | &s_fdt); | |
1d2d9742 | 2279 | |
62083979 MR |
2280 | ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), |
2281 | SPAPR_DR_CONNECTOR_TYPE_PCI); | |
2282 | if (ret) { | |
2283 | return ret; | |
2284 | } | |
2285 | ||
ec132efa AK |
2286 | spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &errp); |
2287 | if (errp) { | |
2288 | error_report_err(errp); | |
2289 | } | |
2290 | spapr_phb_nvgpu_ram_populate_dt(phb, fdt); | |
2291 | ||
3384f95c DG |
2292 | return 0; |
2293 | } | |
298a9710 | 2294 | |
fa28f71b AK |
2295 | void spapr_pci_rtas_init(void) |
2296 | { | |
3a3b8502 AK |
2297 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
2298 | rtas_read_pci_config); | |
2299 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
2300 | rtas_write_pci_config); | |
2301 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
2302 | rtas_ibm_read_pci_config); | |
2303 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
2304 | rtas_ibm_write_pci_config); | |
226419d6 | 2305 | if (msi_nonbroken) { |
3a3b8502 AK |
2306 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
2307 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 2308 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
2309 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
2310 | rtas_ibm_change_msi); | |
0ee2c058 | 2311 | } |
ee954280 GS |
2312 | |
2313 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
2314 | "ibm,set-eeh-option", | |
2315 | rtas_ibm_set_eeh_option); | |
2316 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
2317 | "ibm,get-config-addr-info2", | |
2318 | rtas_ibm_get_config_addr_info2); | |
2319 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
2320 | "ibm,read-slot-reset-state2", | |
2321 | rtas_ibm_read_slot_reset_state2); | |
2322 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
2323 | "ibm,set-slot-reset", | |
2324 | rtas_ibm_set_slot_reset); | |
2325 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
2326 | "ibm,configure-pe", | |
2327 | rtas_ibm_configure_pe); | |
2328 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
2329 | "ibm,slot-error-detail", | |
2330 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
2331 | } |
2332 | ||
8c9f64df | 2333 | static void spapr_pci_register_types(void) |
298a9710 DG |
2334 | { |
2335 | type_register_static(&spapr_phb_info); | |
2336 | } | |
8c9f64df AF |
2337 | |
2338 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
2339 | |
2340 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
2341 | { | |
2342 | bool be = *(bool *)opaque; | |
2343 | ||
2344 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
2345 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
2346 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
2347 | &error_abort); | |
2348 | } | |
2349 | return 0; | |
2350 | } | |
2351 | ||
2352 | void spapr_pci_switch_vga(bool big_endian) | |
2353 | { | |
ce2918cb DG |
2354 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
2355 | SpaprPhbState *sphb; | |
eefaccc0 DG |
2356 | |
2357 | /* | |
2358 | * For backward compatibility with existing guests, we switch | |
2359 | * the endianness of the VGA controller when changing the guest | |
2360 | * interrupt mode | |
2361 | */ | |
2362 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
2363 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
2364 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
2365 | &big_endian); | |
2366 | } | |
2367 | } |