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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/pci/pci.h" | |
27 | #include "hw/pci/msi.h" | |
28 | #include "hw/pci/msix.h" | |
29 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
30 | #include "hw/ppc/spapr.h" |
31 | #include "hw/pci-host/spapr.h" | |
022c62cb | 32 | #include "exec/address-spaces.h" |
3384f95c | 33 | #include <libfdt.h> |
a2950fb6 | 34 | #include "trace.h" |
3384f95c | 35 | |
06aac7bd | 36 | #include "hw/pci/pci_bus.h" |
3384f95c | 37 | |
0ee2c058 AK |
38 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
39 | #define RTAS_QUERY_FN 0 | |
40 | #define RTAS_CHANGE_FN 1 | |
41 | #define RTAS_RESET_FN 2 | |
42 | #define RTAS_CHANGE_MSI_FN 3 | |
43 | #define RTAS_CHANGE_MSIX_FN 4 | |
44 | ||
45 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
46 | #define RTAS_TYPE_MSI 1 | |
47 | #define RTAS_TYPE_MSIX 2 | |
48 | ||
9894c5d4 | 49 | static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid) |
3384f95c | 50 | { |
8c9f64df | 51 | sPAPRPHBState *sphb; |
3384f95c | 52 | |
8c9f64df AF |
53 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
54 | if (sphb->buid != buid) { | |
3384f95c DG |
55 | continue; |
56 | } | |
8c9f64df | 57 | return sphb; |
9894c5d4 AK |
58 | } |
59 | ||
60 | return NULL; | |
61 | } | |
62 | ||
63 | static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid, | |
64 | uint32_t config_addr) | |
65 | { | |
8c9f64df | 66 | sPAPRPHBState *sphb = find_phb(spapr, buid); |
8558d942 | 67 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
8c9f64df | 68 | BusState *bus = BUS(phb->bus); |
9894c5d4 AK |
69 | BusChild *kid; |
70 | int devfn = (config_addr >> 8) & 0xFF; | |
71 | ||
72 | if (!phb) { | |
73 | return NULL; | |
74 | } | |
3384f95c | 75 | |
8c9f64df | 76 | QTAILQ_FOREACH(kid, &bus->children, sibling) { |
9894c5d4 AK |
77 | PCIDevice *dev = (PCIDevice *)kid->child; |
78 | if (dev->devfn == devfn) { | |
79 | return dev; | |
3384f95c DG |
80 | } |
81 | } | |
82 | ||
83 | return NULL; | |
84 | } | |
85 | ||
3f7565c9 BH |
86 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
87 | { | |
92615a5a | 88 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
89 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
90 | } | |
91 | ||
92615a5a DG |
92 | static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, |
93 | uint32_t addr, uint32_t size, | |
94 | target_ulong rets) | |
88045ac5 | 95 | { |
92615a5a DG |
96 | PCIDevice *pci_dev; |
97 | uint32_t val; | |
98 | ||
99 | if ((size != 1) && (size != 2) && (size != 4)) { | |
100 | /* access must be 1, 2 or 4 bytes */ | |
101 | rtas_st(rets, 0, -1); | |
102 | return; | |
88045ac5 | 103 | } |
88045ac5 | 104 | |
92615a5a DG |
105 | pci_dev = find_dev(spapr, buid, addr); |
106 | addr = rtas_pci_cfgaddr(addr); | |
107 | ||
108 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
109 | /* Access must be to a valid device, within bounds and | |
110 | * naturally aligned */ | |
111 | rtas_st(rets, 0, -1); | |
112 | return; | |
88045ac5 | 113 | } |
92615a5a DG |
114 | |
115 | val = pci_host_config_read_common(pci_dev, addr, | |
116 | pci_config_size(pci_dev), size); | |
117 | ||
118 | rtas_st(rets, 0, 0); | |
119 | rtas_st(rets, 1, val); | |
88045ac5 AG |
120 | } |
121 | ||
210b580b | 122 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
123 | uint32_t token, uint32_t nargs, |
124 | target_ulong args, | |
125 | uint32_t nret, target_ulong rets) | |
126 | { | |
92615a5a DG |
127 | uint64_t buid; |
128 | uint32_t size, addr; | |
3384f95c | 129 | |
92615a5a | 130 | if ((nargs != 4) || (nret != 2)) { |
3384f95c DG |
131 | rtas_st(rets, 0, -1); |
132 | return; | |
133 | } | |
92615a5a DG |
134 | |
135 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c | 136 | size = rtas_ld(args, 3); |
92615a5a DG |
137 | addr = rtas_ld(args, 0); |
138 | ||
139 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
140 | } |
141 | ||
210b580b | 142 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
143 | uint32_t token, uint32_t nargs, |
144 | target_ulong args, | |
145 | uint32_t nret, target_ulong rets) | |
146 | { | |
92615a5a | 147 | uint32_t size, addr; |
3384f95c | 148 | |
92615a5a | 149 | if ((nargs != 2) || (nret != 2)) { |
3384f95c DG |
150 | rtas_st(rets, 0, -1); |
151 | return; | |
152 | } | |
92615a5a | 153 | |
3384f95c | 154 | size = rtas_ld(args, 1); |
92615a5a DG |
155 | addr = rtas_ld(args, 0); |
156 | ||
157 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
158 | } | |
159 | ||
160 | static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, | |
161 | uint32_t addr, uint32_t size, | |
162 | uint32_t val, target_ulong rets) | |
163 | { | |
164 | PCIDevice *pci_dev; | |
165 | ||
166 | if ((size != 1) && (size != 2) && (size != 4)) { | |
167 | /* access must be 1, 2 or 4 bytes */ | |
168 | rtas_st(rets, 0, -1); | |
169 | return; | |
170 | } | |
171 | ||
172 | pci_dev = find_dev(spapr, buid, addr); | |
173 | addr = rtas_pci_cfgaddr(addr); | |
174 | ||
175 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
176 | /* Access must be to a valid device, within bounds and | |
177 | * naturally aligned */ | |
178 | rtas_st(rets, 0, -1); | |
179 | return; | |
180 | } | |
181 | ||
182 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
183 | val, size); | |
184 | ||
3384f95c | 185 | rtas_st(rets, 0, 0); |
3384f95c DG |
186 | } |
187 | ||
210b580b | 188 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
189 | uint32_t token, uint32_t nargs, |
190 | target_ulong args, | |
191 | uint32_t nret, target_ulong rets) | |
192 | { | |
92615a5a | 193 | uint64_t buid; |
3384f95c | 194 | uint32_t val, size, addr; |
3384f95c | 195 | |
92615a5a | 196 | if ((nargs != 5) || (nret != 1)) { |
3384f95c DG |
197 | rtas_st(rets, 0, -1); |
198 | return; | |
199 | } | |
92615a5a DG |
200 | |
201 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c DG |
202 | val = rtas_ld(args, 4); |
203 | size = rtas_ld(args, 3); | |
92615a5a DG |
204 | addr = rtas_ld(args, 0); |
205 | ||
206 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
207 | } |
208 | ||
210b580b | 209 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
210 | uint32_t token, uint32_t nargs, |
211 | target_ulong args, | |
212 | uint32_t nret, target_ulong rets) | |
213 | { | |
214 | uint32_t val, size, addr; | |
3384f95c | 215 | |
92615a5a | 216 | if ((nargs != 3) || (nret != 1)) { |
3384f95c DG |
217 | rtas_st(rets, 0, -1); |
218 | return; | |
219 | } | |
92615a5a DG |
220 | |
221 | ||
3384f95c DG |
222 | val = rtas_ld(args, 2); |
223 | size = rtas_ld(args, 1); | |
92615a5a DG |
224 | addr = rtas_ld(args, 0); |
225 | ||
226 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
227 | } |
228 | ||
0ee2c058 AK |
229 | /* |
230 | * Find an entry with config_addr or returns the empty one if not found AND | |
231 | * alloc_new is set. | |
232 | * At the moment the msi_table entries are never released so there is | |
233 | * no point to look till the end of the list if we need to find the free entry. | |
234 | */ | |
235 | static int spapr_msicfg_find(sPAPRPHBState *phb, uint32_t config_addr, | |
236 | bool alloc_new) | |
237 | { | |
238 | int i; | |
239 | ||
240 | for (i = 0; i < SPAPR_MSIX_MAX_DEVS; ++i) { | |
241 | if (!phb->msi_table[i].nvec) { | |
242 | break; | |
243 | } | |
244 | if (phb->msi_table[i].config_addr == config_addr) { | |
245 | return i; | |
246 | } | |
247 | } | |
248 | if ((i < SPAPR_MSIX_MAX_DEVS) && alloc_new) { | |
249 | trace_spapr_pci_msi("Allocating new MSI config", i, config_addr); | |
250 | return i; | |
251 | } | |
252 | ||
253 | return -1; | |
254 | } | |
255 | ||
256 | /* | |
257 | * Set MSI/MSIX message data. | |
258 | * This is required for msi_notify()/msix_notify() which | |
259 | * will write at the addresses via spapr_msi_write(). | |
260 | */ | |
a8170e5e | 261 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, |
0ee2c058 AK |
262 | bool msix, unsigned req_num) |
263 | { | |
264 | unsigned i; | |
265 | MSIMessage msg = { .address = addr, .data = 0 }; | |
266 | ||
267 | if (!msix) { | |
268 | msi_set_message(pdev, msg); | |
269 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
270 | return; | |
271 | } | |
272 | ||
273 | for (i = 0; i < req_num; ++i) { | |
274 | msg.address = addr | (i << 2); | |
275 | msix_set_message(pdev, i, msg); | |
276 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
277 | } | |
278 | } | |
279 | ||
210b580b | 280 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
0ee2c058 AK |
281 | uint32_t token, uint32_t nargs, |
282 | target_ulong args, uint32_t nret, | |
283 | target_ulong rets) | |
284 | { | |
285 | uint32_t config_addr = rtas_ld(args, 0); | |
286 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
287 | unsigned int func = rtas_ld(args, 3); | |
288 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
289 | unsigned int seq_num = rtas_ld(args, 5); | |
290 | unsigned int ret_intr_type; | |
291 | int ndev, irq; | |
292 | sPAPRPHBState *phb = NULL; | |
293 | PCIDevice *pdev = NULL; | |
294 | ||
295 | switch (func) { | |
296 | case RTAS_CHANGE_MSI_FN: | |
297 | case RTAS_CHANGE_FN: | |
298 | ret_intr_type = RTAS_TYPE_MSI; | |
299 | break; | |
300 | case RTAS_CHANGE_MSIX_FN: | |
301 | ret_intr_type = RTAS_TYPE_MSIX; | |
302 | break; | |
303 | default: | |
304 | fprintf(stderr, "rtas_ibm_change_msi(%u) is not implemented\n", func); | |
305 | rtas_st(rets, 0, -3); /* Parameter error */ | |
306 | return; | |
307 | } | |
308 | ||
309 | /* Fins sPAPRPHBState */ | |
310 | phb = find_phb(spapr, buid); | |
311 | if (phb) { | |
312 | pdev = find_dev(spapr, buid, config_addr); | |
313 | } | |
314 | if (!phb || !pdev) { | |
315 | rtas_st(rets, 0, -3); /* Parameter error */ | |
316 | return; | |
317 | } | |
318 | ||
319 | /* Releasing MSIs */ | |
320 | if (!req_num) { | |
321 | ndev = spapr_msicfg_find(phb, config_addr, false); | |
322 | if (ndev < 0) { | |
323 | trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr); | |
324 | rtas_st(rets, 0, -1); /* Hardware error */ | |
325 | return; | |
326 | } | |
327 | trace_spapr_pci_msi("Released MSIs", ndev, config_addr); | |
328 | rtas_st(rets, 0, 0); | |
329 | rtas_st(rets, 1, 0); | |
330 | return; | |
331 | } | |
332 | ||
333 | /* Enabling MSI */ | |
334 | ||
335 | /* Find a device number in the map to add or reuse the existing one */ | |
336 | ndev = spapr_msicfg_find(phb, config_addr, true); | |
337 | if (ndev >= SPAPR_MSIX_MAX_DEVS || ndev < 0) { | |
338 | fprintf(stderr, "No free entry for a new MSI device\n"); | |
339 | rtas_st(rets, 0, -1); /* Hardware error */ | |
340 | return; | |
341 | } | |
342 | trace_spapr_pci_msi("Configuring MSI", ndev, config_addr); | |
343 | ||
344 | /* Check if there is an old config and MSI number has not changed */ | |
345 | if (phb->msi_table[ndev].nvec && (req_num != phb->msi_table[ndev].nvec)) { | |
346 | /* Unexpected behaviour */ | |
347 | fprintf(stderr, "Cannot reuse MSI config for device#%d", ndev); | |
348 | rtas_st(rets, 0, -1); /* Hardware error */ | |
349 | return; | |
350 | } | |
351 | ||
352 | /* There is no cached config, allocate MSIs */ | |
353 | if (!phb->msi_table[ndev].nvec) { | |
70c68cf6 | 354 | irq = spapr_allocate_irq_block(req_num, false); |
0ee2c058 AK |
355 | if (irq < 0) { |
356 | fprintf(stderr, "Cannot allocate MSIs for device#%d", ndev); | |
357 | rtas_st(rets, 0, -1); /* Hardware error */ | |
358 | return; | |
359 | } | |
360 | phb->msi_table[ndev].irq = irq; | |
361 | phb->msi_table[ndev].nvec = req_num; | |
362 | phb->msi_table[ndev].config_addr = config_addr; | |
363 | } | |
364 | ||
365 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ | |
366 | spapr_msi_setmsg(pdev, phb->msi_win_addr | (ndev << 16), | |
367 | ret_intr_type == RTAS_TYPE_MSIX, req_num); | |
368 | ||
369 | rtas_st(rets, 0, 0); | |
370 | rtas_st(rets, 1, req_num); | |
371 | rtas_st(rets, 2, ++seq_num); | |
372 | rtas_st(rets, 3, ret_intr_type); | |
373 | ||
374 | trace_spapr_pci_rtas_ibm_change_msi(func, req_num); | |
375 | } | |
376 | ||
210b580b AL |
377 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
378 | sPAPREnvironment *spapr, | |
0ee2c058 AK |
379 | uint32_t token, |
380 | uint32_t nargs, | |
381 | target_ulong args, | |
382 | uint32_t nret, | |
383 | target_ulong rets) | |
384 | { | |
385 | uint32_t config_addr = rtas_ld(args, 0); | |
386 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
387 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); | |
388 | int ndev; | |
389 | sPAPRPHBState *phb = NULL; | |
390 | ||
391 | /* Fins sPAPRPHBState */ | |
392 | phb = find_phb(spapr, buid); | |
393 | if (!phb) { | |
394 | rtas_st(rets, 0, -3); /* Parameter error */ | |
395 | return; | |
396 | } | |
397 | ||
398 | /* Find device descriptor and start IRQ */ | |
399 | ndev = spapr_msicfg_find(phb, config_addr, false); | |
400 | if (ndev < 0) { | |
401 | trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr); | |
402 | rtas_st(rets, 0, -1); /* Hardware error */ | |
403 | return; | |
404 | } | |
405 | ||
406 | intr_src_num = phb->msi_table[ndev].irq + ioa_intr_num; | |
407 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, | |
408 | intr_src_num); | |
409 | ||
410 | rtas_st(rets, 0, 0); | |
411 | rtas_st(rets, 1, intr_src_num); | |
412 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
413 | } | |
414 | ||
7fb0bd34 DG |
415 | static int pci_spapr_swizzle(int slot, int pin) |
416 | { | |
417 | return (slot + pin) % PCI_NUM_PINS; | |
418 | } | |
419 | ||
3384f95c DG |
420 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
421 | { | |
422 | /* | |
423 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
424 | * which is less than number of IRQs on the specific bus (4). We |
425 | * use standard PCI swizzling, that is (slot number + pin number) | |
426 | * % 4. | |
3384f95c | 427 | */ |
7fb0bd34 | 428 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
429 | } |
430 | ||
431 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
432 | { | |
433 | /* | |
434 | * Here we use the number returned by pci_spapr_map_irq to find a | |
435 | * corresponding qemu_irq. | |
436 | */ | |
437 | sPAPRPHBState *phb = opaque; | |
438 | ||
caae58cb | 439 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 440 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
441 | } |
442 | ||
0ee2c058 AK |
443 | /* |
444 | * MSI/MSIX memory region implementation. | |
445 | * The handler handles both MSI and MSIX. | |
446 | * For MSI-X, the vector number is encoded as a part of the address, | |
447 | * data is set to 0. | |
448 | * For MSI, the vector number is encoded in least bits in data. | |
449 | */ | |
a8170e5e | 450 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
451 | uint64_t data, unsigned size) |
452 | { | |
453 | sPAPRPHBState *phb = opaque; | |
454 | int ndev = addr >> 16; | |
455 | int vec = ((addr & 0xFFFF) >> 2) | data; | |
456 | uint32_t irq = phb->msi_table[ndev].irq + vec; | |
457 | ||
458 | trace_spapr_pci_msi_write(addr, data, irq); | |
459 | ||
460 | qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); | |
461 | } | |
462 | ||
463 | static const MemoryRegionOps spapr_msi_ops = { | |
464 | /* There is no .read as the read result is undefined by PCI spec */ | |
465 | .read = NULL, | |
466 | .write = spapr_msi_write, | |
467 | .endianness = DEVICE_LITTLE_ENDIAN | |
468 | }; | |
469 | ||
298a9710 DG |
470 | /* |
471 | * PHB PCI device | |
472 | */ | |
e00387d5 | 473 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
474 | { |
475 | sPAPRPHBState *phb = opaque; | |
476 | ||
e00387d5 | 477 | return &phb->iommu_as; |
edded454 DG |
478 | } |
479 | ||
298a9710 | 480 | static int spapr_phb_init(SysBusDevice *s) |
3384f95c | 481 | { |
8c9f64df | 482 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 483 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
89dfd6e1 | 484 | const char *busname; |
298a9710 DG |
485 | char *namebuf; |
486 | int i; | |
3384f95c | 487 | PCIBus *bus; |
3384f95c | 488 | |
caae58cb DG |
489 | if (sphb->index != -1) { |
490 | hwaddr windows_base; | |
491 | ||
492 | if ((sphb->buid != -1) || (sphb->dma_liobn != -1) | |
493 | || (sphb->mem_win_addr != -1) | |
494 | || (sphb->io_win_addr != -1) | |
495 | || (sphb->msi_win_addr != -1)) { | |
496 | fprintf(stderr, "Either \"index\" or other parameters must" | |
497 | " be specified for PAPR PHB, not both\n"); | |
498 | return -1; | |
499 | } | |
500 | ||
501 | sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; | |
502 | sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN + sphb->index; | |
503 | ||
504 | windows_base = SPAPR_PCI_WINDOW_BASE | |
505 | + sphb->index * SPAPR_PCI_WINDOW_SPACING; | |
506 | sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; | |
507 | sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; | |
508 | sphb->msi_win_addr = windows_base + SPAPR_PCI_MSI_WIN_OFF; | |
509 | } | |
510 | ||
511 | if (sphb->buid == -1) { | |
512 | fprintf(stderr, "BUID not specified for PHB\n"); | |
513 | return -1; | |
514 | } | |
515 | ||
516 | if (sphb->dma_liobn == -1) { | |
517 | fprintf(stderr, "LIOBN not specified for PHB\n"); | |
518 | return -1; | |
519 | } | |
520 | ||
521 | if (sphb->mem_win_addr == -1) { | |
522 | fprintf(stderr, "Memory window address not specified for PHB\n"); | |
523 | return -1; | |
524 | } | |
525 | ||
526 | if (sphb->io_win_addr == -1) { | |
527 | fprintf(stderr, "IO window address not specified for PHB\n"); | |
528 | return -1; | |
529 | } | |
530 | ||
531 | if (sphb->msi_win_addr == -1) { | |
532 | fprintf(stderr, "MSI window address not specified for PHB\n"); | |
533 | return -1; | |
534 | } | |
535 | ||
536 | if (find_phb(spapr, sphb->buid)) { | |
537 | fprintf(stderr, "PCI host bridges must have unique BUIDs\n"); | |
538 | return -1; | |
539 | } | |
540 | ||
8c9f64df | 541 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 542 | |
8c9f64df | 543 | namebuf = alloca(strlen(sphb->dtbusname) + 32); |
3384f95c | 544 | |
298a9710 | 545 | /* Initialize memory regions */ |
8c9f64df | 546 | sprintf(namebuf, "%s.mmio", sphb->dtbusname); |
40c5dce9 | 547 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, INT64_MAX); |
3384f95c | 548 | |
8c9f64df | 549 | sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); |
40c5dce9 PB |
550 | memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), |
551 | namebuf, &sphb->memspace, | |
8c9f64df AF |
552 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
553 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, | |
554 | &sphb->memwindow); | |
3384f95c | 555 | |
3384f95c DG |
556 | /* On ppc, we only have MMIO no specific IO space from the CPU |
557 | * perspective. In theory we ought to be able to embed the PCI IO | |
558 | * memory region direction in the system memory space. However, | |
559 | * if any of the IO BAR subregions use the old_portio mechanism, | |
560 | * that won't be processed properly unless accessed from the | |
561 | * system io address space. This hack to bounce things via | |
562 | * system_io works around the problem until all the users of | |
563 | * old_portion are updated */ | |
8c9f64df | 564 | sprintf(namebuf, "%s.io", sphb->dtbusname); |
40c5dce9 PB |
565 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
566 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
a3cfa18e DG |
567 | /* FIXME: fix to support multiple PHBs */ |
568 | memory_region_add_subregion(get_system_io(), 0, &sphb->iospace); | |
3384f95c | 569 | |
a3cfa18e | 570 | sprintf(namebuf, "%s.io-alias", sphb->dtbusname); |
66aab867 AK |
571 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
572 | get_system_io(), 0, SPAPR_PCI_IO_WIN_SIZE); | |
8c9f64df | 573 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 574 | &sphb->iowindow); |
3384f95c | 575 | |
0ee2c058 AK |
576 | /* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, |
577 | * we need to allocate some memory to catch those writes coming | |
578 | * from msi_notify()/msix_notify() */ | |
579 | if (msi_supported) { | |
8c9f64df | 580 | sprintf(namebuf, "%s.msi", sphb->dtbusname); |
40c5dce9 | 581 | memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, sphb, |
0ee2c058 | 582 | namebuf, SPAPR_MSIX_MAX_DEVS * 0x10000); |
8c9f64df AF |
583 | memory_region_add_subregion(get_system_memory(), sphb->msi_win_addr, |
584 | &sphb->msiwindow); | |
0ee2c058 AK |
585 | } |
586 | ||
89dfd6e1 DG |
587 | /* |
588 | * Selecting a busname is more complex than you'd think, due to | |
589 | * interacting constraints. If the user has specified an id | |
590 | * explicitly for the phb , then we want to use the qdev default | |
591 | * of naming the bus based on the bridge device (so the user can | |
592 | * then assign devices to it in the way they expect). For the | |
593 | * first / default PCI bus (index=0) we want to use just "pci" | |
594 | * because libvirt expects there to be a bus called, simply, | |
595 | * "pci". Otherwise, we use the same name as in the device tree, | |
596 | * since it's unique by construction, and makes the guest visible | |
597 | * BUID clear. | |
598 | */ | |
599 | if (s->qdev.id) { | |
600 | busname = NULL; | |
601 | } else if (sphb->index == 0) { | |
602 | busname = "pci"; | |
603 | } else { | |
604 | busname = sphb->dtbusname; | |
605 | } | |
606 | bus = pci_register_bus(DEVICE(s), busname, | |
8c9f64df AF |
607 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, |
608 | &sphb->memspace, &sphb->iospace, | |
60a0e443 | 609 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); |
8c9f64df | 610 | phb->bus = bus; |
298a9710 | 611 | |
8c9f64df AF |
612 | sphb->dma_window_start = 0; |
613 | sphb->dma_window_size = 0x40000000; | |
84af6d9f PB |
614 | sphb->tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, |
615 | sphb->dma_window_size); | |
2b7dc949 | 616 | if (!sphb->tcet) { |
caae58cb DG |
617 | fprintf(stderr, "Unable to create TCE table for %s\n", sphb->dtbusname); |
618 | return -1; | |
619 | } | |
7dca8043 AK |
620 | address_space_init(&sphb->iommu_as, spapr_tce_get_iommu(sphb->tcet), |
621 | sphb->dtbusname); | |
622 | ||
e00387d5 | 623 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 624 | |
8c9f64df | 625 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
626 | |
627 | /* Initialize the LSI table */ | |
7fb0bd34 | 628 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 629 | uint32_t irq; |
298a9710 | 630 | |
a307d594 AK |
631 | irq = spapr_allocate_lsi(0); |
632 | if (!irq) { | |
298a9710 DG |
633 | return -1; |
634 | } | |
635 | ||
8c9f64df | 636 | sphb->lsi_table[i].irq = irq; |
298a9710 DG |
637 | } |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
eddeed26 DG |
642 | static void spapr_phb_reset(DeviceState *qdev) |
643 | { | |
1356b98d | 644 | SysBusDevice *s = SYS_BUS_DEVICE(qdev); |
eddeed26 DG |
645 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
646 | ||
647 | /* Reset the IOMMU state */ | |
a83000f5 | 648 | device_reset(DEVICE(sphb->tcet)); |
eddeed26 DG |
649 | } |
650 | ||
298a9710 | 651 | static Property spapr_phb_properties[] = { |
caae58cb DG |
652 | DEFINE_PROP_INT32("index", sPAPRPHBState, index, -1), |
653 | DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, -1), | |
654 | DEFINE_PROP_HEX32("liobn", sPAPRPHBState, dma_liobn, -1), | |
655 | DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), | |
656 | DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, | |
657 | SPAPR_PCI_MMIO_WIN_SIZE), | |
658 | DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, -1), | |
659 | DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, | |
660 | SPAPR_PCI_IO_WIN_SIZE), | |
661 | DEFINE_PROP_HEX64("msi_win_addr", sPAPRPHBState, msi_win_addr, -1), | |
298a9710 DG |
662 | DEFINE_PROP_END_OF_LIST(), |
663 | }; | |
664 | ||
568f0690 DG |
665 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
666 | PCIBus *rootbus) | |
667 | { | |
668 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
669 | ||
670 | return sphb->dtbusname; | |
671 | } | |
672 | ||
298a9710 DG |
673 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
674 | { | |
568f0690 | 675 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 DG |
676 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
677 | DeviceClass *dc = DEVICE_CLASS(klass); | |
678 | ||
568f0690 | 679 | hc->root_bus_path = spapr_phb_root_bus_path; |
298a9710 DG |
680 | sdc->init = spapr_phb_init; |
681 | dc->props = spapr_phb_properties; | |
eddeed26 | 682 | dc->reset = spapr_phb_reset; |
298a9710 | 683 | } |
3384f95c | 684 | |
4240abff | 685 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 686 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 687 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
688 | .instance_size = sizeof(sPAPRPHBState), |
689 | .class_init = spapr_phb_class_init, | |
690 | }; | |
691 | ||
89dfd6e1 | 692 | PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index) |
298a9710 DG |
693 | { |
694 | DeviceState *dev; | |
695 | ||
8c9f64df | 696 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 697 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 698 | qdev_init_nofail(dev); |
caae58cb DG |
699 | |
700 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
701 | } |
702 | ||
703 | /* Macros to operate with address in OF binding to PCI */ | |
704 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
705 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
706 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
707 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
708 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
709 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
710 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
711 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
712 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
713 | ||
e0fdbd7c AK |
714 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
715 | uint32_t xics_phandle, | |
716 | void *fdt) | |
3384f95c | 717 | { |
7fb0bd34 | 718 | int bus_off, i, j; |
3384f95c | 719 | char nodename[256]; |
3384f95c DG |
720 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
721 | struct { | |
722 | uint32_t hi; | |
723 | uint64_t child; | |
724 | uint64_t parent; | |
725 | uint64_t size; | |
c4889f54 | 726 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
727 | { |
728 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
729 | cpu_to_be64(phb->io_win_addr), | |
730 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
731 | }, | |
732 | { | |
733 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
734 | cpu_to_be64(phb->mem_win_addr), | |
735 | cpu_to_be64(memory_region_size(&phb->memwindow)), | |
736 | }, | |
737 | }; | |
738 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; | |
739 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
740 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
741 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
3384f95c DG |
742 | |
743 | /* Start populating the FDT */ | |
744 | sprintf(nodename, "pci@%" PRIx64, phb->buid); | |
745 | bus_off = fdt_add_subnode(fdt, 0, nodename); | |
746 | if (bus_off < 0) { | |
747 | return bus_off; | |
748 | } | |
749 | ||
750 | #define _FDT(exp) \ | |
751 | do { \ | |
752 | int ret = (exp); \ | |
753 | if (ret < 0) { \ | |
754 | return ret; \ | |
755 | } \ | |
756 | } while (0) | |
757 | ||
758 | /* Write PHB properties */ | |
759 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
760 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
761 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
762 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
763 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
764 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
765 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
766 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges))); | |
767 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); | |
3f7565c9 | 768 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
3384f95c | 769 | |
4d8d5467 BH |
770 | /* Build the interrupt-map, this must matches what is done |
771 | * in pci_spapr_map_irq | |
772 | */ | |
773 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
774 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
775 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
776 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
777 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
778 | int lsi_num = pci_spapr_swizzle(i, j); | |
779 | ||
780 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
781 | irqmap[1] = 0; | |
782 | irqmap[2] = 0; | |
783 | irqmap[3] = cpu_to_be32(j+1); | |
784 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 785 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
786 | irqmap[6] = cpu_to_be32(0x8); |
787 | } | |
3384f95c | 788 | } |
3384f95c DG |
789 | /* Write interrupt map */ |
790 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 791 | sizeof(interrupt_map))); |
3384f95c | 792 | |
5c4cbcf2 AK |
793 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", |
794 | phb->dma_liobn, phb->dma_window_start, | |
795 | phb->dma_window_size); | |
edded454 | 796 | |
3384f95c DG |
797 | return 0; |
798 | } | |
298a9710 | 799 | |
fa28f71b AK |
800 | void spapr_pci_rtas_init(void) |
801 | { | |
802 | spapr_rtas_register("read-pci-config", rtas_read_pci_config); | |
803 | spapr_rtas_register("write-pci-config", rtas_write_pci_config); | |
804 | spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config); | |
805 | spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config); | |
0ee2c058 AK |
806 | if (msi_supported) { |
807 | spapr_rtas_register("ibm,query-interrupt-source-number", | |
808 | rtas_ibm_query_interrupt_source_number); | |
809 | spapr_rtas_register("ibm,change-msi", rtas_ibm_change_msi); | |
810 | } | |
fa28f71b AK |
811 | } |
812 | ||
8c9f64df | 813 | static void spapr_pci_register_types(void) |
298a9710 DG |
814 | { |
815 | type_register_static(&spapr_phb_info); | |
816 | } | |
8c9f64df AF |
817 | |
818 | type_init(spapr_pci_register_types) |