]>
Commit | Line | Data |
---|---|---|
3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0d75590d | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 PB |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" | |
83c9f4ca | 29 | #include "hw/hw.h" |
1d2d9742 | 30 | #include "hw/sysbus.h" |
83c9f4ca PB |
31 | #include "hw/pci/pci.h" |
32 | #include "hw/pci/msi.h" | |
33 | #include "hw/pci/msix.h" | |
34 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
35 | #include "hw/ppc/spapr.h" |
36 | #include "hw/pci-host/spapr.h" | |
022c62cb | 37 | #include "exec/address-spaces.h" |
ae4de14c | 38 | #include "exec/ram_addr.h" |
3384f95c | 39 | #include <libfdt.h> |
a2950fb6 | 40 | #include "trace.h" |
295d51aa | 41 | #include "qemu/error-report.h" |
7454c7af | 42 | #include "qapi/qmp/qerror.h" |
3384f95c | 43 | |
1d2d9742 | 44 | #include "hw/pci/pci_bridge.h" |
06aac7bd | 45 | #include "hw/pci/pci_bus.h" |
2530a1a5 | 46 | #include "hw/pci/pci_ids.h" |
62083979 | 47 | #include "hw/ppc/spapr_drc.h" |
7454c7af | 48 | #include "sysemu/device_tree.h" |
77ac58dd | 49 | #include "sysemu/kvm.h" |
ae4de14c | 50 | #include "sysemu/hostmem.h" |
4814401f | 51 | #include "sysemu/numa.h" |
3384f95c | 52 | |
c1fa017c DG |
53 | #include "hw/vfio/vfio.h" |
54 | ||
0ee2c058 AK |
55 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
56 | #define RTAS_QUERY_FN 0 | |
57 | #define RTAS_CHANGE_FN 1 | |
58 | #define RTAS_RESET_FN 2 | |
59 | #define RTAS_CHANGE_MSI_FN 3 | |
60 | #define RTAS_CHANGE_MSIX_FN 4 | |
61 | ||
62 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
63 | #define RTAS_TYPE_MSI 1 | |
64 | #define RTAS_TYPE_MSIX 2 | |
65 | ||
9b7d9284 ND |
66 | #define FDT_NAME_MAX 128 |
67 | ||
7454c7af MR |
68 | #define _FDT(exp) \ |
69 | do { \ | |
70 | int ret = (exp); \ | |
71 | if (ret < 0) { \ | |
72 | return ret; \ | |
73 | } \ | |
74 | } while (0) | |
75 | ||
28e02042 | 76 | sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) |
3384f95c | 77 | { |
8c9f64df | 78 | sPAPRPHBState *sphb; |
3384f95c | 79 | |
8c9f64df AF |
80 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
81 | if (sphb->buid != buid) { | |
3384f95c DG |
82 | continue; |
83 | } | |
8c9f64df | 84 | return sphb; |
9894c5d4 AK |
85 | } |
86 | ||
87 | return NULL; | |
88 | } | |
89 | ||
28e02042 | 90 | PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, |
46c5874e | 91 | uint32_t config_addr) |
9894c5d4 | 92 | { |
46c5874e | 93 | sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 94 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 95 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
96 | int devfn = (config_addr >> 8) & 0xFF; |
97 | ||
98 | if (!phb) { | |
99 | return NULL; | |
100 | } | |
3384f95c | 101 | |
5dac82ce | 102 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
103 | } |
104 | ||
3f7565c9 BH |
105 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
106 | { | |
92615a5a | 107 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
108 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
109 | } | |
110 | ||
28e02042 | 111 | static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
112 | uint32_t addr, uint32_t size, |
113 | target_ulong rets) | |
88045ac5 | 114 | { |
92615a5a DG |
115 | PCIDevice *pci_dev; |
116 | uint32_t val; | |
117 | ||
118 | if ((size != 1) && (size != 2) && (size != 4)) { | |
119 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 120 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 121 | return; |
88045ac5 | 122 | } |
88045ac5 | 123 | |
46c5874e | 124 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
125 | addr = rtas_pci_cfgaddr(addr); |
126 | ||
127 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
128 | /* Access must be to a valid device, within bounds and | |
129 | * naturally aligned */ | |
a64d325d | 130 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 131 | return; |
88045ac5 | 132 | } |
92615a5a DG |
133 | |
134 | val = pci_host_config_read_common(pci_dev, addr, | |
135 | pci_config_size(pci_dev), size); | |
136 | ||
a64d325d | 137 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 138 | rtas_st(rets, 1, val); |
88045ac5 AG |
139 | } |
140 | ||
28e02042 | 141 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
142 | uint32_t token, uint32_t nargs, |
143 | target_ulong args, | |
144 | uint32_t nret, target_ulong rets) | |
145 | { | |
92615a5a DG |
146 | uint64_t buid; |
147 | uint32_t size, addr; | |
3384f95c | 148 | |
92615a5a | 149 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 150 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
151 | return; |
152 | } | |
92615a5a | 153 | |
a14aa92b | 154 | buid = rtas_ldq(args, 1); |
3384f95c | 155 | size = rtas_ld(args, 3); |
92615a5a DG |
156 | addr = rtas_ld(args, 0); |
157 | ||
158 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
159 | } |
160 | ||
28e02042 | 161 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
162 | uint32_t token, uint32_t nargs, |
163 | target_ulong args, | |
164 | uint32_t nret, target_ulong rets) | |
165 | { | |
92615a5a | 166 | uint32_t size, addr; |
3384f95c | 167 | |
92615a5a | 168 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 169 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
170 | return; |
171 | } | |
92615a5a | 172 | |
3384f95c | 173 | size = rtas_ld(args, 1); |
92615a5a DG |
174 | addr = rtas_ld(args, 0); |
175 | ||
176 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
177 | } | |
178 | ||
28e02042 | 179 | static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
180 | uint32_t addr, uint32_t size, |
181 | uint32_t val, target_ulong rets) | |
182 | { | |
183 | PCIDevice *pci_dev; | |
184 | ||
185 | if ((size != 1) && (size != 2) && (size != 4)) { | |
186 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 187 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
188 | return; |
189 | } | |
190 | ||
46c5874e | 191 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
192 | addr = rtas_pci_cfgaddr(addr); |
193 | ||
194 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
195 | /* Access must be to a valid device, within bounds and | |
196 | * naturally aligned */ | |
a64d325d | 197 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
198 | return; |
199 | } | |
200 | ||
201 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
202 | val, size); | |
203 | ||
a64d325d | 204 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
205 | } |
206 | ||
28e02042 | 207 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
208 | uint32_t token, uint32_t nargs, |
209 | target_ulong args, | |
210 | uint32_t nret, target_ulong rets) | |
211 | { | |
92615a5a | 212 | uint64_t buid; |
3384f95c | 213 | uint32_t val, size, addr; |
3384f95c | 214 | |
92615a5a | 215 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 216 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
217 | return; |
218 | } | |
92615a5a | 219 | |
a14aa92b | 220 | buid = rtas_ldq(args, 1); |
3384f95c DG |
221 | val = rtas_ld(args, 4); |
222 | size = rtas_ld(args, 3); | |
92615a5a DG |
223 | addr = rtas_ld(args, 0); |
224 | ||
225 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
226 | } |
227 | ||
28e02042 | 228 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
229 | uint32_t token, uint32_t nargs, |
230 | target_ulong args, | |
231 | uint32_t nret, target_ulong rets) | |
232 | { | |
233 | uint32_t val, size, addr; | |
3384f95c | 234 | |
92615a5a | 235 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 236 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
237 | return; |
238 | } | |
92615a5a DG |
239 | |
240 | ||
3384f95c DG |
241 | val = rtas_ld(args, 2); |
242 | size = rtas_ld(args, 1); | |
92615a5a DG |
243 | addr = rtas_ld(args, 0); |
244 | ||
245 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
246 | } |
247 | ||
0ee2c058 AK |
248 | /* |
249 | * Set MSI/MSIX message data. | |
250 | * This is required for msi_notify()/msix_notify() which | |
251 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
252 | * |
253 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
254 | * table will be reset. | |
0ee2c058 | 255 | */ |
f1c2dc7c AK |
256 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
257 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
258 | { |
259 | unsigned i; | |
f1c2dc7c | 260 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
261 | |
262 | if (!msix) { | |
263 | msi_set_message(pdev, msg); | |
264 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
265 | return; | |
266 | } | |
267 | ||
9a321e92 | 268 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
269 | msix_set_message(pdev, i, msg); |
270 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
271 | if (addr) { |
272 | ++msg.data; | |
273 | } | |
0ee2c058 AK |
274 | } |
275 | } | |
276 | ||
28e02042 | 277 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
0ee2c058 AK |
278 | uint32_t token, uint32_t nargs, |
279 | target_ulong args, uint32_t nret, | |
280 | target_ulong rets) | |
281 | { | |
282 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 283 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 AK |
284 | unsigned int func = rtas_ld(args, 3); |
285 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
286 | unsigned int seq_num = rtas_ld(args, 5); | |
287 | unsigned int ret_intr_type; | |
d4a63ac8 | 288 | unsigned int irq, max_irqs = 0; |
0ee2c058 AK |
289 | sPAPRPHBState *phb = NULL; |
290 | PCIDevice *pdev = NULL; | |
9a321e92 AK |
291 | spapr_pci_msi *msi; |
292 | int *config_addr_key; | |
a005b3ef | 293 | Error *err = NULL; |
0ee2c058 AK |
294 | |
295 | switch (func) { | |
296 | case RTAS_CHANGE_MSI_FN: | |
297 | case RTAS_CHANGE_FN: | |
298 | ret_intr_type = RTAS_TYPE_MSI; | |
299 | break; | |
300 | case RTAS_CHANGE_MSIX_FN: | |
301 | ret_intr_type = RTAS_TYPE_MSIX; | |
302 | break; | |
303 | default: | |
295d51aa | 304 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 305 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
306 | return; |
307 | } | |
308 | ||
309 | /* Fins sPAPRPHBState */ | |
46c5874e | 310 | phb = spapr_pci_find_phb(spapr, buid); |
0ee2c058 | 311 | if (phb) { |
46c5874e | 312 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
0ee2c058 AK |
313 | } |
314 | if (!phb || !pdev) { | |
a64d325d | 315 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
316 | return; |
317 | } | |
318 | ||
ce266b75 GK |
319 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
320 | ||
0ee2c058 AK |
321 | /* Releasing MSIs */ |
322 | if (!req_num) { | |
9a321e92 AK |
323 | if (!msi) { |
324 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 325 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
326 | return; |
327 | } | |
9a321e92 | 328 | |
681bfade | 329 | spapr_ics_free(spapr->ics, msi->first_irq, msi->num); |
32420522 | 330 | if (msi_present(pdev)) { |
d4a63ac8 | 331 | spapr_msi_setmsg(pdev, 0, false, 0, 0); |
32420522 AK |
332 | } |
333 | if (msix_present(pdev)) { | |
d4a63ac8 | 334 | spapr_msi_setmsg(pdev, 0, true, 0, 0); |
32420522 | 335 | } |
9a321e92 AK |
336 | g_hash_table_remove(phb->msi, &config_addr); |
337 | ||
338 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 339 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
340 | rtas_st(rets, 1, 0); |
341 | return; | |
342 | } | |
343 | ||
344 | /* Enabling MSI */ | |
345 | ||
28668b5f AK |
346 | /* Check if the device supports as many IRQs as requested */ |
347 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
348 | max_irqs = msi_nr_vectors_allocated(pdev); | |
349 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
350 | max_irqs = pdev->msix_entries_nr; | |
351 | } | |
352 | if (!max_irqs) { | |
9a321e92 AK |
353 | error_report("Requested interrupt type %d is not enabled for device %x", |
354 | ret_intr_type, config_addr); | |
28668b5f AK |
355 | rtas_st(rets, 0, -1); /* Hardware error */ |
356 | return; | |
357 | } | |
358 | /* Correct the number if the guest asked for too many */ | |
359 | if (req_num > max_irqs) { | |
9a321e92 | 360 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 361 | req_num = max_irqs; |
9a321e92 AK |
362 | irq = 0; /* to avoid misleading trace */ |
363 | goto out; | |
28668b5f AK |
364 | } |
365 | ||
9a321e92 | 366 | /* Allocate MSIs */ |
681bfade | 367 | irq = spapr_ics_alloc_block(spapr->ics, req_num, false, |
a005b3ef GK |
368 | ret_intr_type == RTAS_TYPE_MSI, &err); |
369 | if (err) { | |
370 | error_reportf_err(err, "Can't allocate MSIs for device %x: ", | |
371 | config_addr); | |
a64d325d | 372 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
373 | return; |
374 | } | |
375 | ||
ce266b75 GK |
376 | /* Release previous MSIs */ |
377 | if (msi) { | |
681bfade | 378 | spapr_ics_free(spapr->ics, msi->first_irq, msi->num); |
ce266b75 GK |
379 | g_hash_table_remove(phb->msi, &config_addr); |
380 | } | |
381 | ||
0ee2c058 | 382 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 383 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 384 | irq, req_num); |
0ee2c058 | 385 | |
9a321e92 AK |
386 | /* Add MSI device to cache */ |
387 | msi = g_new(spapr_pci_msi, 1); | |
388 | msi->first_irq = irq; | |
389 | msi->num = req_num; | |
390 | config_addr_key = g_new(int, 1); | |
391 | *config_addr_key = config_addr; | |
392 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
393 | ||
394 | out: | |
a64d325d | 395 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
396 | rtas_st(rets, 1, req_num); |
397 | rtas_st(rets, 2, ++seq_num); | |
b359bd6a SB |
398 | if (nret > 3) { |
399 | rtas_st(rets, 3, ret_intr_type); | |
400 | } | |
0ee2c058 | 401 | |
9a321e92 | 402 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
403 | } |
404 | ||
210b580b | 405 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
28e02042 | 406 | sPAPRMachineState *spapr, |
0ee2c058 AK |
407 | uint32_t token, |
408 | uint32_t nargs, | |
409 | target_ulong args, | |
410 | uint32_t nret, | |
411 | target_ulong rets) | |
412 | { | |
413 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 414 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 | 415 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); |
0ee2c058 | 416 | sPAPRPHBState *phb = NULL; |
9a321e92 AK |
417 | PCIDevice *pdev = NULL; |
418 | spapr_pci_msi *msi; | |
0ee2c058 | 419 | |
9a321e92 | 420 | /* Find sPAPRPHBState */ |
46c5874e | 421 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 422 | if (phb) { |
46c5874e | 423 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
424 | } |
425 | if (!phb || !pdev) { | |
a64d325d | 426 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
427 | return; |
428 | } | |
429 | ||
430 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
431 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
432 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
433 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 434 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
435 | return; |
436 | } | |
9a321e92 | 437 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
438 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
439 | intr_src_num); | |
440 | ||
a64d325d | 441 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
442 | rtas_st(rets, 1, intr_src_num); |
443 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
444 | } | |
445 | ||
ee954280 | 446 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
28e02042 | 447 | sPAPRMachineState *spapr, |
ee954280 GS |
448 | uint32_t token, uint32_t nargs, |
449 | target_ulong args, uint32_t nret, | |
450 | target_ulong rets) | |
451 | { | |
452 | sPAPRPHBState *sphb; | |
ee954280 GS |
453 | uint32_t addr, option; |
454 | uint64_t buid; | |
455 | int ret; | |
456 | ||
457 | if ((nargs != 4) || (nret != 1)) { | |
458 | goto param_error_exit; | |
459 | } | |
460 | ||
a14aa92b | 461 | buid = rtas_ldq(args, 1); |
ee954280 GS |
462 | addr = rtas_ld(args, 0); |
463 | option = rtas_ld(args, 3); | |
464 | ||
46c5874e | 465 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
466 | if (!sphb) { |
467 | goto param_error_exit; | |
468 | } | |
469 | ||
fbb4e983 | 470 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
471 | goto param_error_exit; |
472 | } | |
473 | ||
fbb4e983 | 474 | ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); |
ee954280 GS |
475 | rtas_st(rets, 0, ret); |
476 | return; | |
477 | ||
478 | param_error_exit: | |
479 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
480 | } | |
481 | ||
482 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
28e02042 | 483 | sPAPRMachineState *spapr, |
ee954280 GS |
484 | uint32_t token, uint32_t nargs, |
485 | target_ulong args, uint32_t nret, | |
486 | target_ulong rets) | |
487 | { | |
488 | sPAPRPHBState *sphb; | |
ee954280 GS |
489 | PCIDevice *pdev; |
490 | uint32_t addr, option; | |
491 | uint64_t buid; | |
492 | ||
493 | if ((nargs != 4) || (nret != 2)) { | |
494 | goto param_error_exit; | |
495 | } | |
496 | ||
a14aa92b | 497 | buid = rtas_ldq(args, 1); |
46c5874e | 498 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
499 | if (!sphb) { |
500 | goto param_error_exit; | |
501 | } | |
502 | ||
fbb4e983 | 503 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
504 | goto param_error_exit; |
505 | } | |
506 | ||
507 | /* | |
508 | * We always have PE address of form "00BB0001". "BB" | |
509 | * represents the bus number of PE's primary bus. | |
510 | */ | |
511 | option = rtas_ld(args, 3); | |
512 | switch (option) { | |
513 | case RTAS_GET_PE_ADDR: | |
514 | addr = rtas_ld(args, 0); | |
46c5874e | 515 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
516 | if (!pdev) { |
517 | goto param_error_exit; | |
518 | } | |
519 | ||
520 | rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); | |
521 | break; | |
522 | case RTAS_GET_PE_MODE: | |
523 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
524 | break; | |
525 | default: | |
526 | goto param_error_exit; | |
527 | } | |
528 | ||
529 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
530 | return; | |
531 | ||
532 | param_error_exit: | |
533 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
534 | } | |
535 | ||
536 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
28e02042 | 537 | sPAPRMachineState *spapr, |
ee954280 GS |
538 | uint32_t token, uint32_t nargs, |
539 | target_ulong args, uint32_t nret, | |
540 | target_ulong rets) | |
541 | { | |
542 | sPAPRPHBState *sphb; | |
ee954280 GS |
543 | uint64_t buid; |
544 | int state, ret; | |
545 | ||
546 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
547 | goto param_error_exit; | |
548 | } | |
549 | ||
a14aa92b | 550 | buid = rtas_ldq(args, 1); |
46c5874e | 551 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
552 | if (!sphb) { |
553 | goto param_error_exit; | |
554 | } | |
555 | ||
fbb4e983 | 556 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
557 | goto param_error_exit; |
558 | } | |
559 | ||
fbb4e983 | 560 | ret = spapr_phb_vfio_eeh_get_state(sphb, &state); |
ee954280 GS |
561 | rtas_st(rets, 0, ret); |
562 | if (ret != RTAS_OUT_SUCCESS) { | |
563 | return; | |
564 | } | |
565 | ||
566 | rtas_st(rets, 1, state); | |
567 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
568 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
569 | if (nret >= 5) { | |
570 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
571 | } | |
572 | return; | |
573 | ||
574 | param_error_exit: | |
575 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
576 | } | |
577 | ||
578 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
28e02042 | 579 | sPAPRMachineState *spapr, |
ee954280 GS |
580 | uint32_t token, uint32_t nargs, |
581 | target_ulong args, uint32_t nret, | |
582 | target_ulong rets) | |
583 | { | |
584 | sPAPRPHBState *sphb; | |
ee954280 GS |
585 | uint32_t option; |
586 | uint64_t buid; | |
587 | int ret; | |
588 | ||
589 | if ((nargs != 4) || (nret != 1)) { | |
590 | goto param_error_exit; | |
591 | } | |
592 | ||
a14aa92b | 593 | buid = rtas_ldq(args, 1); |
ee954280 | 594 | option = rtas_ld(args, 3); |
46c5874e | 595 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
596 | if (!sphb) { |
597 | goto param_error_exit; | |
598 | } | |
599 | ||
fbb4e983 | 600 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
601 | goto param_error_exit; |
602 | } | |
603 | ||
fbb4e983 | 604 | ret = spapr_phb_vfio_eeh_reset(sphb, option); |
ee954280 GS |
605 | rtas_st(rets, 0, ret); |
606 | return; | |
607 | ||
608 | param_error_exit: | |
609 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
610 | } | |
611 | ||
612 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
28e02042 | 613 | sPAPRMachineState *spapr, |
ee954280 GS |
614 | uint32_t token, uint32_t nargs, |
615 | target_ulong args, uint32_t nret, | |
616 | target_ulong rets) | |
617 | { | |
618 | sPAPRPHBState *sphb; | |
ee954280 GS |
619 | uint64_t buid; |
620 | int ret; | |
621 | ||
622 | if ((nargs != 3) || (nret != 1)) { | |
623 | goto param_error_exit; | |
624 | } | |
625 | ||
a14aa92b | 626 | buid = rtas_ldq(args, 1); |
46c5874e | 627 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
628 | if (!sphb) { |
629 | goto param_error_exit; | |
630 | } | |
631 | ||
fbb4e983 | 632 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
633 | goto param_error_exit; |
634 | } | |
635 | ||
fbb4e983 | 636 | ret = spapr_phb_vfio_eeh_configure(sphb); |
ee954280 GS |
637 | rtas_st(rets, 0, ret); |
638 | return; | |
639 | ||
640 | param_error_exit: | |
641 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
642 | } | |
643 | ||
644 | /* To support it later */ | |
645 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
28e02042 | 646 | sPAPRMachineState *spapr, |
ee954280 GS |
647 | uint32_t token, uint32_t nargs, |
648 | target_ulong args, uint32_t nret, | |
649 | target_ulong rets) | |
650 | { | |
651 | sPAPRPHBState *sphb; | |
ee954280 GS |
652 | int option; |
653 | uint64_t buid; | |
654 | ||
655 | if ((nargs != 8) || (nret != 1)) { | |
656 | goto param_error_exit; | |
657 | } | |
658 | ||
a14aa92b | 659 | buid = rtas_ldq(args, 1); |
46c5874e | 660 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
661 | if (!sphb) { |
662 | goto param_error_exit; | |
663 | } | |
664 | ||
fbb4e983 | 665 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
666 | goto param_error_exit; |
667 | } | |
668 | ||
669 | option = rtas_ld(args, 7); | |
670 | switch (option) { | |
671 | case RTAS_SLOT_TEMP_ERR_LOG: | |
672 | case RTAS_SLOT_PERM_ERR_LOG: | |
673 | break; | |
674 | default: | |
675 | goto param_error_exit; | |
676 | } | |
677 | ||
678 | /* We don't have error log yet */ | |
679 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
680 | return; | |
681 | ||
682 | param_error_exit: | |
683 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
684 | } | |
685 | ||
7fb0bd34 DG |
686 | static int pci_spapr_swizzle(int slot, int pin) |
687 | { | |
688 | return (slot + pin) % PCI_NUM_PINS; | |
689 | } | |
690 | ||
3384f95c DG |
691 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
692 | { | |
693 | /* | |
694 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
695 | * which is less than number of IRQs on the specific bus (4). We |
696 | * use standard PCI swizzling, that is (slot number + pin number) | |
697 | * % 4. | |
3384f95c | 698 | */ |
7fb0bd34 | 699 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
700 | } |
701 | ||
702 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
703 | { | |
704 | /* | |
705 | * Here we use the number returned by pci_spapr_map_irq to find a | |
706 | * corresponding qemu_irq. | |
707 | */ | |
708 | sPAPRPHBState *phb = opaque; | |
709 | ||
caae58cb | 710 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 711 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
712 | } |
713 | ||
5cc7a967 AK |
714 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
715 | { | |
716 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); | |
717 | PCIINTxRoute route; | |
718 | ||
719 | route.mode = PCI_INTX_ENABLED; | |
720 | route.irq = sphb->lsi_table[pin].irq; | |
721 | ||
722 | return route; | |
723 | } | |
724 | ||
0ee2c058 AK |
725 | /* |
726 | * MSI/MSIX memory region implementation. | |
727 | * The handler handles both MSI and MSIX. | |
728 | * For MSI-X, the vector number is encoded as a part of the address, | |
729 | * data is set to 0. | |
730 | * For MSI, the vector number is encoded in least bits in data. | |
731 | */ | |
a8170e5e | 732 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
733 | uint64_t data, unsigned size) |
734 | { | |
28e02042 | 735 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
f1c2dc7c | 736 | uint32_t irq = data; |
0ee2c058 AK |
737 | |
738 | trace_spapr_pci_msi_write(addr, data, irq); | |
739 | ||
27f24582 | 740 | qemu_irq_pulse(xics_get_qirq(spapr->xics, irq)); |
0ee2c058 AK |
741 | } |
742 | ||
743 | static const MemoryRegionOps spapr_msi_ops = { | |
744 | /* There is no .read as the read result is undefined by PCI spec */ | |
745 | .read = NULL, | |
746 | .write = spapr_msi_write, | |
747 | .endianness = DEVICE_LITTLE_ENDIAN | |
748 | }; | |
749 | ||
298a9710 DG |
750 | /* |
751 | * PHB PCI device | |
752 | */ | |
e00387d5 | 753 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
754 | { |
755 | sPAPRPHBState *phb = opaque; | |
756 | ||
e00387d5 | 757 | return &phb->iommu_as; |
edded454 DG |
758 | } |
759 | ||
16b0ea1d ND |
760 | static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) |
761 | { | |
762 | char *path = NULL, *buf = NULL, *host = NULL; | |
763 | ||
764 | /* Get the PCI VFIO host id */ | |
765 | host = object_property_get_str(OBJECT(pdev), "host", NULL); | |
766 | if (!host) { | |
767 | goto err_out; | |
768 | } | |
769 | ||
770 | /* Construct the path of the file that will give us the DT location */ | |
771 | path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); | |
772 | g_free(host); | |
773 | if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { | |
774 | goto err_out; | |
775 | } | |
776 | g_free(path); | |
777 | ||
778 | /* Construct and read from host device tree the loc-code */ | |
779 | path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); | |
780 | g_free(buf); | |
781 | if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { | |
782 | goto err_out; | |
783 | } | |
784 | return buf; | |
785 | ||
786 | err_out: | |
787 | g_free(path); | |
788 | return NULL; | |
789 | } | |
790 | ||
791 | static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) | |
792 | { | |
793 | char *buf; | |
794 | const char *devtype = "qemu"; | |
795 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
796 | ||
797 | if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
798 | buf = spapr_phb_vfio_get_loc_code(sphb, pdev); | |
799 | if (buf) { | |
800 | return buf; | |
801 | } | |
802 | devtype = "vfio"; | |
803 | } | |
804 | /* | |
805 | * For emulated devices and VFIO-failure case, make up | |
806 | * the loc-code. | |
807 | */ | |
808 | buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", | |
809 | devtype, pdev->name, sphb->index, busnr, | |
810 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
811 | return buf; | |
812 | } | |
813 | ||
7454c7af MR |
814 | /* Macros to operate with address in OF binding to PCI */ |
815 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
816 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
817 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
818 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
819 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
820 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
821 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
822 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
823 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
824 | ||
825 | /* for 'reg'/'assigned-addresses' OF properties */ | |
826 | #define RESOURCE_CELLS_SIZE 2 | |
827 | #define RESOURCE_CELLS_ADDRESS 3 | |
828 | ||
829 | typedef struct ResourceFields { | |
830 | uint32_t phys_hi; | |
831 | uint32_t phys_mid; | |
832 | uint32_t phys_lo; | |
833 | uint32_t size_hi; | |
834 | uint32_t size_lo; | |
835 | } QEMU_PACKED ResourceFields; | |
836 | ||
837 | typedef struct ResourceProps { | |
838 | ResourceFields reg[8]; | |
839 | ResourceFields assigned[7]; | |
840 | uint32_t reg_len; | |
841 | uint32_t assigned_len; | |
842 | } ResourceProps; | |
843 | ||
844 | /* fill in the 'reg'/'assigned-resources' OF properties for | |
845 | * a PCI device. 'reg' describes resource requirements for a | |
846 | * device's IO/MEM regions, 'assigned-addresses' describes the | |
847 | * actual resource assignments. | |
848 | * | |
849 | * the properties are arrays of ('phys-addr', 'size') pairs describing | |
850 | * the addressable regions of the PCI device, where 'phys-addr' is a | |
851 | * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to | |
852 | * (phys.hi, phys.mid, phys.lo), and 'size' is a | |
853 | * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). | |
854 | * | |
855 | * phys.hi = 0xYYXXXXZZ, where: | |
856 | * 0xYY = npt000ss | |
857 | * ||| | | |
72187935 ND |
858 | * ||| +-- space code |
859 | * ||| | | |
860 | * ||| + 00 if configuration space | |
861 | * ||| + 01 if IO region, | |
862 | * ||| + 10 if 32-bit MEM region | |
863 | * ||| + 11 if 64-bit MEM region | |
864 | * ||| | |
7454c7af MR |
865 | * ||+------ for non-relocatable IO: 1 if aliased |
866 | * || for relocatable IO: 1 if below 64KB | |
867 | * || for MEM: 1 if below 1MB | |
868 | * |+------- 1 if region is prefetchable | |
869 | * +-------- 1 if region is non-relocatable | |
870 | * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function | |
871 | * bits respectively | |
872 | * 0xZZ = rrrrrrrr, the register number of the BAR corresponding | |
873 | * to the region | |
874 | * | |
875 | * phys.mid and phys.lo correspond respectively to the hi/lo portions | |
876 | * of the actual address of the region. | |
877 | * | |
878 | * how the phys-addr/size values are used differ slightly between | |
879 | * 'reg' and 'assigned-addresses' properties. namely, 'reg' has | |
880 | * an additional description for the config space region of the | |
881 | * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 | |
882 | * to describe the region as relocatable, with an address-mapping | |
883 | * that corresponds directly to the PHB's address space for the | |
884 | * resource. 'assigned-addresses' always has n=1 set with an absolute | |
885 | * address assigned for the resource. in general, 'assigned-addresses' | |
886 | * won't be populated, since addresses for PCI devices are generally | |
887 | * unmapped initially and left to the guest to assign. | |
888 | * | |
889 | * note also that addresses defined in these properties are, at least | |
890 | * for PAPR guests, relative to the PHBs IO/MEM windows, and | |
891 | * correspond directly to the addresses in the BARs. | |
892 | * | |
893 | * in accordance with PCI Bus Binding to Open Firmware, | |
894 | * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, | |
895 | * Appendix C. | |
896 | */ | |
897 | static void populate_resource_props(PCIDevice *d, ResourceProps *rp) | |
898 | { | |
899 | int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); | |
900 | uint32_t dev_id = (b_bbbbbbbb(bus_num) | | |
901 | b_ddddd(PCI_SLOT(d->devfn)) | | |
902 | b_fff(PCI_FUNC(d->devfn))); | |
903 | ResourceFields *reg, *assigned; | |
904 | int i, reg_idx = 0, assigned_idx = 0; | |
905 | ||
906 | /* config space region */ | |
907 | reg = &rp->reg[reg_idx++]; | |
908 | reg->phys_hi = cpu_to_be32(dev_id); | |
909 | reg->phys_mid = 0; | |
910 | reg->phys_lo = 0; | |
911 | reg->size_hi = 0; | |
912 | reg->size_lo = 0; | |
913 | ||
914 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
915 | if (!d->io_regions[i].size) { | |
916 | continue; | |
917 | } | |
918 | ||
919 | reg = &rp->reg[reg_idx++]; | |
920 | ||
921 | reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); | |
922 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
923 | reg->phys_hi |= cpu_to_be32(b_ss(1)); | |
72187935 ND |
924 | } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
925 | reg->phys_hi |= cpu_to_be32(b_ss(3)); | |
7454c7af MR |
926 | } else { |
927 | reg->phys_hi |= cpu_to_be32(b_ss(2)); | |
928 | } | |
929 | reg->phys_mid = 0; | |
930 | reg->phys_lo = 0; | |
931 | reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); | |
932 | reg->size_lo = cpu_to_be32(d->io_regions[i].size); | |
933 | ||
934 | if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { | |
935 | continue; | |
936 | } | |
937 | ||
938 | assigned = &rp->assigned[assigned_idx++]; | |
939 | assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); | |
940 | assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); | |
941 | assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); | |
942 | assigned->size_hi = reg->size_hi; | |
943 | assigned->size_lo = reg->size_lo; | |
944 | } | |
945 | ||
946 | rp->reg_len = reg_idx * sizeof(ResourceFields); | |
947 | rp->assigned_len = assigned_idx * sizeof(ResourceFields); | |
948 | } | |
949 | ||
2530a1a5 LV |
950 | typedef struct PCIClass PCIClass; |
951 | typedef struct PCISubClass PCISubClass; | |
952 | typedef struct PCIIFace PCIIFace; | |
953 | ||
954 | struct PCIIFace { | |
955 | int iface; | |
956 | const char *name; | |
957 | }; | |
958 | ||
959 | struct PCISubClass { | |
960 | int subclass; | |
961 | const char *name; | |
962 | const PCIIFace *iface; | |
963 | }; | |
964 | ||
965 | struct PCIClass { | |
966 | const char *name; | |
967 | const PCISubClass *subc; | |
968 | }; | |
969 | ||
970 | static const PCISubClass undef_subclass[] = { | |
971 | { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, | |
972 | { 0xFF, NULL, NULL }, | |
973 | }; | |
974 | ||
975 | static const PCISubClass mass_subclass[] = { | |
976 | { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, | |
977 | { PCI_CLASS_STORAGE_IDE, "ide", NULL }, | |
978 | { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, | |
979 | { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, | |
980 | { PCI_CLASS_STORAGE_RAID, "raid", NULL }, | |
981 | { PCI_CLASS_STORAGE_ATA, "ata", NULL }, | |
982 | { PCI_CLASS_STORAGE_SATA, "sata", NULL }, | |
983 | { PCI_CLASS_STORAGE_SAS, "sas", NULL }, | |
984 | { 0xFF, NULL, NULL }, | |
985 | }; | |
986 | ||
987 | static const PCISubClass net_subclass[] = { | |
988 | { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, | |
989 | { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, | |
990 | { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, | |
991 | { PCI_CLASS_NETWORK_ATM, "atm", NULL }, | |
992 | { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, | |
993 | { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, | |
994 | { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, | |
995 | { 0xFF, NULL, NULL }, | |
996 | }; | |
997 | ||
998 | static const PCISubClass displ_subclass[] = { | |
999 | { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, | |
1000 | { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, | |
1001 | { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, | |
1002 | { 0xFF, NULL, NULL }, | |
1003 | }; | |
1004 | ||
1005 | static const PCISubClass media_subclass[] = { | |
1006 | { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, | |
1007 | { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, | |
1008 | { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, | |
1009 | { 0xFF, NULL, NULL }, | |
1010 | }; | |
1011 | ||
1012 | static const PCISubClass mem_subclass[] = { | |
1013 | { PCI_CLASS_MEMORY_RAM, "memory", NULL }, | |
1014 | { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, | |
1015 | { 0xFF, NULL, NULL }, | |
1016 | }; | |
1017 | ||
1018 | static const PCISubClass bridg_subclass[] = { | |
1019 | { PCI_CLASS_BRIDGE_HOST, "host", NULL }, | |
1020 | { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, | |
1021 | { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, | |
1022 | { PCI_CLASS_BRIDGE_MC, "mca", NULL }, | |
1023 | { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, | |
1024 | { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, | |
1025 | { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, | |
1026 | { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, | |
1027 | { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, | |
1028 | { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, | |
1029 | { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, | |
1030 | { 0xFF, NULL, NULL }, | |
1031 | }; | |
1032 | ||
1033 | static const PCISubClass comm_subclass[] = { | |
1034 | { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, | |
1035 | { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, | |
1036 | { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, | |
1037 | { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, | |
1038 | { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, | |
1039 | { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, | |
1040 | { 0xFF, NULL, NULL, }, | |
1041 | }; | |
1042 | ||
1043 | static const PCIIFace pic_iface[] = { | |
1044 | { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, | |
1045 | { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, | |
1046 | { 0xFF, NULL }, | |
1047 | }; | |
1048 | ||
1049 | static const PCISubClass sys_subclass[] = { | |
1050 | { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, | |
1051 | { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, | |
1052 | { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, | |
1053 | { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, | |
1054 | { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, | |
1055 | { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, | |
1056 | { 0xFF, NULL, NULL }, | |
1057 | }; | |
1058 | ||
1059 | static const PCISubClass inp_subclass[] = { | |
1060 | { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, | |
1061 | { PCI_CLASS_INPUT_PEN, "pen", NULL }, | |
1062 | { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, | |
1063 | { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, | |
1064 | { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, | |
1065 | { 0xFF, NULL, NULL }, | |
1066 | }; | |
1067 | ||
1068 | static const PCISubClass dock_subclass[] = { | |
1069 | { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, | |
1070 | { 0xFF, NULL, NULL }, | |
1071 | }; | |
1072 | ||
1073 | static const PCISubClass cpu_subclass[] = { | |
1074 | { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, | |
1075 | { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, | |
1076 | { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, | |
1077 | { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, | |
1078 | { 0xFF, NULL, NULL }, | |
1079 | }; | |
1080 | ||
1081 | static const PCIIFace usb_iface[] = { | |
1082 | { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, | |
1083 | { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, | |
1084 | { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, | |
1085 | { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, | |
1086 | { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, | |
1087 | { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, | |
1088 | { 0xFF, NULL }, | |
1089 | }; | |
1090 | ||
1091 | static const PCISubClass ser_subclass[] = { | |
1092 | { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, | |
1093 | { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, | |
1094 | { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, | |
1095 | { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, | |
1096 | { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, | |
1097 | { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, | |
1098 | { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, | |
1099 | { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, | |
1100 | { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, | |
1101 | { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, | |
1102 | { 0xFF, NULL, NULL }, | |
1103 | }; | |
1104 | ||
1105 | static const PCISubClass wrl_subclass[] = { | |
1106 | { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, | |
1107 | { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, | |
1108 | { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, | |
1109 | { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, | |
1110 | { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, | |
1111 | { 0xFF, NULL, NULL }, | |
1112 | }; | |
1113 | ||
1114 | static const PCISubClass sat_subclass[] = { | |
1115 | { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, | |
1116 | { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, | |
1117 | { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, | |
1118 | { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, | |
1119 | { 0xFF, NULL, NULL }, | |
1120 | }; | |
1121 | ||
1122 | static const PCISubClass crypt_subclass[] = { | |
1123 | { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, | |
1124 | { PCI_CLASS_CRYPT_ENTERTAINMENT, | |
1125 | "entertainment-encryption", NULL }, | |
1126 | { 0xFF, NULL, NULL }, | |
1127 | }; | |
1128 | ||
1129 | static const PCISubClass spc_subclass[] = { | |
1130 | { PCI_CLASS_SP_DPIO, "dpio", NULL }, | |
1131 | { PCI_CLASS_SP_PERF, "counter", NULL }, | |
1132 | { PCI_CLASS_SP_SYNCH, "measurement", NULL }, | |
1133 | { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, | |
1134 | { 0xFF, NULL, NULL }, | |
1135 | }; | |
1136 | ||
1137 | static const PCIClass pci_classes[] = { | |
1138 | { "legacy-device", undef_subclass }, | |
1139 | { "mass-storage", mass_subclass }, | |
1140 | { "network", net_subclass }, | |
1141 | { "display", displ_subclass, }, | |
1142 | { "multimedia-device", media_subclass }, | |
1143 | { "memory-controller", mem_subclass }, | |
1144 | { "unknown-bridge", bridg_subclass }, | |
1145 | { "communication-controller", comm_subclass}, | |
1146 | { "system-peripheral", sys_subclass }, | |
1147 | { "input-controller", inp_subclass }, | |
1148 | { "docking-station", dock_subclass }, | |
1149 | { "cpu", cpu_subclass }, | |
1150 | { "serial-bus", ser_subclass }, | |
1151 | { "wireless-controller", wrl_subclass }, | |
1152 | { "intelligent-io", NULL }, | |
1153 | { "satellite-device", sat_subclass }, | |
1154 | { "encryption", crypt_subclass }, | |
1155 | { "data-processing-controller", spc_subclass }, | |
1156 | }; | |
1157 | ||
1158 | static const char *pci_find_device_name(uint8_t class, uint8_t subclass, | |
1159 | uint8_t iface) | |
1160 | { | |
1161 | const PCIClass *pclass; | |
1162 | const PCISubClass *psubclass; | |
1163 | const PCIIFace *piface; | |
1164 | const char *name; | |
1165 | ||
1166 | if (class >= ARRAY_SIZE(pci_classes)) { | |
1167 | return "pci"; | |
1168 | } | |
1169 | ||
1170 | pclass = pci_classes + class; | |
1171 | name = pclass->name; | |
1172 | ||
1173 | if (pclass->subc == NULL) { | |
1174 | return name; | |
1175 | } | |
1176 | ||
1177 | psubclass = pclass->subc; | |
1178 | while ((psubclass->subclass & 0xff) != 0xff) { | |
1179 | if ((psubclass->subclass & 0xff) == subclass) { | |
1180 | name = psubclass->name; | |
1181 | break; | |
1182 | } | |
1183 | psubclass++; | |
1184 | } | |
1185 | ||
1186 | piface = psubclass->iface; | |
1187 | if (piface == NULL) { | |
1188 | return name; | |
1189 | } | |
1190 | while ((piface->iface & 0xff) != 0xff) { | |
1191 | if ((piface->iface & 0xff) == iface) { | |
1192 | name = piface->name; | |
1193 | break; | |
1194 | } | |
1195 | piface++; | |
1196 | } | |
1197 | ||
1198 | return name; | |
1199 | } | |
1200 | ||
1201 | static void pci_get_node_name(char *nodename, int len, PCIDevice *dev) | |
1202 | { | |
1203 | int slot = PCI_SLOT(dev->devfn); | |
1204 | int func = PCI_FUNC(dev->devfn); | |
1205 | uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); | |
1206 | const char *name; | |
1207 | ||
1208 | name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, | |
1209 | ccode & 0xff); | |
1210 | ||
1211 | if (func != 0) { | |
1212 | snprintf(nodename, len, "%s@%x,%x", name, slot, func); | |
1213 | } else { | |
1214 | snprintf(nodename, len, "%s@%x", name, slot); | |
1215 | } | |
1216 | } | |
1217 | ||
e634b89c ND |
1218 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
1219 | PCIDevice *pdev); | |
1220 | ||
7454c7af | 1221 | static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, |
16b0ea1d | 1222 | sPAPRPHBState *sphb) |
7454c7af MR |
1223 | { |
1224 | ResourceProps rp; | |
1225 | bool is_bridge = false; | |
16b0ea1d ND |
1226 | int pci_status, err; |
1227 | char *buf = NULL; | |
e634b89c | 1228 | uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); |
2530a1a5 | 1229 | uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); |
a8ad731a | 1230 | uint32_t max_msi, max_msix; |
7454c7af MR |
1231 | |
1232 | if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == | |
1233 | PCI_HEADER_TYPE_BRIDGE) { | |
1234 | is_bridge = true; | |
1235 | } | |
1236 | ||
1237 | /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ | |
1238 | _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", | |
1239 | pci_default_read_config(dev, PCI_VENDOR_ID, 2))); | |
1240 | _FDT(fdt_setprop_cell(fdt, offset, "device-id", | |
1241 | pci_default_read_config(dev, PCI_DEVICE_ID, 2))); | |
1242 | _FDT(fdt_setprop_cell(fdt, offset, "revision-id", | |
1243 | pci_default_read_config(dev, PCI_REVISION_ID, 1))); | |
2530a1a5 | 1244 | _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); |
7454c7af MR |
1245 | if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { |
1246 | _FDT(fdt_setprop_cell(fdt, offset, "interrupts", | |
1247 | pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); | |
1248 | } | |
1249 | ||
1250 | if (!is_bridge) { | |
1251 | _FDT(fdt_setprop_cell(fdt, offset, "min-grant", | |
1252 | pci_default_read_config(dev, PCI_MIN_GNT, 1))); | |
1253 | _FDT(fdt_setprop_cell(fdt, offset, "max-latency", | |
1254 | pci_default_read_config(dev, PCI_MAX_LAT, 1))); | |
1255 | } | |
1256 | ||
1257 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { | |
1258 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", | |
1259 | pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); | |
1260 | } | |
1261 | ||
1262 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { | |
1263 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", | |
1264 | pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); | |
1265 | } | |
1266 | ||
1267 | _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", | |
1268 | pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); | |
1269 | ||
1270 | /* the following fdt cells are masked off the pci status register */ | |
1271 | pci_status = pci_default_read_config(dev, PCI_STATUS, 2); | |
1272 | _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", | |
1273 | PCI_STATUS_DEVSEL_MASK & pci_status)); | |
1274 | ||
1275 | if (pci_status & PCI_STATUS_FAST_BACK) { | |
1276 | _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); | |
1277 | } | |
1278 | if (pci_status & PCI_STATUS_66MHZ) { | |
1279 | _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); | |
1280 | } | |
1281 | if (pci_status & PCI_STATUS_UDF) { | |
1282 | _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); | |
1283 | } | |
1284 | ||
2530a1a5 LV |
1285 | _FDT(fdt_setprop_string(fdt, offset, "name", |
1286 | pci_find_device_name((ccode >> 16) & 0xff, | |
1287 | (ccode >> 8) & 0xff, | |
1288 | ccode & 0xff))); | |
16b0ea1d ND |
1289 | buf = spapr_phb_get_loc_code(sphb, dev); |
1290 | if (!buf) { | |
1291 | error_report("Failed setting the ibm,loc-code"); | |
1292 | return -1; | |
1293 | } | |
1294 | ||
1295 | err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); | |
1296 | g_free(buf); | |
1297 | if (err < 0) { | |
1298 | return err; | |
1299 | } | |
1300 | ||
e634b89c ND |
1301 | if (drc_index) { |
1302 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); | |
1303 | } | |
7454c7af MR |
1304 | |
1305 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", | |
1306 | RESOURCE_CELLS_ADDRESS)); | |
1307 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", | |
1308 | RESOURCE_CELLS_SIZE)); | |
a8ad731a MR |
1309 | |
1310 | max_msi = msi_nr_vectors_allocated(dev); | |
1311 | if (max_msi) { | |
1312 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); | |
1313 | } | |
1314 | max_msix = dev->msix_entries_nr; | |
1315 | if (max_msix) { | |
1316 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); | |
1317 | } | |
7454c7af MR |
1318 | |
1319 | populate_resource_props(dev, &rp); | |
1320 | _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); | |
1321 | _FDT(fdt_setprop(fdt, offset, "assigned-addresses", | |
1322 | (uint8_t *)rp.assigned, rp.assigned_len)); | |
1323 | ||
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | /* create OF node for pci device and required OF DT properties */ | |
1d2d9742 | 1328 | static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, |
1d2d9742 | 1329 | void *fdt, int node_offset) |
7454c7af | 1330 | { |
1d2d9742 | 1331 | int offset, ret; |
9b7d9284 | 1332 | char nodename[FDT_NAME_MAX]; |
7454c7af | 1333 | |
2530a1a5 | 1334 | pci_get_node_name(nodename, FDT_NAME_MAX, dev); |
1d2d9742 | 1335 | offset = fdt_add_subnode(fdt, node_offset, nodename); |
e634b89c ND |
1336 | ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); |
1337 | ||
7454c7af | 1338 | g_assert(!ret); |
1d2d9742 ND |
1339 | if (ret) { |
1340 | return 0; | |
1341 | } | |
1342 | return offset; | |
7454c7af MR |
1343 | } |
1344 | ||
1345 | static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, | |
1346 | sPAPRPHBState *phb, | |
1347 | PCIDevice *pdev, | |
1348 | Error **errp) | |
1349 | { | |
1350 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1351 | DeviceState *dev = DEVICE(pdev); | |
7454c7af | 1352 | void *fdt = NULL; |
1d2d9742 | 1353 | int fdt_start_offset = 0, fdt_size; |
7454c7af | 1354 | |
5dd5238c JD |
1355 | fdt = create_device_tree(&fdt_size); |
1356 | fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); | |
1357 | if (!fdt_start_offset) { | |
1358 | error_setg(errp, "Failed to create pci child device tree node"); | |
1359 | goto out; | |
7454c7af MR |
1360 | } |
1361 | ||
1362 | drck->attach(drc, DEVICE(pdev), | |
1363 | fdt, fdt_start_offset, !dev->hotplugged, errp); | |
1d2d9742 | 1364 | out: |
7454c7af MR |
1365 | if (*errp) { |
1366 | g_free(fdt); | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) | |
1371 | { | |
1372 | /* some version guests do not wait for completion of a device | |
1373 | * cleanup (generally done asynchronously by the kernel) before | |
1374 | * signaling to QEMU that the device is safe, but instead sleep | |
1375 | * for some 'safe' period of time. unfortunately on a busy host | |
1376 | * this sleep isn't guaranteed to be long enough, resulting in | |
1377 | * bad things like IRQ lines being left asserted during final | |
1378 | * device removal. to deal with this we call reset just prior | |
1379 | * to finalizing the device, which will put the device back into | |
1380 | * an 'idle' state, as the device cleanup code expects. | |
1381 | */ | |
1382 | pci_device_reset(PCI_DEVICE(dev)); | |
1383 | object_unparent(OBJECT(dev)); | |
1384 | } | |
1385 | ||
1386 | static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, | |
1387 | sPAPRPHBState *phb, | |
1388 | PCIDevice *pdev, | |
1389 | Error **errp) | |
1390 | { | |
1391 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1392 | ||
1393 | drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); | |
1394 | } | |
1395 | ||
788d2599 MR |
1396 | static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb, |
1397 | uint32_t busnr, | |
1398 | int32_t devfn) | |
7454c7af | 1399 | { |
7454c7af MR |
1400 | return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, |
1401 | (phb->index << 16) | | |
1402 | (busnr << 8) | | |
788d2599 MR |
1403 | devfn); |
1404 | } | |
1405 | ||
1406 | static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, | |
1407 | PCIDevice *pdev) | |
1408 | { | |
1409 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
1410 | return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn); | |
7454c7af MR |
1411 | } |
1412 | ||
1d2d9742 ND |
1413 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
1414 | PCIDevice *pdev) | |
1415 | { | |
1416 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1417 | sPAPRDRConnectorClass *drck; | |
1418 | ||
1419 | if (!drc) { | |
1420 | return 0; | |
1421 | } | |
1422 | ||
1423 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1424 | return drck->get_index(drc); | |
1425 | } | |
1426 | ||
7454c7af MR |
1427 | static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, |
1428 | DeviceState *plugged_dev, Error **errp) | |
1429 | { | |
1430 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1431 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1432 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1433 | Error *local_err = NULL; | |
788d2599 MR |
1434 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); |
1435 | uint32_t slotnr = PCI_SLOT(pdev->devfn); | |
7454c7af MR |
1436 | |
1437 | /* if DR is disabled we don't need to do anything in the case of | |
1438 | * hotplug or coldplug callbacks | |
1439 | */ | |
1440 | if (!phb->dr_enabled) { | |
1441 | /* if this is a hotplug operation initiated by the user | |
1442 | * we need to let them know it's not enabled | |
1443 | */ | |
1444 | if (plugged_dev->hotplugged) { | |
c6bd8c70 MA |
1445 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1446 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1447 | } |
1448 | return; | |
1449 | } | |
1450 | ||
1451 | g_assert(drc); | |
1452 | ||
788d2599 MR |
1453 | /* Following the QEMU convention used for PCIe multifunction |
1454 | * hotplug, we do not allow functions to be hotplugged to a | |
1455 | * slot that already has function 0 present | |
1456 | */ | |
1457 | if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && | |
1458 | PCI_FUNC(pdev->devfn) != 0) { | |
1459 | error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," | |
1460 | " additional functions can no longer be exposed to guest.", | |
1461 | slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); | |
1462 | return; | |
1463 | } | |
1464 | ||
7454c7af MR |
1465 | spapr_phb_add_pci_device(drc, phb, pdev, &local_err); |
1466 | if (local_err) { | |
1467 | error_propagate(errp, local_err); | |
1468 | return; | |
1469 | } | |
788d2599 MR |
1470 | |
1471 | /* If this is function 0, signal hotplug for all the device functions. | |
1472 | * Otherwise defer sending the hotplug event. | |
1473 | */ | |
1474 | if (plugged_dev->hotplugged && PCI_FUNC(pdev->devfn) == 0) { | |
1475 | int i; | |
1476 | ||
1477 | for (i = 0; i < 8; i++) { | |
1478 | sPAPRDRConnector *func_drc; | |
1479 | sPAPRDRConnectorClass *func_drck; | |
1480 | sPAPRDREntitySense state; | |
1481 | ||
1482 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1483 | PCI_DEVFN(slotnr, i)); | |
1484 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
1485 | func_drck->entity_sense(func_drc, &state); | |
1486 | ||
1487 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { | |
1488 | spapr_hotplug_req_add_by_index(func_drc); | |
1489 | } | |
1490 | } | |
c5bc152b | 1491 | } |
7454c7af MR |
1492 | } |
1493 | ||
1494 | static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, | |
1495 | DeviceState *plugged_dev, Error **errp) | |
1496 | { | |
1497 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1498 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1499 | sPAPRDRConnectorClass *drck; | |
1500 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1501 | Error *local_err = NULL; | |
1502 | ||
1503 | if (!phb->dr_enabled) { | |
c6bd8c70 MA |
1504 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1505 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1506 | return; |
1507 | } | |
1508 | ||
1509 | g_assert(drc); | |
1510 | ||
1511 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1512 | if (!drck->release_pending(drc)) { | |
788d2599 MR |
1513 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); |
1514 | uint32_t slotnr = PCI_SLOT(pdev->devfn); | |
1515 | sPAPRDRConnector *func_drc; | |
1516 | sPAPRDRConnectorClass *func_drck; | |
1517 | sPAPRDREntitySense state; | |
1518 | int i; | |
1519 | ||
1520 | /* ensure any other present functions are pending unplug */ | |
1521 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1522 | for (i = 1; i < 8; i++) { | |
1523 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1524 | PCI_DEVFN(slotnr, i)); | |
1525 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
1526 | func_drck->entity_sense(func_drc, &state); | |
1527 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT | |
1528 | && !func_drck->release_pending(func_drc)) { | |
1529 | error_setg(errp, | |
1530 | "PCI: slot %d, function %d still present. " | |
1531 | "Must unplug all non-0 functions first.", | |
1532 | slotnr, i); | |
1533 | return; | |
1534 | } | |
1535 | } | |
1536 | } | |
1537 | ||
7454c7af MR |
1538 | spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); |
1539 | if (local_err) { | |
1540 | error_propagate(errp, local_err); | |
1541 | return; | |
1542 | } | |
788d2599 MR |
1543 | |
1544 | /* if this isn't func 0, defer unplug event. otherwise signal removal | |
1545 | * for all present functions | |
1546 | */ | |
1547 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1548 | for (i = 7; i >= 0; i--) { | |
1549 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1550 | PCI_DEVFN(slotnr, i)); | |
1551 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
1552 | func_drck->entity_sense(func_drc, &state); | |
1553 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { | |
1554 | spapr_hotplug_req_remove_by_index(func_drc); | |
1555 | } | |
1556 | } | |
1557 | } | |
7454c7af MR |
1558 | } |
1559 | } | |
1560 | ||
c6ba42f6 | 1561 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 1562 | { |
28e02042 | 1563 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
c6ba42f6 | 1564 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
8c9f64df | 1565 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 1566 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
298a9710 DG |
1567 | char *namebuf; |
1568 | int i; | |
3384f95c | 1569 | PCIBus *bus; |
8c46f7ec | 1570 | uint64_t msi_window_size = 4096; |
a36304fd | 1571 | sPAPRTCETable *tcet; |
ae4de14c AK |
1572 | const unsigned windows_supported = |
1573 | sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; | |
3384f95c | 1574 | |
421b1b27 | 1575 | if (sphb->index != (uint32_t)-1) { |
6737d9ad DG |
1576 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
1577 | Error *local_err = NULL; | |
caae58cb | 1578 | |
ae4de14c AK |
1579 | if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn[0] != (uint32_t)-1) |
1580 | || (sphb->dma_liobn[1] != (uint32_t)-1 && windows_supported == 2) | |
421b1b27 | 1581 | || (sphb->mem_win_addr != (hwaddr)-1) |
daa23699 | 1582 | || (sphb->mem64_win_addr != (hwaddr)-1) |
421b1b27 | 1583 | || (sphb->io_win_addr != (hwaddr)-1)) { |
c6ba42f6 AK |
1584 | error_setg(errp, "Either \"index\" or other parameters must" |
1585 | " be specified for PAPR PHB, not both"); | |
1586 | return; | |
caae58cb DG |
1587 | } |
1588 | ||
daa23699 DG |
1589 | smc->phb_placement(spapr, sphb->index, |
1590 | &sphb->buid, &sphb->io_win_addr, | |
1591 | &sphb->mem_win_addr, &sphb->mem64_win_addr, | |
6737d9ad DG |
1592 | windows_supported, sphb->dma_liobn, &local_err); |
1593 | if (local_err) { | |
1594 | error_propagate(errp, local_err); | |
3e4ac968 DG |
1595 | return; |
1596 | } | |
caae58cb DG |
1597 | } |
1598 | ||
421b1b27 | 1599 | if (sphb->buid == (uint64_t)-1) { |
c6ba42f6 AK |
1600 | error_setg(errp, "BUID not specified for PHB"); |
1601 | return; | |
caae58cb DG |
1602 | } |
1603 | ||
ae4de14c AK |
1604 | if ((sphb->dma_liobn[0] == (uint32_t)-1) || |
1605 | ((sphb->dma_liobn[1] == (uint32_t)-1) && (windows_supported > 1))) { | |
1606 | error_setg(errp, "LIOBN(s) not specified for PHB"); | |
c6ba42f6 | 1607 | return; |
caae58cb DG |
1608 | } |
1609 | ||
421b1b27 | 1610 | if (sphb->mem_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1611 | error_setg(errp, "Memory window address not specified for PHB"); |
1612 | return; | |
caae58cb DG |
1613 | } |
1614 | ||
421b1b27 | 1615 | if (sphb->io_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1616 | error_setg(errp, "IO window address not specified for PHB"); |
1617 | return; | |
caae58cb DG |
1618 | } |
1619 | ||
daa23699 DG |
1620 | if (sphb->mem64_win_size != 0) { |
1621 | if (sphb->mem64_win_addr == (hwaddr)-1) { | |
1622 | error_setg(errp, | |
1623 | "64-bit memory window address not specified for PHB"); | |
1624 | return; | |
1625 | } | |
1626 | ||
1627 | if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { | |
1628 | error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx | |
1629 | " (max 2 GiB)", sphb->mem_win_size); | |
1630 | return; | |
1631 | } | |
1632 | ||
1633 | if (sphb->mem64_win_pciaddr == (hwaddr)-1) { | |
1634 | /* 64-bit window defaults to identity mapping */ | |
1635 | sphb->mem64_win_pciaddr = sphb->mem64_win_addr; | |
1636 | } | |
1637 | } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { | |
1638 | /* | |
1639 | * For compatibility with old configuration, if no 64-bit MMIO | |
1640 | * window is specified, but the ordinary (32-bit) memory | |
1641 | * window is specified as > 2GiB, we treat it as a 2GiB 32-bit | |
1642 | * window, with a 64-bit MMIO window following on immediately | |
1643 | * afterwards | |
1644 | */ | |
1645 | sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; | |
1646 | sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; | |
1647 | sphb->mem64_win_pciaddr = | |
1648 | SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; | |
1649 | sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; | |
1650 | } | |
1651 | ||
46c5874e | 1652 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
c6ba42f6 AK |
1653 | error_setg(errp, "PCI host bridges must have unique BUIDs"); |
1654 | return; | |
caae58cb DG |
1655 | } |
1656 | ||
4bcfa56c MR |
1657 | if (sphb->numa_node != -1 && |
1658 | (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) { | |
1659 | error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); | |
1660 | return; | |
1661 | } | |
1662 | ||
8c9f64df | 1663 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 1664 | |
8c9f64df | 1665 | namebuf = alloca(strlen(sphb->dtbusname) + 32); |
3384f95c | 1666 | |
298a9710 | 1667 | /* Initialize memory regions */ |
8c9f64df | 1668 | sprintf(namebuf, "%s.mmio", sphb->dtbusname); |
92b8e39c | 1669 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
3384f95c | 1670 | |
daa23699 DG |
1671 | sprintf(namebuf, "%s.mmio32-alias", sphb->dtbusname); |
1672 | memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), | |
40c5dce9 | 1673 | namebuf, &sphb->memspace, |
8c9f64df AF |
1674 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
1675 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, | |
daa23699 DG |
1676 | &sphb->mem32window); |
1677 | ||
1678 | sprintf(namebuf, "%s.mmio64-alias", sphb->dtbusname); | |
1679 | memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), | |
1680 | namebuf, &sphb->memspace, | |
1681 | sphb->mem64_win_pciaddr, sphb->mem64_win_size); | |
1682 | memory_region_add_subregion(get_system_memory(), sphb->mem64_win_addr, | |
1683 | &sphb->mem64window); | |
3384f95c | 1684 | |
fabe9ee1 | 1685 | /* Initialize IO regions */ |
8c9f64df | 1686 | sprintf(namebuf, "%s.io", sphb->dtbusname); |
40c5dce9 PB |
1687 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
1688 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
3384f95c | 1689 | |
a3cfa18e | 1690 | sprintf(namebuf, "%s.io-alias", sphb->dtbusname); |
66aab867 | 1691 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 1692 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
8c9f64df | 1693 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 1694 | &sphb->iowindow); |
1b8601b0 AK |
1695 | |
1696 | bus = pci_register_bus(dev, NULL, | |
8c9f64df AF |
1697 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, |
1698 | &sphb->memspace, &sphb->iospace, | |
60a0e443 | 1699 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); |
8c9f64df | 1700 | phb->bus = bus; |
7454c7af | 1701 | qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); |
298a9710 | 1702 | |
cca7fad5 AK |
1703 | /* |
1704 | * Initialize PHB address space. | |
1705 | * By default there will be at least one subregion for default | |
1706 | * 32bit DMA window. | |
1707 | * Later the guest might want to create another DMA window | |
1708 | * which will become another memory subregion. | |
1709 | */ | |
1710 | sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); | |
1711 | ||
1712 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), | |
1713 | namebuf, UINT64_MAX); | |
1714 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, | |
1715 | sphb->dtbusname); | |
1716 | ||
8c46f7ec GK |
1717 | /* |
1718 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
1719 | * we need to allocate some memory to catch those writes coming | |
1720 | * from msi_notify()/msix_notify(). | |
1721 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
1722 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
1723 | * be used. | |
1724 | * | |
1725 | * For KVM we want to ensure that this memory is a full page so that | |
1726 | * our memory slot is of page size granularity. | |
1727 | */ | |
1728 | #ifdef CONFIG_KVM | |
1729 | if (kvm_enabled()) { | |
1730 | msi_window_size = getpagesize(); | |
1731 | } | |
1732 | #endif | |
1733 | ||
1734 | memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, | |
1735 | "msi", msi_window_size); | |
1736 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
1737 | &sphb->msiwindow); | |
1738 | ||
e00387d5 | 1739 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 1740 | |
5cc7a967 AK |
1741 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
1742 | ||
8c9f64df | 1743 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
1744 | |
1745 | /* Initialize the LSI table */ | |
7fb0bd34 | 1746 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 1747 | uint32_t irq; |
a005b3ef | 1748 | Error *local_err = NULL; |
298a9710 | 1749 | |
681bfade | 1750 | irq = spapr_ics_alloc_block(spapr->ics, 1, true, false, &local_err); |
a005b3ef GK |
1751 | if (local_err) { |
1752 | error_propagate(errp, local_err); | |
1753 | error_prepend(errp, "can't allocate LSIs: "); | |
c6ba42f6 | 1754 | return; |
298a9710 DG |
1755 | } |
1756 | ||
8c9f64df | 1757 | sphb->lsi_table[i].irq = irq; |
298a9710 | 1758 | } |
da6ccee4 | 1759 | |
62083979 MR |
1760 | /* allocate connectors for child PCI devices */ |
1761 | if (sphb->dr_enabled) { | |
1762 | for (i = 0; i < PCI_SLOT_MAX * 8; i++) { | |
1763 | spapr_dr_connector_new(OBJECT(phb), | |
1764 | SPAPR_DR_CONNECTOR_TYPE_PCI, | |
1765 | (sphb->index << 16) | i); | |
1766 | } | |
1767 | } | |
1768 | ||
ae4de14c AK |
1769 | /* DMA setup */ |
1770 | for (i = 0; i < windows_supported; ++i) { | |
1771 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); | |
1772 | if (!tcet) { | |
1773 | error_setg(errp, "Creating window#%d failed for %s", | |
1774 | i, sphb->dtbusname); | |
1775 | return; | |
1776 | } | |
1777 | memory_region_add_subregion_overlap(&sphb->iommu_root, 0, | |
1778 | spapr_tce_get_iommu(tcet), 0); | |
da6ccee4 | 1779 | } |
cca7fad5 | 1780 | |
a36304fd | 1781 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); |
298a9710 DG |
1782 | } |
1783 | ||
e28c16f6 | 1784 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 1785 | { |
e28c16f6 AK |
1786 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
1787 | ||
1788 | if (dev) { | |
1789 | device_reset(dev); | |
1790 | } | |
eddeed26 | 1791 | |
e28c16f6 AK |
1792 | return 0; |
1793 | } | |
1794 | ||
b3162f22 | 1795 | void spapr_phb_dma_reset(sPAPRPHBState *sphb) |
e28c16f6 | 1796 | { |
ae4de14c AK |
1797 | int i; |
1798 | sPAPRTCETable *tcet; | |
1799 | ||
1800 | for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { | |
1801 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); | |
acf1b6dd | 1802 | |
ae4de14c AK |
1803 | if (tcet && tcet->nb_table) { |
1804 | spapr_tce_table_disable(tcet); | |
1805 | } | |
acf1b6dd AK |
1806 | } |
1807 | ||
1808 | /* Register default 32bit DMA window */ | |
ae4de14c | 1809 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); |
acf1b6dd AK |
1810 | spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, |
1811 | sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); | |
b3162f22 AK |
1812 | } |
1813 | ||
1814 | static void spapr_phb_reset(DeviceState *qdev) | |
1815 | { | |
1816 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); | |
1817 | ||
1818 | spapr_phb_dma_reset(sphb); | |
acf1b6dd | 1819 | |
eddeed26 | 1820 | /* Reset the IOMMU state */ |
e28c16f6 | 1821 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
fbb4e983 DG |
1822 | |
1823 | if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { | |
1824 | spapr_phb_vfio_reset(qdev); | |
1825 | } | |
eddeed26 DG |
1826 | } |
1827 | ||
298a9710 | 1828 | static Property spapr_phb_properties[] = { |
3e4ac968 | 1829 | DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), |
c7bcc85d | 1830 | DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), |
ae4de14c AK |
1831 | DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn[0], -1), |
1832 | DEFINE_PROP_UINT32("liobn64", sPAPRPHBState, dma_liobn[1], -1), | |
c7bcc85d PB |
1833 | DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), |
1834 | DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, | |
357d1e3b | 1835 | SPAPR_PCI_MEM32_WIN_SIZE), |
daa23699 | 1836 | DEFINE_PROP_UINT64("mem64_win_addr", sPAPRPHBState, mem64_win_addr, -1), |
357d1e3b DG |
1837 | DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size, |
1838 | SPAPR_PCI_MEM64_WIN_SIZE), | |
daa23699 DG |
1839 | DEFINE_PROP_UINT64("mem64_win_pciaddr", sPAPRPHBState, mem64_win_pciaddr, |
1840 | -1), | |
c7bcc85d PB |
1841 | DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), |
1842 | DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, | |
1843 | SPAPR_PCI_IO_WIN_SIZE), | |
7619c7b0 MR |
1844 | DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, |
1845 | true), | |
f93caaac DG |
1846 | /* Default DMA window is 0..1GB */ |
1847 | DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0), | |
1848 | DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000), | |
ae4de14c AK |
1849 | DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr, |
1850 | 0x800000000000000ULL), | |
1851 | DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true), | |
1852 | DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask, | |
1853 | (1ULL << 12) | (1ULL << 16)), | |
4814401f | 1854 | DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1), |
5c4537bd DG |
1855 | DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState, |
1856 | pre_2_8_migration, false), | |
298a9710 DG |
1857 | DEFINE_PROP_END_OF_LIST(), |
1858 | }; | |
1859 | ||
1112cf94 DG |
1860 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
1861 | .name = "spapr_pci/lsi", | |
1862 | .version_id = 1, | |
1863 | .minimum_version_id = 1, | |
3aff6c2f | 1864 | .fields = (VMStateField[]) { |
1112cf94 DG |
1865 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), |
1866 | ||
1867 | VMSTATE_END_OF_LIST() | |
1868 | }, | |
1869 | }; | |
1870 | ||
1871 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 1872 | .name = "spapr_pci/msi", |
1112cf94 DG |
1873 | .version_id = 1, |
1874 | .minimum_version_id = 1, | |
9a321e92 AK |
1875 | .fields = (VMStateField []) { |
1876 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
1877 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
1878 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
1879 | VMSTATE_END_OF_LIST() |
1880 | }, | |
1881 | }; | |
1882 | ||
9a321e92 AK |
1883 | static void spapr_pci_pre_save(void *opaque) |
1884 | { | |
1885 | sPAPRPHBState *sphb = opaque; | |
708414f0 MA |
1886 | GHashTableIter iter; |
1887 | gpointer key, value; | |
1888 | int i; | |
9a321e92 | 1889 | |
012aef07 MA |
1890 | g_free(sphb->msi_devs); |
1891 | sphb->msi_devs = NULL; | |
708414f0 MA |
1892 | sphb->msi_devs_num = g_hash_table_size(sphb->msi); |
1893 | if (!sphb->msi_devs_num) { | |
9a321e92 AK |
1894 | return; |
1895 | } | |
708414f0 | 1896 | sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); |
9a321e92 | 1897 | |
708414f0 MA |
1898 | g_hash_table_iter_init(&iter, sphb->msi); |
1899 | for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { | |
1900 | sphb->msi_devs[i].key = *(uint32_t *) key; | |
1901 | sphb->msi_devs[i].value = *(spapr_pci_msi *) value; | |
1902 | } | |
5c4537bd DG |
1903 | |
1904 | if (sphb->pre_2_8_migration) { | |
1905 | sphb->mig_liobn = sphb->dma_liobn[0]; | |
1906 | sphb->mig_mem_win_addr = sphb->mem_win_addr; | |
1907 | sphb->mig_mem_win_size = sphb->mem_win_size; | |
1908 | sphb->mig_io_win_addr = sphb->io_win_addr; | |
1909 | sphb->mig_io_win_size = sphb->io_win_size; | |
1910 | ||
1911 | if ((sphb->mem64_win_size != 0) | |
1912 | && (sphb->mem64_win_addr | |
1913 | == (sphb->mem_win_addr + sphb->mem_win_size))) { | |
1914 | sphb->mig_mem_win_size += sphb->mem64_win_size; | |
1915 | } | |
1916 | } | |
9a321e92 AK |
1917 | } |
1918 | ||
1919 | static int spapr_pci_post_load(void *opaque, int version_id) | |
1920 | { | |
1921 | sPAPRPHBState *sphb = opaque; | |
1922 | gpointer key, value; | |
1923 | int i; | |
1924 | ||
1925 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
1926 | key = g_memdup(&sphb->msi_devs[i].key, | |
1927 | sizeof(sphb->msi_devs[i].key)); | |
1928 | value = g_memdup(&sphb->msi_devs[i].value, | |
1929 | sizeof(sphb->msi_devs[i].value)); | |
1930 | g_hash_table_insert(sphb->msi, key, value); | |
1931 | } | |
012aef07 MA |
1932 | g_free(sphb->msi_devs); |
1933 | sphb->msi_devs = NULL; | |
9a321e92 AK |
1934 | sphb->msi_devs_num = 0; |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
5c4537bd DG |
1939 | static bool pre_2_8_migration(void *opaque, int version_id) |
1940 | { | |
1941 | sPAPRPHBState *sphb = opaque; | |
1942 | ||
1943 | return sphb->pre_2_8_migration; | |
1944 | } | |
1945 | ||
1112cf94 DG |
1946 | static const VMStateDescription vmstate_spapr_pci = { |
1947 | .name = "spapr_pci", | |
5a78b821 | 1948 | .version_id = 2, |
9a321e92 AK |
1949 | .minimum_version_id = 2, |
1950 | .pre_save = spapr_pci_pre_save, | |
1951 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 1952 | .fields = (VMStateField[]) { |
1112cf94 | 1953 | VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), |
5c4537bd DG |
1954 | VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration), |
1955 | VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration), | |
1956 | VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration), | |
1957 | VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration), | |
1958 | VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration), | |
1112cf94 DG |
1959 | VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, |
1960 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), | |
9a321e92 AK |
1961 | VMSTATE_INT32(msi_devs_num, sPAPRPHBState), |
1962 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, | |
1963 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), | |
1112cf94 DG |
1964 | VMSTATE_END_OF_LIST() |
1965 | }, | |
1966 | }; | |
1967 | ||
568f0690 DG |
1968 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
1969 | PCIBus *rootbus) | |
1970 | { | |
1971 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
1972 | ||
1973 | return sphb->dtbusname; | |
1974 | } | |
1975 | ||
298a9710 DG |
1976 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
1977 | { | |
568f0690 | 1978 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 1979 | DeviceClass *dc = DEVICE_CLASS(klass); |
7454c7af | 1980 | HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); |
298a9710 | 1981 | |
568f0690 | 1982 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 1983 | dc->realize = spapr_phb_realize; |
298a9710 | 1984 | dc->props = spapr_phb_properties; |
eddeed26 | 1985 | dc->reset = spapr_phb_reset; |
1112cf94 | 1986 | dc->vmsd = &vmstate_spapr_pci; |
09aa9a52 | 1987 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
7454c7af MR |
1988 | hp->plug = spapr_phb_hot_plug_child; |
1989 | hp->unplug = spapr_phb_hot_unplug_child; | |
298a9710 | 1990 | } |
3384f95c | 1991 | |
4240abff | 1992 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 1993 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 1994 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
1995 | .instance_size = sizeof(sPAPRPHBState), |
1996 | .class_init = spapr_phb_class_init, | |
7454c7af MR |
1997 | .interfaces = (InterfaceInfo[]) { |
1998 | { TYPE_HOTPLUG_HANDLER }, | |
1999 | { } | |
2000 | } | |
298a9710 DG |
2001 | }; |
2002 | ||
28e02042 | 2003 | PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) |
298a9710 DG |
2004 | { |
2005 | DeviceState *dev; | |
2006 | ||
8c9f64df | 2007 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 2008 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 2009 | qdev_init_nofail(dev); |
caae58cb DG |
2010 | |
2011 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
2012 | } |
2013 | ||
1d2d9742 ND |
2014 | typedef struct sPAPRFDT { |
2015 | void *fdt; | |
2016 | int node_off; | |
2017 | sPAPRPHBState *sphb; | |
2018 | } sPAPRFDT; | |
2019 | ||
2020 | static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, | |
2021 | void *opaque) | |
2022 | { | |
2023 | PCIBus *sec_bus; | |
2024 | sPAPRFDT *p = opaque; | |
2025 | int offset; | |
2026 | sPAPRFDT s_fdt; | |
1d2d9742 | 2027 | |
e634b89c | 2028 | offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); |
1d2d9742 ND |
2029 | if (!offset) { |
2030 | error_report("Failed to create pci child device tree node"); | |
2031 | return; | |
2032 | } | |
2033 | ||
2034 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
2035 | PCI_HEADER_TYPE_BRIDGE)) { | |
2036 | return; | |
2037 | } | |
2038 | ||
2039 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
2040 | if (!sec_bus) { | |
2041 | return; | |
2042 | } | |
2043 | ||
2044 | s_fdt.fdt = p->fdt; | |
2045 | s_fdt.node_off = offset; | |
2046 | s_fdt.sphb = p->sphb; | |
a8eeafda GK |
2047 | pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus), |
2048 | spapr_populate_pci_devices_dt, | |
2049 | &s_fdt); | |
1d2d9742 ND |
2050 | } |
2051 | ||
2052 | static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, | |
2053 | void *opaque) | |
2054 | { | |
2055 | unsigned int *bus_no = opaque; | |
2056 | unsigned int primary = *bus_no; | |
2057 | unsigned int subordinate = 0xff; | |
2058 | PCIBus *sec_bus = NULL; | |
2059 | ||
2060 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
2061 | PCI_HEADER_TYPE_BRIDGE)) { | |
2062 | return; | |
2063 | } | |
2064 | ||
2065 | (*bus_no)++; | |
2066 | pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); | |
2067 | pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); | |
2068 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2069 | ||
2070 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
2071 | if (!sec_bus) { | |
2072 | return; | |
2073 | } | |
2074 | ||
2075 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); | |
2076 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
2077 | spapr_phb_pci_enumerate_bridge, bus_no); | |
2078 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2079 | } | |
2080 | ||
2081 | static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) | |
2082 | { | |
2083 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; | |
2084 | unsigned int bus_no = 0; | |
2085 | ||
2086 | pci_for_each_device(bus, pci_bus_num(bus), | |
2087 | spapr_phb_pci_enumerate_bridge, | |
2088 | &bus_no); | |
2089 | ||
2090 | } | |
2091 | ||
e0fdbd7c AK |
2092 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
2093 | uint32_t xics_phandle, | |
2094 | void *fdt) | |
3384f95c | 2095 | { |
62083979 | 2096 | int bus_off, i, j, ret; |
9b7d9284 | 2097 | char nodename[FDT_NAME_MAX]; |
3384f95c DG |
2098 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
2099 | struct { | |
2100 | uint32_t hi; | |
2101 | uint64_t child; | |
2102 | uint64_t parent; | |
2103 | uint64_t size; | |
c4889f54 | 2104 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
2105 | { |
2106 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
2107 | cpu_to_be64(phb->io_win_addr), | |
2108 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
2109 | }, | |
2110 | { | |
2111 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
2112 | cpu_to_be64(phb->mem_win_addr), | |
daa23699 | 2113 | cpu_to_be64(phb->mem_win_size), |
b194df47 AK |
2114 | }, |
2115 | { | |
daa23699 DG |
2116 | cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), |
2117 | cpu_to_be64(phb->mem64_win_addr), | |
2118 | cpu_to_be64(phb->mem64_win_size), | |
3384f95c DG |
2119 | }, |
2120 | }; | |
daa23699 DG |
2121 | const unsigned sizeof_ranges = |
2122 | (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); | |
3384f95c DG |
2123 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
2124 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
2125 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
2126 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
ae4de14c AK |
2127 | uint32_t ddw_applicable[] = { |
2128 | cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), | |
2129 | cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), | |
2130 | cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) | |
2131 | }; | |
2132 | uint32_t ddw_extensions[] = { | |
2133 | cpu_to_be32(1), | |
2134 | cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) | |
2135 | }; | |
4814401f AK |
2136 | uint32_t associativity[] = {cpu_to_be32(0x4), |
2137 | cpu_to_be32(0x0), | |
2138 | cpu_to_be32(0x0), | |
2139 | cpu_to_be32(0x0), | |
2140 | cpu_to_be32(phb->numa_node)}; | |
ccf9ff85 | 2141 | sPAPRTCETable *tcet; |
1d2d9742 ND |
2142 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; |
2143 | sPAPRFDT s_fdt; | |
3384f95c DG |
2144 | |
2145 | /* Start populating the FDT */ | |
9b7d9284 | 2146 | snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); |
3384f95c DG |
2147 | bus_off = fdt_add_subnode(fdt, 0, nodename); |
2148 | if (bus_off < 0) { | |
2149 | return bus_off; | |
2150 | } | |
2151 | ||
3384f95c DG |
2152 | /* Write PHB properties */ |
2153 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
2154 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
2155 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
2156 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
2157 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
2158 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
2159 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 2160 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 2161 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 2162 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
161deaf2 | 2163 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR)); |
3384f95c | 2164 | |
ae4de14c AK |
2165 | /* Dynamic DMA window */ |
2166 | if (phb->ddw_enabled) { | |
2167 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, | |
2168 | sizeof(ddw_applicable))); | |
2169 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", | |
2170 | &ddw_extensions, sizeof(ddw_extensions))); | |
2171 | } | |
2172 | ||
4814401f | 2173 | /* Advertise NUMA via ibm,associativity */ |
4bcfa56c | 2174 | if (phb->numa_node != -1) { |
4814401f AK |
2175 | _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, |
2176 | sizeof(associativity))); | |
2177 | } | |
2178 | ||
4d8d5467 BH |
2179 | /* Build the interrupt-map, this must matches what is done |
2180 | * in pci_spapr_map_irq | |
2181 | */ | |
2182 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
2183 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
2184 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
2185 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
2186 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
2187 | int lsi_num = pci_spapr_swizzle(i, j); | |
2188 | ||
2189 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
2190 | irqmap[1] = 0; | |
2191 | irqmap[2] = 0; | |
2192 | irqmap[3] = cpu_to_be32(j+1); | |
2193 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 2194 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
2195 | irqmap[6] = cpu_to_be32(0x8); |
2196 | } | |
3384f95c | 2197 | } |
3384f95c DG |
2198 | /* Write interrupt map */ |
2199 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 2200 | sizeof(interrupt_map))); |
3384f95c | 2201 | |
ae4de14c | 2202 | tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); |
da34fed7 TH |
2203 | if (!tcet) { |
2204 | return -1; | |
2205 | } | |
ccf9ff85 AK |
2206 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", |
2207 | tcet->liobn, tcet->bus_offset, | |
2208 | tcet->nb_table << tcet->page_shift); | |
edded454 | 2209 | |
1d2d9742 ND |
2210 | /* Walk the bridges and program the bus numbers*/ |
2211 | spapr_phb_pci_enumerate(phb); | |
2212 | _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); | |
2213 | ||
2214 | /* Populate tree nodes with PCI devices attached */ | |
2215 | s_fdt.fdt = fdt; | |
2216 | s_fdt.node_off = bus_off; | |
2217 | s_fdt.sphb = phb; | |
a8eeafda GK |
2218 | pci_for_each_device_reverse(bus, pci_bus_num(bus), |
2219 | spapr_populate_pci_devices_dt, | |
2220 | &s_fdt); | |
1d2d9742 | 2221 | |
62083979 MR |
2222 | ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), |
2223 | SPAPR_DR_CONNECTOR_TYPE_PCI); | |
2224 | if (ret) { | |
2225 | return ret; | |
2226 | } | |
2227 | ||
3384f95c DG |
2228 | return 0; |
2229 | } | |
298a9710 | 2230 | |
fa28f71b AK |
2231 | void spapr_pci_rtas_init(void) |
2232 | { | |
3a3b8502 AK |
2233 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
2234 | rtas_read_pci_config); | |
2235 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
2236 | rtas_write_pci_config); | |
2237 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
2238 | rtas_ibm_read_pci_config); | |
2239 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
2240 | rtas_ibm_write_pci_config); | |
226419d6 | 2241 | if (msi_nonbroken) { |
3a3b8502 AK |
2242 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
2243 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 2244 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
2245 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
2246 | rtas_ibm_change_msi); | |
0ee2c058 | 2247 | } |
ee954280 GS |
2248 | |
2249 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
2250 | "ibm,set-eeh-option", | |
2251 | rtas_ibm_set_eeh_option); | |
2252 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
2253 | "ibm,get-config-addr-info2", | |
2254 | rtas_ibm_get_config_addr_info2); | |
2255 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
2256 | "ibm,read-slot-reset-state2", | |
2257 | rtas_ibm_read_slot_reset_state2); | |
2258 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
2259 | "ibm,set-slot-reset", | |
2260 | rtas_ibm_set_slot_reset); | |
2261 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
2262 | "ibm,configure-pe", | |
2263 | rtas_ibm_configure_pe); | |
2264 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
2265 | "ibm,slot-error-detail", | |
2266 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
2267 | } |
2268 | ||
8c9f64df | 2269 | static void spapr_pci_register_types(void) |
298a9710 DG |
2270 | { |
2271 | type_register_static(&spapr_phb_info); | |
2272 | } | |
8c9f64df AF |
2273 | |
2274 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
2275 | |
2276 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
2277 | { | |
2278 | bool be = *(bool *)opaque; | |
2279 | ||
2280 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
2281 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
2282 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
2283 | &error_abort); | |
2284 | } | |
2285 | return 0; | |
2286 | } | |
2287 | ||
2288 | void spapr_pci_switch_vga(bool big_endian) | |
2289 | { | |
28e02042 | 2290 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
eefaccc0 DG |
2291 | sPAPRPHBState *sphb; |
2292 | ||
2293 | /* | |
2294 | * For backward compatibility with existing guests, we switch | |
2295 | * the endianness of the VGA controller when changing the guest | |
2296 | * interrupt mode | |
2297 | */ | |
2298 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
2299 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
2300 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
2301 | &big_endian); | |
2302 | } | |
2303 | } |