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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/pci/pci.h" | |
27 | #include "hw/pci/msi.h" | |
28 | #include "hw/pci/msix.h" | |
29 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
30 | #include "hw/ppc/spapr.h" |
31 | #include "hw/pci-host/spapr.h" | |
022c62cb | 32 | #include "exec/address-spaces.h" |
3384f95c | 33 | #include <libfdt.h> |
a2950fb6 | 34 | #include "trace.h" |
295d51aa | 35 | #include "qemu/error-report.h" |
7454c7af | 36 | #include "qapi/qmp/qerror.h" |
3384f95c | 37 | |
06aac7bd | 38 | #include "hw/pci/pci_bus.h" |
62083979 | 39 | #include "hw/ppc/spapr_drc.h" |
7454c7af | 40 | #include "sysemu/device_tree.h" |
3384f95c | 41 | |
0ee2c058 AK |
42 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
43 | #define RTAS_QUERY_FN 0 | |
44 | #define RTAS_CHANGE_FN 1 | |
45 | #define RTAS_RESET_FN 2 | |
46 | #define RTAS_CHANGE_MSI_FN 3 | |
47 | #define RTAS_CHANGE_MSIX_FN 4 | |
48 | ||
49 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
50 | #define RTAS_TYPE_MSI 1 | |
51 | #define RTAS_TYPE_MSIX 2 | |
52 | ||
9b7d9284 ND |
53 | #define FDT_NAME_MAX 128 |
54 | ||
7454c7af MR |
55 | #define _FDT(exp) \ |
56 | do { \ | |
57 | int ret = (exp); \ | |
58 | if (ret < 0) { \ | |
59 | return ret; \ | |
60 | } \ | |
61 | } while (0) | |
62 | ||
28e02042 | 63 | sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) |
3384f95c | 64 | { |
8c9f64df | 65 | sPAPRPHBState *sphb; |
3384f95c | 66 | |
8c9f64df AF |
67 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
68 | if (sphb->buid != buid) { | |
3384f95c DG |
69 | continue; |
70 | } | |
8c9f64df | 71 | return sphb; |
9894c5d4 AK |
72 | } |
73 | ||
74 | return NULL; | |
75 | } | |
76 | ||
28e02042 | 77 | PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, |
46c5874e | 78 | uint32_t config_addr) |
9894c5d4 | 79 | { |
46c5874e | 80 | sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 81 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 82 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
83 | int devfn = (config_addr >> 8) & 0xFF; |
84 | ||
85 | if (!phb) { | |
86 | return NULL; | |
87 | } | |
3384f95c | 88 | |
5dac82ce | 89 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
90 | } |
91 | ||
3f7565c9 BH |
92 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
93 | { | |
92615a5a | 94 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
95 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
96 | } | |
97 | ||
28e02042 | 98 | static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
99 | uint32_t addr, uint32_t size, |
100 | target_ulong rets) | |
88045ac5 | 101 | { |
92615a5a DG |
102 | PCIDevice *pci_dev; |
103 | uint32_t val; | |
104 | ||
105 | if ((size != 1) && (size != 2) && (size != 4)) { | |
106 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 107 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 108 | return; |
88045ac5 | 109 | } |
88045ac5 | 110 | |
46c5874e | 111 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
112 | addr = rtas_pci_cfgaddr(addr); |
113 | ||
114 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
115 | /* Access must be to a valid device, within bounds and | |
116 | * naturally aligned */ | |
a64d325d | 117 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 118 | return; |
88045ac5 | 119 | } |
92615a5a DG |
120 | |
121 | val = pci_host_config_read_common(pci_dev, addr, | |
122 | pci_config_size(pci_dev), size); | |
123 | ||
a64d325d | 124 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 125 | rtas_st(rets, 1, val); |
88045ac5 AG |
126 | } |
127 | ||
28e02042 | 128 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
129 | uint32_t token, uint32_t nargs, |
130 | target_ulong args, | |
131 | uint32_t nret, target_ulong rets) | |
132 | { | |
92615a5a DG |
133 | uint64_t buid; |
134 | uint32_t size, addr; | |
3384f95c | 135 | |
92615a5a | 136 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 137 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
138 | return; |
139 | } | |
92615a5a DG |
140 | |
141 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c | 142 | size = rtas_ld(args, 3); |
92615a5a DG |
143 | addr = rtas_ld(args, 0); |
144 | ||
145 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
146 | } |
147 | ||
28e02042 | 148 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
149 | uint32_t token, uint32_t nargs, |
150 | target_ulong args, | |
151 | uint32_t nret, target_ulong rets) | |
152 | { | |
92615a5a | 153 | uint32_t size, addr; |
3384f95c | 154 | |
92615a5a | 155 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 156 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
157 | return; |
158 | } | |
92615a5a | 159 | |
3384f95c | 160 | size = rtas_ld(args, 1); |
92615a5a DG |
161 | addr = rtas_ld(args, 0); |
162 | ||
163 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
164 | } | |
165 | ||
28e02042 | 166 | static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
167 | uint32_t addr, uint32_t size, |
168 | uint32_t val, target_ulong rets) | |
169 | { | |
170 | PCIDevice *pci_dev; | |
171 | ||
172 | if ((size != 1) && (size != 2) && (size != 4)) { | |
173 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 174 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
175 | return; |
176 | } | |
177 | ||
46c5874e | 178 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
179 | addr = rtas_pci_cfgaddr(addr); |
180 | ||
181 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
182 | /* Access must be to a valid device, within bounds and | |
183 | * naturally aligned */ | |
a64d325d | 184 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
185 | return; |
186 | } | |
187 | ||
188 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
189 | val, size); | |
190 | ||
a64d325d | 191 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
192 | } |
193 | ||
28e02042 | 194 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
195 | uint32_t token, uint32_t nargs, |
196 | target_ulong args, | |
197 | uint32_t nret, target_ulong rets) | |
198 | { | |
92615a5a | 199 | uint64_t buid; |
3384f95c | 200 | uint32_t val, size, addr; |
3384f95c | 201 | |
92615a5a | 202 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 203 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
204 | return; |
205 | } | |
92615a5a DG |
206 | |
207 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c DG |
208 | val = rtas_ld(args, 4); |
209 | size = rtas_ld(args, 3); | |
92615a5a DG |
210 | addr = rtas_ld(args, 0); |
211 | ||
212 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
213 | } |
214 | ||
28e02042 | 215 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
216 | uint32_t token, uint32_t nargs, |
217 | target_ulong args, | |
218 | uint32_t nret, target_ulong rets) | |
219 | { | |
220 | uint32_t val, size, addr; | |
3384f95c | 221 | |
92615a5a | 222 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 223 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
224 | return; |
225 | } | |
92615a5a DG |
226 | |
227 | ||
3384f95c DG |
228 | val = rtas_ld(args, 2); |
229 | size = rtas_ld(args, 1); | |
92615a5a DG |
230 | addr = rtas_ld(args, 0); |
231 | ||
232 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
233 | } |
234 | ||
0ee2c058 AK |
235 | /* |
236 | * Set MSI/MSIX message data. | |
237 | * This is required for msi_notify()/msix_notify() which | |
238 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
239 | * |
240 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
241 | * table will be reset. | |
0ee2c058 | 242 | */ |
f1c2dc7c AK |
243 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
244 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
245 | { |
246 | unsigned i; | |
f1c2dc7c | 247 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
248 | |
249 | if (!msix) { | |
250 | msi_set_message(pdev, msg); | |
251 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
252 | return; | |
253 | } | |
254 | ||
9a321e92 | 255 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
256 | msix_set_message(pdev, i, msg); |
257 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
258 | if (addr) { |
259 | ++msg.data; | |
260 | } | |
0ee2c058 AK |
261 | } |
262 | } | |
263 | ||
28e02042 | 264 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
0ee2c058 AK |
265 | uint32_t token, uint32_t nargs, |
266 | target_ulong args, uint32_t nret, | |
267 | target_ulong rets) | |
268 | { | |
269 | uint32_t config_addr = rtas_ld(args, 0); | |
270 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
271 | unsigned int func = rtas_ld(args, 3); | |
272 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
273 | unsigned int seq_num = rtas_ld(args, 5); | |
274 | unsigned int ret_intr_type; | |
9a321e92 | 275 | unsigned int irq, max_irqs = 0, num = 0; |
0ee2c058 AK |
276 | sPAPRPHBState *phb = NULL; |
277 | PCIDevice *pdev = NULL; | |
9a321e92 AK |
278 | spapr_pci_msi *msi; |
279 | int *config_addr_key; | |
0ee2c058 AK |
280 | |
281 | switch (func) { | |
282 | case RTAS_CHANGE_MSI_FN: | |
283 | case RTAS_CHANGE_FN: | |
284 | ret_intr_type = RTAS_TYPE_MSI; | |
285 | break; | |
286 | case RTAS_CHANGE_MSIX_FN: | |
287 | ret_intr_type = RTAS_TYPE_MSIX; | |
288 | break; | |
289 | default: | |
295d51aa | 290 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 291 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
292 | return; |
293 | } | |
294 | ||
295 | /* Fins sPAPRPHBState */ | |
46c5874e | 296 | phb = spapr_pci_find_phb(spapr, buid); |
0ee2c058 | 297 | if (phb) { |
46c5874e | 298 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
0ee2c058 AK |
299 | } |
300 | if (!phb || !pdev) { | |
a64d325d | 301 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
302 | return; |
303 | } | |
304 | ||
305 | /* Releasing MSIs */ | |
306 | if (!req_num) { | |
9a321e92 AK |
307 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
308 | if (!msi) { | |
309 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 310 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
311 | return; |
312 | } | |
9a321e92 AK |
313 | |
314 | xics_free(spapr->icp, msi->first_irq, msi->num); | |
32420522 AK |
315 | if (msi_present(pdev)) { |
316 | spapr_msi_setmsg(pdev, 0, false, 0, num); | |
317 | } | |
318 | if (msix_present(pdev)) { | |
319 | spapr_msi_setmsg(pdev, 0, true, 0, num); | |
320 | } | |
9a321e92 AK |
321 | g_hash_table_remove(phb->msi, &config_addr); |
322 | ||
323 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 324 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
325 | rtas_st(rets, 1, 0); |
326 | return; | |
327 | } | |
328 | ||
329 | /* Enabling MSI */ | |
330 | ||
28668b5f AK |
331 | /* Check if the device supports as many IRQs as requested */ |
332 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
333 | max_irqs = msi_nr_vectors_allocated(pdev); | |
334 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
335 | max_irqs = pdev->msix_entries_nr; | |
336 | } | |
337 | if (!max_irqs) { | |
9a321e92 AK |
338 | error_report("Requested interrupt type %d is not enabled for device %x", |
339 | ret_intr_type, config_addr); | |
28668b5f AK |
340 | rtas_st(rets, 0, -1); /* Hardware error */ |
341 | return; | |
342 | } | |
343 | /* Correct the number if the guest asked for too many */ | |
344 | if (req_num > max_irqs) { | |
9a321e92 | 345 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 346 | req_num = max_irqs; |
9a321e92 AK |
347 | irq = 0; /* to avoid misleading trace */ |
348 | goto out; | |
28668b5f AK |
349 | } |
350 | ||
9a321e92 AK |
351 | /* Allocate MSIs */ |
352 | irq = xics_alloc_block(spapr->icp, 0, req_num, false, | |
353 | ret_intr_type == RTAS_TYPE_MSI); | |
354 | if (!irq) { | |
355 | error_report("Cannot allocate MSIs for device %x", config_addr); | |
a64d325d | 356 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
357 | return; |
358 | } | |
359 | ||
0ee2c058 | 360 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 361 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 362 | irq, req_num); |
0ee2c058 | 363 | |
9a321e92 AK |
364 | /* Add MSI device to cache */ |
365 | msi = g_new(spapr_pci_msi, 1); | |
366 | msi->first_irq = irq; | |
367 | msi->num = req_num; | |
368 | config_addr_key = g_new(int, 1); | |
369 | *config_addr_key = config_addr; | |
370 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
371 | ||
372 | out: | |
a64d325d | 373 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
374 | rtas_st(rets, 1, req_num); |
375 | rtas_st(rets, 2, ++seq_num); | |
376 | rtas_st(rets, 3, ret_intr_type); | |
377 | ||
9a321e92 | 378 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
379 | } |
380 | ||
210b580b | 381 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
28e02042 | 382 | sPAPRMachineState *spapr, |
0ee2c058 AK |
383 | uint32_t token, |
384 | uint32_t nargs, | |
385 | target_ulong args, | |
386 | uint32_t nret, | |
387 | target_ulong rets) | |
388 | { | |
389 | uint32_t config_addr = rtas_ld(args, 0); | |
390 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
391 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); | |
0ee2c058 | 392 | sPAPRPHBState *phb = NULL; |
9a321e92 AK |
393 | PCIDevice *pdev = NULL; |
394 | spapr_pci_msi *msi; | |
0ee2c058 | 395 | |
9a321e92 | 396 | /* Find sPAPRPHBState */ |
46c5874e | 397 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 398 | if (phb) { |
46c5874e | 399 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
400 | } |
401 | if (!phb || !pdev) { | |
a64d325d | 402 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
403 | return; |
404 | } | |
405 | ||
406 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
407 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
408 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
409 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 410 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
411 | return; |
412 | } | |
9a321e92 | 413 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
414 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
415 | intr_src_num); | |
416 | ||
a64d325d | 417 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
418 | rtas_st(rets, 1, intr_src_num); |
419 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
420 | } | |
421 | ||
ee954280 | 422 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
28e02042 | 423 | sPAPRMachineState *spapr, |
ee954280 GS |
424 | uint32_t token, uint32_t nargs, |
425 | target_ulong args, uint32_t nret, | |
426 | target_ulong rets) | |
427 | { | |
428 | sPAPRPHBState *sphb; | |
429 | sPAPRPHBClass *spc; | |
430 | uint32_t addr, option; | |
431 | uint64_t buid; | |
432 | int ret; | |
433 | ||
434 | if ((nargs != 4) || (nret != 1)) { | |
435 | goto param_error_exit; | |
436 | } | |
437 | ||
438 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
439 | addr = rtas_ld(args, 0); | |
440 | option = rtas_ld(args, 3); | |
441 | ||
46c5874e | 442 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
443 | if (!sphb) { |
444 | goto param_error_exit; | |
445 | } | |
446 | ||
447 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
448 | if (!spc->eeh_set_option) { | |
449 | goto param_error_exit; | |
450 | } | |
451 | ||
452 | ret = spc->eeh_set_option(sphb, addr, option); | |
453 | rtas_st(rets, 0, ret); | |
454 | return; | |
455 | ||
456 | param_error_exit: | |
457 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
458 | } | |
459 | ||
460 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
28e02042 | 461 | sPAPRMachineState *spapr, |
ee954280 GS |
462 | uint32_t token, uint32_t nargs, |
463 | target_ulong args, uint32_t nret, | |
464 | target_ulong rets) | |
465 | { | |
466 | sPAPRPHBState *sphb; | |
467 | sPAPRPHBClass *spc; | |
468 | PCIDevice *pdev; | |
469 | uint32_t addr, option; | |
470 | uint64_t buid; | |
471 | ||
472 | if ((nargs != 4) || (nret != 2)) { | |
473 | goto param_error_exit; | |
474 | } | |
475 | ||
476 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 477 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
478 | if (!sphb) { |
479 | goto param_error_exit; | |
480 | } | |
481 | ||
482 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
483 | if (!spc->eeh_set_option) { | |
484 | goto param_error_exit; | |
485 | } | |
486 | ||
487 | /* | |
488 | * We always have PE address of form "00BB0001". "BB" | |
489 | * represents the bus number of PE's primary bus. | |
490 | */ | |
491 | option = rtas_ld(args, 3); | |
492 | switch (option) { | |
493 | case RTAS_GET_PE_ADDR: | |
494 | addr = rtas_ld(args, 0); | |
46c5874e | 495 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
496 | if (!pdev) { |
497 | goto param_error_exit; | |
498 | } | |
499 | ||
500 | rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); | |
501 | break; | |
502 | case RTAS_GET_PE_MODE: | |
503 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
504 | break; | |
505 | default: | |
506 | goto param_error_exit; | |
507 | } | |
508 | ||
509 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
510 | return; | |
511 | ||
512 | param_error_exit: | |
513 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
514 | } | |
515 | ||
516 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
28e02042 | 517 | sPAPRMachineState *spapr, |
ee954280 GS |
518 | uint32_t token, uint32_t nargs, |
519 | target_ulong args, uint32_t nret, | |
520 | target_ulong rets) | |
521 | { | |
522 | sPAPRPHBState *sphb; | |
523 | sPAPRPHBClass *spc; | |
524 | uint64_t buid; | |
525 | int state, ret; | |
526 | ||
527 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
528 | goto param_error_exit; | |
529 | } | |
530 | ||
531 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 532 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
533 | if (!sphb) { |
534 | goto param_error_exit; | |
535 | } | |
536 | ||
537 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
538 | if (!spc->eeh_get_state) { | |
539 | goto param_error_exit; | |
540 | } | |
541 | ||
542 | ret = spc->eeh_get_state(sphb, &state); | |
543 | rtas_st(rets, 0, ret); | |
544 | if (ret != RTAS_OUT_SUCCESS) { | |
545 | return; | |
546 | } | |
547 | ||
548 | rtas_st(rets, 1, state); | |
549 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
550 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
551 | if (nret >= 5) { | |
552 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
553 | } | |
554 | return; | |
555 | ||
556 | param_error_exit: | |
557 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
558 | } | |
559 | ||
560 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
28e02042 | 561 | sPAPRMachineState *spapr, |
ee954280 GS |
562 | uint32_t token, uint32_t nargs, |
563 | target_ulong args, uint32_t nret, | |
564 | target_ulong rets) | |
565 | { | |
566 | sPAPRPHBState *sphb; | |
567 | sPAPRPHBClass *spc; | |
568 | uint32_t option; | |
569 | uint64_t buid; | |
570 | int ret; | |
571 | ||
572 | if ((nargs != 4) || (nret != 1)) { | |
573 | goto param_error_exit; | |
574 | } | |
575 | ||
576 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
577 | option = rtas_ld(args, 3); | |
46c5874e | 578 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
579 | if (!sphb) { |
580 | goto param_error_exit; | |
581 | } | |
582 | ||
583 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
584 | if (!spc->eeh_reset) { | |
585 | goto param_error_exit; | |
586 | } | |
587 | ||
588 | ret = spc->eeh_reset(sphb, option); | |
589 | rtas_st(rets, 0, ret); | |
590 | return; | |
591 | ||
592 | param_error_exit: | |
593 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
594 | } | |
595 | ||
596 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
28e02042 | 597 | sPAPRMachineState *spapr, |
ee954280 GS |
598 | uint32_t token, uint32_t nargs, |
599 | target_ulong args, uint32_t nret, | |
600 | target_ulong rets) | |
601 | { | |
602 | sPAPRPHBState *sphb; | |
603 | sPAPRPHBClass *spc; | |
604 | uint64_t buid; | |
605 | int ret; | |
606 | ||
607 | if ((nargs != 3) || (nret != 1)) { | |
608 | goto param_error_exit; | |
609 | } | |
610 | ||
611 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 612 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
613 | if (!sphb) { |
614 | goto param_error_exit; | |
615 | } | |
616 | ||
617 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
618 | if (!spc->eeh_configure) { | |
619 | goto param_error_exit; | |
620 | } | |
621 | ||
622 | ret = spc->eeh_configure(sphb); | |
623 | rtas_st(rets, 0, ret); | |
624 | return; | |
625 | ||
626 | param_error_exit: | |
627 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
628 | } | |
629 | ||
630 | /* To support it later */ | |
631 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
28e02042 | 632 | sPAPRMachineState *spapr, |
ee954280 GS |
633 | uint32_t token, uint32_t nargs, |
634 | target_ulong args, uint32_t nret, | |
635 | target_ulong rets) | |
636 | { | |
637 | sPAPRPHBState *sphb; | |
638 | sPAPRPHBClass *spc; | |
639 | int option; | |
640 | uint64_t buid; | |
641 | ||
642 | if ((nargs != 8) || (nret != 1)) { | |
643 | goto param_error_exit; | |
644 | } | |
645 | ||
646 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 647 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
648 | if (!sphb) { |
649 | goto param_error_exit; | |
650 | } | |
651 | ||
652 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
653 | if (!spc->eeh_set_option) { | |
654 | goto param_error_exit; | |
655 | } | |
656 | ||
657 | option = rtas_ld(args, 7); | |
658 | switch (option) { | |
659 | case RTAS_SLOT_TEMP_ERR_LOG: | |
660 | case RTAS_SLOT_PERM_ERR_LOG: | |
661 | break; | |
662 | default: | |
663 | goto param_error_exit; | |
664 | } | |
665 | ||
666 | /* We don't have error log yet */ | |
667 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
668 | return; | |
669 | ||
670 | param_error_exit: | |
671 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
672 | } | |
673 | ||
7fb0bd34 DG |
674 | static int pci_spapr_swizzle(int slot, int pin) |
675 | { | |
676 | return (slot + pin) % PCI_NUM_PINS; | |
677 | } | |
678 | ||
3384f95c DG |
679 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
680 | { | |
681 | /* | |
682 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
683 | * which is less than number of IRQs on the specific bus (4). We |
684 | * use standard PCI swizzling, that is (slot number + pin number) | |
685 | * % 4. | |
3384f95c | 686 | */ |
7fb0bd34 | 687 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
688 | } |
689 | ||
690 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
691 | { | |
692 | /* | |
693 | * Here we use the number returned by pci_spapr_map_irq to find a | |
694 | * corresponding qemu_irq. | |
695 | */ | |
696 | sPAPRPHBState *phb = opaque; | |
697 | ||
caae58cb | 698 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 699 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
700 | } |
701 | ||
5cc7a967 AK |
702 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
703 | { | |
704 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); | |
705 | PCIINTxRoute route; | |
706 | ||
707 | route.mode = PCI_INTX_ENABLED; | |
708 | route.irq = sphb->lsi_table[pin].irq; | |
709 | ||
710 | return route; | |
711 | } | |
712 | ||
0ee2c058 AK |
713 | /* |
714 | * MSI/MSIX memory region implementation. | |
715 | * The handler handles both MSI and MSIX. | |
716 | * For MSI-X, the vector number is encoded as a part of the address, | |
717 | * data is set to 0. | |
718 | * For MSI, the vector number is encoded in least bits in data. | |
719 | */ | |
a8170e5e | 720 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
721 | uint64_t data, unsigned size) |
722 | { | |
28e02042 | 723 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
f1c2dc7c | 724 | uint32_t irq = data; |
0ee2c058 AK |
725 | |
726 | trace_spapr_pci_msi_write(addr, data, irq); | |
727 | ||
728 | qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); | |
729 | } | |
730 | ||
731 | static const MemoryRegionOps spapr_msi_ops = { | |
732 | /* There is no .read as the read result is undefined by PCI spec */ | |
733 | .read = NULL, | |
734 | .write = spapr_msi_write, | |
735 | .endianness = DEVICE_LITTLE_ENDIAN | |
736 | }; | |
737 | ||
298a9710 DG |
738 | /* |
739 | * PHB PCI device | |
740 | */ | |
e00387d5 | 741 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
742 | { |
743 | sPAPRPHBState *phb = opaque; | |
744 | ||
e00387d5 | 745 | return &phb->iommu_as; |
edded454 DG |
746 | } |
747 | ||
7454c7af MR |
748 | /* Macros to operate with address in OF binding to PCI */ |
749 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
750 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
751 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
752 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
753 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
754 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
755 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
756 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
757 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
758 | ||
759 | /* for 'reg'/'assigned-addresses' OF properties */ | |
760 | #define RESOURCE_CELLS_SIZE 2 | |
761 | #define RESOURCE_CELLS_ADDRESS 3 | |
762 | ||
763 | typedef struct ResourceFields { | |
764 | uint32_t phys_hi; | |
765 | uint32_t phys_mid; | |
766 | uint32_t phys_lo; | |
767 | uint32_t size_hi; | |
768 | uint32_t size_lo; | |
769 | } QEMU_PACKED ResourceFields; | |
770 | ||
771 | typedef struct ResourceProps { | |
772 | ResourceFields reg[8]; | |
773 | ResourceFields assigned[7]; | |
774 | uint32_t reg_len; | |
775 | uint32_t assigned_len; | |
776 | } ResourceProps; | |
777 | ||
778 | /* fill in the 'reg'/'assigned-resources' OF properties for | |
779 | * a PCI device. 'reg' describes resource requirements for a | |
780 | * device's IO/MEM regions, 'assigned-addresses' describes the | |
781 | * actual resource assignments. | |
782 | * | |
783 | * the properties are arrays of ('phys-addr', 'size') pairs describing | |
784 | * the addressable regions of the PCI device, where 'phys-addr' is a | |
785 | * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to | |
786 | * (phys.hi, phys.mid, phys.lo), and 'size' is a | |
787 | * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). | |
788 | * | |
789 | * phys.hi = 0xYYXXXXZZ, where: | |
790 | * 0xYY = npt000ss | |
791 | * ||| | | |
72187935 ND |
792 | * ||| +-- space code |
793 | * ||| | | |
794 | * ||| + 00 if configuration space | |
795 | * ||| + 01 if IO region, | |
796 | * ||| + 10 if 32-bit MEM region | |
797 | * ||| + 11 if 64-bit MEM region | |
798 | * ||| | |
7454c7af MR |
799 | * ||+------ for non-relocatable IO: 1 if aliased |
800 | * || for relocatable IO: 1 if below 64KB | |
801 | * || for MEM: 1 if below 1MB | |
802 | * |+------- 1 if region is prefetchable | |
803 | * +-------- 1 if region is non-relocatable | |
804 | * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function | |
805 | * bits respectively | |
806 | * 0xZZ = rrrrrrrr, the register number of the BAR corresponding | |
807 | * to the region | |
808 | * | |
809 | * phys.mid and phys.lo correspond respectively to the hi/lo portions | |
810 | * of the actual address of the region. | |
811 | * | |
812 | * how the phys-addr/size values are used differ slightly between | |
813 | * 'reg' and 'assigned-addresses' properties. namely, 'reg' has | |
814 | * an additional description for the config space region of the | |
815 | * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 | |
816 | * to describe the region as relocatable, with an address-mapping | |
817 | * that corresponds directly to the PHB's address space for the | |
818 | * resource. 'assigned-addresses' always has n=1 set with an absolute | |
819 | * address assigned for the resource. in general, 'assigned-addresses' | |
820 | * won't be populated, since addresses for PCI devices are generally | |
821 | * unmapped initially and left to the guest to assign. | |
822 | * | |
823 | * note also that addresses defined in these properties are, at least | |
824 | * for PAPR guests, relative to the PHBs IO/MEM windows, and | |
825 | * correspond directly to the addresses in the BARs. | |
826 | * | |
827 | * in accordance with PCI Bus Binding to Open Firmware, | |
828 | * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, | |
829 | * Appendix C. | |
830 | */ | |
831 | static void populate_resource_props(PCIDevice *d, ResourceProps *rp) | |
832 | { | |
833 | int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); | |
834 | uint32_t dev_id = (b_bbbbbbbb(bus_num) | | |
835 | b_ddddd(PCI_SLOT(d->devfn)) | | |
836 | b_fff(PCI_FUNC(d->devfn))); | |
837 | ResourceFields *reg, *assigned; | |
838 | int i, reg_idx = 0, assigned_idx = 0; | |
839 | ||
840 | /* config space region */ | |
841 | reg = &rp->reg[reg_idx++]; | |
842 | reg->phys_hi = cpu_to_be32(dev_id); | |
843 | reg->phys_mid = 0; | |
844 | reg->phys_lo = 0; | |
845 | reg->size_hi = 0; | |
846 | reg->size_lo = 0; | |
847 | ||
848 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
849 | if (!d->io_regions[i].size) { | |
850 | continue; | |
851 | } | |
852 | ||
853 | reg = &rp->reg[reg_idx++]; | |
854 | ||
855 | reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); | |
856 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
857 | reg->phys_hi |= cpu_to_be32(b_ss(1)); | |
72187935 ND |
858 | } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
859 | reg->phys_hi |= cpu_to_be32(b_ss(3)); | |
7454c7af MR |
860 | } else { |
861 | reg->phys_hi |= cpu_to_be32(b_ss(2)); | |
862 | } | |
863 | reg->phys_mid = 0; | |
864 | reg->phys_lo = 0; | |
865 | reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); | |
866 | reg->size_lo = cpu_to_be32(d->io_regions[i].size); | |
867 | ||
868 | if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { | |
869 | continue; | |
870 | } | |
871 | ||
872 | assigned = &rp->assigned[assigned_idx++]; | |
873 | assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); | |
874 | assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); | |
875 | assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); | |
876 | assigned->size_hi = reg->size_hi; | |
877 | assigned->size_lo = reg->size_lo; | |
878 | } | |
879 | ||
880 | rp->reg_len = reg_idx * sizeof(ResourceFields); | |
881 | rp->assigned_len = assigned_idx * sizeof(ResourceFields); | |
882 | } | |
883 | ||
884 | static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, | |
885 | int phb_index, int drc_index, | |
886 | const char *drc_name) | |
887 | { | |
888 | ResourceProps rp; | |
889 | bool is_bridge = false; | |
890 | int pci_status; | |
891 | ||
892 | if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == | |
893 | PCI_HEADER_TYPE_BRIDGE) { | |
894 | is_bridge = true; | |
895 | } | |
896 | ||
897 | /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ | |
898 | _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", | |
899 | pci_default_read_config(dev, PCI_VENDOR_ID, 2))); | |
900 | _FDT(fdt_setprop_cell(fdt, offset, "device-id", | |
901 | pci_default_read_config(dev, PCI_DEVICE_ID, 2))); | |
902 | _FDT(fdt_setprop_cell(fdt, offset, "revision-id", | |
903 | pci_default_read_config(dev, PCI_REVISION_ID, 1))); | |
904 | _FDT(fdt_setprop_cell(fdt, offset, "class-code", | |
4a7c3474 | 905 | pci_default_read_config(dev, PCI_CLASS_PROG, 3))); |
7454c7af MR |
906 | if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { |
907 | _FDT(fdt_setprop_cell(fdt, offset, "interrupts", | |
908 | pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); | |
909 | } | |
910 | ||
911 | if (!is_bridge) { | |
912 | _FDT(fdt_setprop_cell(fdt, offset, "min-grant", | |
913 | pci_default_read_config(dev, PCI_MIN_GNT, 1))); | |
914 | _FDT(fdt_setprop_cell(fdt, offset, "max-latency", | |
915 | pci_default_read_config(dev, PCI_MAX_LAT, 1))); | |
916 | } | |
917 | ||
918 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { | |
919 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", | |
920 | pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); | |
921 | } | |
922 | ||
923 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { | |
924 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", | |
925 | pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); | |
926 | } | |
927 | ||
928 | _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", | |
929 | pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); | |
930 | ||
931 | /* the following fdt cells are masked off the pci status register */ | |
932 | pci_status = pci_default_read_config(dev, PCI_STATUS, 2); | |
933 | _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", | |
934 | PCI_STATUS_DEVSEL_MASK & pci_status)); | |
935 | ||
936 | if (pci_status & PCI_STATUS_FAST_BACK) { | |
937 | _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); | |
938 | } | |
939 | if (pci_status & PCI_STATUS_66MHZ) { | |
940 | _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); | |
941 | } | |
942 | if (pci_status & PCI_STATUS_UDF) { | |
943 | _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); | |
944 | } | |
945 | ||
946 | /* NOTE: this is normally generated by firmware via path/unit name, | |
947 | * but in our case we must set it manually since it does not get | |
948 | * processed by OF beforehand | |
949 | */ | |
950 | _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); | |
951 | _FDT(fdt_setprop(fdt, offset, "ibm,loc-code", drc_name, strlen(drc_name))); | |
952 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); | |
953 | ||
954 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", | |
955 | RESOURCE_CELLS_ADDRESS)); | |
956 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", | |
957 | RESOURCE_CELLS_SIZE)); | |
958 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", | |
959 | RESOURCE_CELLS_SIZE)); | |
960 | ||
961 | populate_resource_props(dev, &rp); | |
962 | _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); | |
963 | _FDT(fdt_setprop(fdt, offset, "assigned-addresses", | |
964 | (uint8_t *)rp.assigned, rp.assigned_len)); | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
969 | /* create OF node for pci device and required OF DT properties */ | |
970 | static void *spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, | |
971 | int drc_index, const char *drc_name, | |
972 | int *dt_offset) | |
973 | { | |
974 | void *fdt; | |
975 | int offset, ret, fdt_size; | |
976 | int slot = PCI_SLOT(dev->devfn); | |
977 | int func = PCI_FUNC(dev->devfn); | |
9b7d9284 | 978 | char nodename[FDT_NAME_MAX]; |
7454c7af MR |
979 | |
980 | fdt = create_device_tree(&fdt_size); | |
981 | if (func != 0) { | |
9b7d9284 | 982 | snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); |
7454c7af | 983 | } else { |
9b7d9284 | 984 | snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); |
7454c7af MR |
985 | } |
986 | offset = fdt_add_subnode(fdt, 0, nodename); | |
987 | ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb->index, drc_index, | |
988 | drc_name); | |
989 | g_assert(!ret); | |
990 | ||
991 | *dt_offset = offset; | |
992 | return fdt; | |
993 | } | |
994 | ||
995 | static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, | |
996 | sPAPRPHBState *phb, | |
997 | PCIDevice *pdev, | |
998 | Error **errp) | |
999 | { | |
1000 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1001 | DeviceState *dev = DEVICE(pdev); | |
1002 | int drc_index = drck->get_index(drc); | |
1003 | const char *drc_name = drck->get_name(drc); | |
1004 | void *fdt = NULL; | |
1005 | int fdt_start_offset = 0; | |
1006 | ||
1007 | /* boot-time devices get their device tree node created by SLOF, but for | |
1008 | * hotplugged devices we need QEMU to generate it so the guest can fetch | |
1009 | * it via RTAS | |
1010 | */ | |
1011 | if (dev->hotplugged) { | |
1012 | fdt = spapr_create_pci_child_dt(phb, pdev, drc_index, drc_name, | |
1013 | &fdt_start_offset); | |
1014 | } | |
1015 | ||
1016 | drck->attach(drc, DEVICE(pdev), | |
1017 | fdt, fdt_start_offset, !dev->hotplugged, errp); | |
1018 | if (*errp) { | |
1019 | g_free(fdt); | |
1020 | } | |
1021 | } | |
1022 | ||
1023 | static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) | |
1024 | { | |
1025 | /* some version guests do not wait for completion of a device | |
1026 | * cleanup (generally done asynchronously by the kernel) before | |
1027 | * signaling to QEMU that the device is safe, but instead sleep | |
1028 | * for some 'safe' period of time. unfortunately on a busy host | |
1029 | * this sleep isn't guaranteed to be long enough, resulting in | |
1030 | * bad things like IRQ lines being left asserted during final | |
1031 | * device removal. to deal with this we call reset just prior | |
1032 | * to finalizing the device, which will put the device back into | |
1033 | * an 'idle' state, as the device cleanup code expects. | |
1034 | */ | |
1035 | pci_device_reset(PCI_DEVICE(dev)); | |
1036 | object_unparent(OBJECT(dev)); | |
1037 | } | |
1038 | ||
1039 | static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, | |
1040 | sPAPRPHBState *phb, | |
1041 | PCIDevice *pdev, | |
1042 | Error **errp) | |
1043 | { | |
1044 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1045 | ||
1046 | drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); | |
1047 | } | |
1048 | ||
1049 | static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, | |
1050 | PCIDevice *pdev) | |
1051 | { | |
1052 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
1053 | return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, | |
1054 | (phb->index << 16) | | |
1055 | (busnr << 8) | | |
1056 | pdev->devfn); | |
1057 | } | |
1058 | ||
1059 | static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, | |
1060 | DeviceState *plugged_dev, Error **errp) | |
1061 | { | |
1062 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1063 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1064 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1065 | Error *local_err = NULL; | |
1066 | ||
1067 | /* if DR is disabled we don't need to do anything in the case of | |
1068 | * hotplug or coldplug callbacks | |
1069 | */ | |
1070 | if (!phb->dr_enabled) { | |
1071 | /* if this is a hotplug operation initiated by the user | |
1072 | * we need to let them know it's not enabled | |
1073 | */ | |
1074 | if (plugged_dev->hotplugged) { | |
c6bd8c70 MA |
1075 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1076 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1077 | } |
1078 | return; | |
1079 | } | |
1080 | ||
1081 | g_assert(drc); | |
1082 | ||
1083 | spapr_phb_add_pci_device(drc, phb, pdev, &local_err); | |
1084 | if (local_err) { | |
1085 | error_propagate(errp, local_err); | |
1086 | return; | |
1087 | } | |
c5bc152b TD |
1088 | if (plugged_dev->hotplugged) { |
1089 | spapr_hotplug_req_add_event(drc); | |
1090 | } | |
7454c7af MR |
1091 | } |
1092 | ||
1093 | static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, | |
1094 | DeviceState *plugged_dev, Error **errp) | |
1095 | { | |
1096 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1097 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1098 | sPAPRDRConnectorClass *drck; | |
1099 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1100 | Error *local_err = NULL; | |
1101 | ||
1102 | if (!phb->dr_enabled) { | |
c6bd8c70 MA |
1103 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1104 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1105 | return; |
1106 | } | |
1107 | ||
1108 | g_assert(drc); | |
1109 | ||
1110 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1111 | if (!drck->release_pending(drc)) { | |
1112 | spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); | |
1113 | if (local_err) { | |
1114 | error_propagate(errp, local_err); | |
1115 | return; | |
1116 | } | |
c5bc152b | 1117 | spapr_hotplug_req_remove_event(drc); |
7454c7af MR |
1118 | } |
1119 | } | |
1120 | ||
c6ba42f6 | 1121 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 1122 | { |
28e02042 | 1123 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
c6ba42f6 | 1124 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
8c9f64df | 1125 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 1126 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
da6ccee4 | 1127 | sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); |
298a9710 DG |
1128 | char *namebuf; |
1129 | int i; | |
3384f95c | 1130 | PCIBus *bus; |
8c46f7ec | 1131 | uint64_t msi_window_size = 4096; |
3384f95c | 1132 | |
421b1b27 | 1133 | if (sphb->index != (uint32_t)-1) { |
caae58cb DG |
1134 | hwaddr windows_base; |
1135 | ||
421b1b27 DG |
1136 | if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) |
1137 | || (sphb->mem_win_addr != (hwaddr)-1) | |
1138 | || (sphb->io_win_addr != (hwaddr)-1)) { | |
c6ba42f6 AK |
1139 | error_setg(errp, "Either \"index\" or other parameters must" |
1140 | " be specified for PAPR PHB, not both"); | |
1141 | return; | |
caae58cb DG |
1142 | } |
1143 | ||
3e4ac968 DG |
1144 | if (sphb->index > SPAPR_PCI_MAX_INDEX) { |
1145 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
1146 | SPAPR_PCI_MAX_INDEX); | |
1147 | return; | |
1148 | } | |
1149 | ||
caae58cb | 1150 | sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; |
c8545818 | 1151 | sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); |
caae58cb DG |
1152 | |
1153 | windows_base = SPAPR_PCI_WINDOW_BASE | |
1154 | + sphb->index * SPAPR_PCI_WINDOW_SPACING; | |
1155 | sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; | |
1156 | sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; | |
caae58cb DG |
1157 | } |
1158 | ||
421b1b27 | 1159 | if (sphb->buid == (uint64_t)-1) { |
c6ba42f6 AK |
1160 | error_setg(errp, "BUID not specified for PHB"); |
1161 | return; | |
caae58cb DG |
1162 | } |
1163 | ||
421b1b27 | 1164 | if (sphb->dma_liobn == (uint32_t)-1) { |
c6ba42f6 AK |
1165 | error_setg(errp, "LIOBN not specified for PHB"); |
1166 | return; | |
caae58cb DG |
1167 | } |
1168 | ||
421b1b27 | 1169 | if (sphb->mem_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1170 | error_setg(errp, "Memory window address not specified for PHB"); |
1171 | return; | |
caae58cb DG |
1172 | } |
1173 | ||
421b1b27 | 1174 | if (sphb->io_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1175 | error_setg(errp, "IO window address not specified for PHB"); |
1176 | return; | |
caae58cb DG |
1177 | } |
1178 | ||
46c5874e | 1179 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
c6ba42f6 AK |
1180 | error_setg(errp, "PCI host bridges must have unique BUIDs"); |
1181 | return; | |
caae58cb DG |
1182 | } |
1183 | ||
8c9f64df | 1184 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 1185 | |
8c9f64df | 1186 | namebuf = alloca(strlen(sphb->dtbusname) + 32); |
3384f95c | 1187 | |
298a9710 | 1188 | /* Initialize memory regions */ |
8c9f64df | 1189 | sprintf(namebuf, "%s.mmio", sphb->dtbusname); |
92b8e39c | 1190 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
3384f95c | 1191 | |
8c9f64df | 1192 | sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); |
40c5dce9 PB |
1193 | memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), |
1194 | namebuf, &sphb->memspace, | |
8c9f64df AF |
1195 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
1196 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, | |
1197 | &sphb->memwindow); | |
3384f95c | 1198 | |
fabe9ee1 | 1199 | /* Initialize IO regions */ |
8c9f64df | 1200 | sprintf(namebuf, "%s.io", sphb->dtbusname); |
40c5dce9 PB |
1201 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
1202 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
3384f95c | 1203 | |
a3cfa18e | 1204 | sprintf(namebuf, "%s.io-alias", sphb->dtbusname); |
66aab867 | 1205 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 1206 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
8c9f64df | 1207 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 1208 | &sphb->iowindow); |
1b8601b0 AK |
1209 | |
1210 | bus = pci_register_bus(dev, NULL, | |
8c9f64df AF |
1211 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, |
1212 | &sphb->memspace, &sphb->iospace, | |
60a0e443 | 1213 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); |
8c9f64df | 1214 | phb->bus = bus; |
7454c7af | 1215 | qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); |
298a9710 | 1216 | |
cca7fad5 AK |
1217 | /* |
1218 | * Initialize PHB address space. | |
1219 | * By default there will be at least one subregion for default | |
1220 | * 32bit DMA window. | |
1221 | * Later the guest might want to create another DMA window | |
1222 | * which will become another memory subregion. | |
1223 | */ | |
1224 | sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); | |
1225 | ||
1226 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), | |
1227 | namebuf, UINT64_MAX); | |
1228 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, | |
1229 | sphb->dtbusname); | |
1230 | ||
8c46f7ec GK |
1231 | /* |
1232 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
1233 | * we need to allocate some memory to catch those writes coming | |
1234 | * from msi_notify()/msix_notify(). | |
1235 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
1236 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
1237 | * be used. | |
1238 | * | |
1239 | * For KVM we want to ensure that this memory is a full page so that | |
1240 | * our memory slot is of page size granularity. | |
1241 | */ | |
1242 | #ifdef CONFIG_KVM | |
1243 | if (kvm_enabled()) { | |
1244 | msi_window_size = getpagesize(); | |
1245 | } | |
1246 | #endif | |
1247 | ||
1248 | memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, | |
1249 | "msi", msi_window_size); | |
1250 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
1251 | &sphb->msiwindow); | |
1252 | ||
e00387d5 | 1253 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 1254 | |
5cc7a967 AK |
1255 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
1256 | ||
8c9f64df | 1257 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
1258 | |
1259 | /* Initialize the LSI table */ | |
7fb0bd34 | 1260 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 1261 | uint32_t irq; |
298a9710 | 1262 | |
bee763db | 1263 | irq = xics_alloc_block(spapr->icp, 0, 1, true, false); |
a307d594 | 1264 | if (!irq) { |
c6ba42f6 AK |
1265 | error_setg(errp, "spapr_allocate_lsi failed"); |
1266 | return; | |
298a9710 DG |
1267 | } |
1268 | ||
8c9f64df | 1269 | sphb->lsi_table[i].irq = irq; |
298a9710 | 1270 | } |
da6ccee4 | 1271 | |
62083979 MR |
1272 | /* allocate connectors for child PCI devices */ |
1273 | if (sphb->dr_enabled) { | |
1274 | for (i = 0; i < PCI_SLOT_MAX * 8; i++) { | |
1275 | spapr_dr_connector_new(OBJECT(phb), | |
1276 | SPAPR_DR_CONNECTOR_TYPE_PCI, | |
1277 | (sphb->index << 16) | i); | |
1278 | } | |
1279 | } | |
1280 | ||
da6ccee4 AK |
1281 | if (!info->finish_realize) { |
1282 | error_setg(errp, "finish_realize not defined"); | |
1283 | return; | |
1284 | } | |
1285 | ||
1286 | info->finish_realize(sphb, errp); | |
9a321e92 AK |
1287 | |
1288 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); | |
da6ccee4 AK |
1289 | } |
1290 | ||
1291 | static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) | |
1292 | { | |
e28c16f6 | 1293 | sPAPRTCETable *tcet; |
3e1a01cb | 1294 | uint32_t nb_table; |
e28c16f6 | 1295 | |
3e1a01cb | 1296 | nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; |
e28c16f6 | 1297 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, |
3e1a01cb | 1298 | 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); |
e28c16f6 | 1299 | if (!tcet) { |
da6ccee4 AK |
1300 | error_setg(errp, "Unable to create TCE table for %s", |
1301 | sphb->dtbusname); | |
1302 | return ; | |
1303 | } | |
cca7fad5 AK |
1304 | |
1305 | /* Register default 32bit DMA window */ | |
1306 | memory_region_add_subregion(&sphb->iommu_root, 0, | |
e28c16f6 | 1307 | spapr_tce_get_iommu(tcet)); |
298a9710 DG |
1308 | } |
1309 | ||
e28c16f6 | 1310 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 1311 | { |
e28c16f6 AK |
1312 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
1313 | ||
1314 | if (dev) { | |
1315 | device_reset(dev); | |
1316 | } | |
eddeed26 | 1317 | |
e28c16f6 AK |
1318 | return 0; |
1319 | } | |
1320 | ||
1321 | static void spapr_phb_reset(DeviceState *qdev) | |
1322 | { | |
eddeed26 | 1323 | /* Reset the IOMMU state */ |
e28c16f6 | 1324 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
eddeed26 DG |
1325 | } |
1326 | ||
298a9710 | 1327 | static Property spapr_phb_properties[] = { |
3e4ac968 | 1328 | DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), |
c7bcc85d PB |
1329 | DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), |
1330 | DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), | |
1331 | DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), | |
1332 | DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, | |
1333 | SPAPR_PCI_MMIO_WIN_SIZE), | |
1334 | DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), | |
1335 | DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, | |
1336 | SPAPR_PCI_IO_WIN_SIZE), | |
7619c7b0 MR |
1337 | DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, |
1338 | true), | |
298a9710 DG |
1339 | DEFINE_PROP_END_OF_LIST(), |
1340 | }; | |
1341 | ||
1112cf94 DG |
1342 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
1343 | .name = "spapr_pci/lsi", | |
1344 | .version_id = 1, | |
1345 | .minimum_version_id = 1, | |
3aff6c2f | 1346 | .fields = (VMStateField[]) { |
1112cf94 DG |
1347 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), |
1348 | ||
1349 | VMSTATE_END_OF_LIST() | |
1350 | }, | |
1351 | }; | |
1352 | ||
1353 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 1354 | .name = "spapr_pci/msi", |
1112cf94 DG |
1355 | .version_id = 1, |
1356 | .minimum_version_id = 1, | |
9a321e92 AK |
1357 | .fields = (VMStateField []) { |
1358 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
1359 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
1360 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
1361 | VMSTATE_END_OF_LIST() |
1362 | }, | |
1363 | }; | |
1364 | ||
9a321e92 AK |
1365 | static void spapr_pci_pre_save(void *opaque) |
1366 | { | |
1367 | sPAPRPHBState *sphb = opaque; | |
708414f0 MA |
1368 | GHashTableIter iter; |
1369 | gpointer key, value; | |
1370 | int i; | |
9a321e92 AK |
1371 | |
1372 | if (sphb->msi_devs) { | |
1373 | g_free(sphb->msi_devs); | |
1374 | sphb->msi_devs = NULL; | |
1375 | } | |
708414f0 MA |
1376 | sphb->msi_devs_num = g_hash_table_size(sphb->msi); |
1377 | if (!sphb->msi_devs_num) { | |
9a321e92 AK |
1378 | return; |
1379 | } | |
708414f0 | 1380 | sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); |
9a321e92 | 1381 | |
708414f0 MA |
1382 | g_hash_table_iter_init(&iter, sphb->msi); |
1383 | for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { | |
1384 | sphb->msi_devs[i].key = *(uint32_t *) key; | |
1385 | sphb->msi_devs[i].value = *(spapr_pci_msi *) value; | |
1386 | } | |
9a321e92 AK |
1387 | } |
1388 | ||
1389 | static int spapr_pci_post_load(void *opaque, int version_id) | |
1390 | { | |
1391 | sPAPRPHBState *sphb = opaque; | |
1392 | gpointer key, value; | |
1393 | int i; | |
1394 | ||
1395 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
1396 | key = g_memdup(&sphb->msi_devs[i].key, | |
1397 | sizeof(sphb->msi_devs[i].key)); | |
1398 | value = g_memdup(&sphb->msi_devs[i].value, | |
1399 | sizeof(sphb->msi_devs[i].value)); | |
1400 | g_hash_table_insert(sphb->msi, key, value); | |
1401 | } | |
1402 | if (sphb->msi_devs) { | |
1403 | g_free(sphb->msi_devs); | |
1404 | sphb->msi_devs = NULL; | |
1405 | } | |
1406 | sphb->msi_devs_num = 0; | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
1112cf94 DG |
1411 | static const VMStateDescription vmstate_spapr_pci = { |
1412 | .name = "spapr_pci", | |
9a321e92 AK |
1413 | .version_id = 2, |
1414 | .minimum_version_id = 2, | |
1415 | .pre_save = spapr_pci_pre_save, | |
1416 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 1417 | .fields = (VMStateField[]) { |
1112cf94 DG |
1418 | VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), |
1419 | VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), | |
1420 | VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), | |
1421 | VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), | |
1422 | VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), | |
1423 | VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), | |
1112cf94 DG |
1424 | VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, |
1425 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), | |
9a321e92 AK |
1426 | VMSTATE_INT32(msi_devs_num, sPAPRPHBState), |
1427 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, | |
1428 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), | |
1112cf94 DG |
1429 | VMSTATE_END_OF_LIST() |
1430 | }, | |
1431 | }; | |
1432 | ||
568f0690 DG |
1433 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
1434 | PCIBus *rootbus) | |
1435 | { | |
1436 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
1437 | ||
1438 | return sphb->dtbusname; | |
1439 | } | |
1440 | ||
298a9710 DG |
1441 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
1442 | { | |
568f0690 | 1443 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 1444 | DeviceClass *dc = DEVICE_CLASS(klass); |
da6ccee4 | 1445 | sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); |
7454c7af | 1446 | HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); |
298a9710 | 1447 | |
568f0690 | 1448 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 1449 | dc->realize = spapr_phb_realize; |
298a9710 | 1450 | dc->props = spapr_phb_properties; |
eddeed26 | 1451 | dc->reset = spapr_phb_reset; |
1112cf94 | 1452 | dc->vmsd = &vmstate_spapr_pci; |
09aa9a52 AK |
1453 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
1454 | dc->cannot_instantiate_with_device_add_yet = false; | |
da6ccee4 | 1455 | spc->finish_realize = spapr_phb_finish_realize; |
7454c7af MR |
1456 | hp->plug = spapr_phb_hot_plug_child; |
1457 | hp->unplug = spapr_phb_hot_unplug_child; | |
298a9710 | 1458 | } |
3384f95c | 1459 | |
4240abff | 1460 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 1461 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 1462 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
1463 | .instance_size = sizeof(sPAPRPHBState), |
1464 | .class_init = spapr_phb_class_init, | |
da6ccee4 | 1465 | .class_size = sizeof(sPAPRPHBClass), |
7454c7af MR |
1466 | .interfaces = (InterfaceInfo[]) { |
1467 | { TYPE_HOTPLUG_HANDLER }, | |
1468 | { } | |
1469 | } | |
298a9710 DG |
1470 | }; |
1471 | ||
28e02042 | 1472 | PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) |
298a9710 DG |
1473 | { |
1474 | DeviceState *dev; | |
1475 | ||
8c9f64df | 1476 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 1477 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 1478 | qdev_init_nofail(dev); |
caae58cb DG |
1479 | |
1480 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
1481 | } |
1482 | ||
e0fdbd7c AK |
1483 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
1484 | uint32_t xics_phandle, | |
1485 | void *fdt) | |
3384f95c | 1486 | { |
62083979 | 1487 | int bus_off, i, j, ret; |
9b7d9284 | 1488 | char nodename[FDT_NAME_MAX]; |
3384f95c | 1489 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
b194df47 AK |
1490 | const uint64_t mmiosize = memory_region_size(&phb->memwindow); |
1491 | const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; | |
1492 | const uint64_t w32size = MIN(w32max, mmiosize); | |
1493 | const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; | |
3384f95c DG |
1494 | struct { |
1495 | uint32_t hi; | |
1496 | uint64_t child; | |
1497 | uint64_t parent; | |
1498 | uint64_t size; | |
c4889f54 | 1499 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
1500 | { |
1501 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
1502 | cpu_to_be64(phb->io_win_addr), | |
1503 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
1504 | }, | |
1505 | { | |
1506 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
1507 | cpu_to_be64(phb->mem_win_addr), | |
b194df47 AK |
1508 | cpu_to_be64(w32size), |
1509 | }, | |
1510 | { | |
1511 | cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), | |
1512 | cpu_to_be64(phb->mem_win_addr + w32size), | |
1513 | cpu_to_be64(w64size) | |
3384f95c DG |
1514 | }, |
1515 | }; | |
b194df47 | 1516 | const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); |
3384f95c DG |
1517 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
1518 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
1519 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
1520 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
ccf9ff85 | 1521 | sPAPRTCETable *tcet; |
3384f95c DG |
1522 | |
1523 | /* Start populating the FDT */ | |
9b7d9284 | 1524 | snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); |
3384f95c DG |
1525 | bus_off = fdt_add_subnode(fdt, 0, nodename); |
1526 | if (bus_off < 0) { | |
1527 | return bus_off; | |
1528 | } | |
1529 | ||
3384f95c DG |
1530 | /* Write PHB properties */ |
1531 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
1532 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
1533 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
1534 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
1535 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
1536 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
1537 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 1538 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 1539 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 1540 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
9dbae977 | 1541 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); |
3384f95c | 1542 | |
4d8d5467 BH |
1543 | /* Build the interrupt-map, this must matches what is done |
1544 | * in pci_spapr_map_irq | |
1545 | */ | |
1546 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
1547 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
1548 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
1549 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
1550 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
1551 | int lsi_num = pci_spapr_swizzle(i, j); | |
1552 | ||
1553 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
1554 | irqmap[1] = 0; | |
1555 | irqmap[2] = 0; | |
1556 | irqmap[3] = cpu_to_be32(j+1); | |
1557 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 1558 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
1559 | irqmap[6] = cpu_to_be32(0x8); |
1560 | } | |
3384f95c | 1561 | } |
3384f95c DG |
1562 | /* Write interrupt map */ |
1563 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 1564 | sizeof(interrupt_map))); |
3384f95c | 1565 | |
ccf9ff85 AK |
1566 | tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); |
1567 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", | |
1568 | tcet->liobn, tcet->bus_offset, | |
1569 | tcet->nb_table << tcet->page_shift); | |
edded454 | 1570 | |
62083979 MR |
1571 | ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), |
1572 | SPAPR_DR_CONNECTOR_TYPE_PCI); | |
1573 | if (ret) { | |
1574 | return ret; | |
1575 | } | |
1576 | ||
3384f95c DG |
1577 | return 0; |
1578 | } | |
298a9710 | 1579 | |
fa28f71b AK |
1580 | void spapr_pci_rtas_init(void) |
1581 | { | |
3a3b8502 AK |
1582 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
1583 | rtas_read_pci_config); | |
1584 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
1585 | rtas_write_pci_config); | |
1586 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
1587 | rtas_ibm_read_pci_config); | |
1588 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
1589 | rtas_ibm_write_pci_config); | |
0ee2c058 | 1590 | if (msi_supported) { |
3a3b8502 AK |
1591 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
1592 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 1593 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
1594 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
1595 | rtas_ibm_change_msi); | |
0ee2c058 | 1596 | } |
ee954280 GS |
1597 | |
1598 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
1599 | "ibm,set-eeh-option", | |
1600 | rtas_ibm_set_eeh_option); | |
1601 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
1602 | "ibm,get-config-addr-info2", | |
1603 | rtas_ibm_get_config_addr_info2); | |
1604 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
1605 | "ibm,read-slot-reset-state2", | |
1606 | rtas_ibm_read_slot_reset_state2); | |
1607 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
1608 | "ibm,set-slot-reset", | |
1609 | rtas_ibm_set_slot_reset); | |
1610 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
1611 | "ibm,configure-pe", | |
1612 | rtas_ibm_configure_pe); | |
1613 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
1614 | "ibm,slot-error-detail", | |
1615 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
1616 | } |
1617 | ||
8c9f64df | 1618 | static void spapr_pci_register_types(void) |
298a9710 DG |
1619 | { |
1620 | type_register_static(&spapr_phb_info); | |
1621 | } | |
8c9f64df AF |
1622 | |
1623 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
1624 | |
1625 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
1626 | { | |
1627 | bool be = *(bool *)opaque; | |
1628 | ||
1629 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
1630 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
1631 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
1632 | &error_abort); | |
1633 | } | |
1634 | return 0; | |
1635 | } | |
1636 | ||
1637 | void spapr_pci_switch_vga(bool big_endian) | |
1638 | { | |
28e02042 | 1639 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
eefaccc0 DG |
1640 | sPAPRPHBState *sphb; |
1641 | ||
1642 | /* | |
1643 | * For backward compatibility with existing guests, we switch | |
1644 | * the endianness of the VGA controller when changing the guest | |
1645 | * interrupt mode | |
1646 | */ | |
1647 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
1648 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
1649 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
1650 | &big_endian); | |
1651 | } | |
1652 | } |