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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
83c9f4ca | 25 | #include "hw/hw.h" |
1d2d9742 | 26 | #include "hw/sysbus.h" |
83c9f4ca PB |
27 | #include "hw/pci/pci.h" |
28 | #include "hw/pci/msi.h" | |
29 | #include "hw/pci/msix.h" | |
30 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
31 | #include "hw/ppc/spapr.h" |
32 | #include "hw/pci-host/spapr.h" | |
022c62cb | 33 | #include "exec/address-spaces.h" |
3384f95c | 34 | #include <libfdt.h> |
a2950fb6 | 35 | #include "trace.h" |
295d51aa | 36 | #include "qemu/error-report.h" |
7454c7af | 37 | #include "qapi/qmp/qerror.h" |
3384f95c | 38 | |
1d2d9742 | 39 | #include "hw/pci/pci_bridge.h" |
06aac7bd | 40 | #include "hw/pci/pci_bus.h" |
62083979 | 41 | #include "hw/ppc/spapr_drc.h" |
7454c7af | 42 | #include "sysemu/device_tree.h" |
3384f95c | 43 | |
0ee2c058 AK |
44 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
45 | #define RTAS_QUERY_FN 0 | |
46 | #define RTAS_CHANGE_FN 1 | |
47 | #define RTAS_RESET_FN 2 | |
48 | #define RTAS_CHANGE_MSI_FN 3 | |
49 | #define RTAS_CHANGE_MSIX_FN 4 | |
50 | ||
51 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
52 | #define RTAS_TYPE_MSI 1 | |
53 | #define RTAS_TYPE_MSIX 2 | |
54 | ||
9b7d9284 ND |
55 | #define FDT_NAME_MAX 128 |
56 | ||
7454c7af MR |
57 | #define _FDT(exp) \ |
58 | do { \ | |
59 | int ret = (exp); \ | |
60 | if (ret < 0) { \ | |
61 | return ret; \ | |
62 | } \ | |
63 | } while (0) | |
64 | ||
28e02042 | 65 | sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) |
3384f95c | 66 | { |
8c9f64df | 67 | sPAPRPHBState *sphb; |
3384f95c | 68 | |
8c9f64df AF |
69 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
70 | if (sphb->buid != buid) { | |
3384f95c DG |
71 | continue; |
72 | } | |
8c9f64df | 73 | return sphb; |
9894c5d4 AK |
74 | } |
75 | ||
76 | return NULL; | |
77 | } | |
78 | ||
28e02042 | 79 | PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, |
46c5874e | 80 | uint32_t config_addr) |
9894c5d4 | 81 | { |
46c5874e | 82 | sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 83 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 84 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
85 | int devfn = (config_addr >> 8) & 0xFF; |
86 | ||
87 | if (!phb) { | |
88 | return NULL; | |
89 | } | |
3384f95c | 90 | |
5dac82ce | 91 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
92 | } |
93 | ||
3f7565c9 BH |
94 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
95 | { | |
92615a5a | 96 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
97 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
98 | } | |
99 | ||
28e02042 | 100 | static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
101 | uint32_t addr, uint32_t size, |
102 | target_ulong rets) | |
88045ac5 | 103 | { |
92615a5a DG |
104 | PCIDevice *pci_dev; |
105 | uint32_t val; | |
106 | ||
107 | if ((size != 1) && (size != 2) && (size != 4)) { | |
108 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 109 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 110 | return; |
88045ac5 | 111 | } |
88045ac5 | 112 | |
46c5874e | 113 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
114 | addr = rtas_pci_cfgaddr(addr); |
115 | ||
116 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
117 | /* Access must be to a valid device, within bounds and | |
118 | * naturally aligned */ | |
a64d325d | 119 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 120 | return; |
88045ac5 | 121 | } |
92615a5a DG |
122 | |
123 | val = pci_host_config_read_common(pci_dev, addr, | |
124 | pci_config_size(pci_dev), size); | |
125 | ||
a64d325d | 126 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 127 | rtas_st(rets, 1, val); |
88045ac5 AG |
128 | } |
129 | ||
28e02042 | 130 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
131 | uint32_t token, uint32_t nargs, |
132 | target_ulong args, | |
133 | uint32_t nret, target_ulong rets) | |
134 | { | |
92615a5a DG |
135 | uint64_t buid; |
136 | uint32_t size, addr; | |
3384f95c | 137 | |
92615a5a | 138 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 139 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
140 | return; |
141 | } | |
92615a5a DG |
142 | |
143 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c | 144 | size = rtas_ld(args, 3); |
92615a5a DG |
145 | addr = rtas_ld(args, 0); |
146 | ||
147 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
148 | } |
149 | ||
28e02042 | 150 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
151 | uint32_t token, uint32_t nargs, |
152 | target_ulong args, | |
153 | uint32_t nret, target_ulong rets) | |
154 | { | |
92615a5a | 155 | uint32_t size, addr; |
3384f95c | 156 | |
92615a5a | 157 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 158 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
159 | return; |
160 | } | |
92615a5a | 161 | |
3384f95c | 162 | size = rtas_ld(args, 1); |
92615a5a DG |
163 | addr = rtas_ld(args, 0); |
164 | ||
165 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
166 | } | |
167 | ||
28e02042 | 168 | static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
169 | uint32_t addr, uint32_t size, |
170 | uint32_t val, target_ulong rets) | |
171 | { | |
172 | PCIDevice *pci_dev; | |
173 | ||
174 | if ((size != 1) && (size != 2) && (size != 4)) { | |
175 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 176 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
177 | return; |
178 | } | |
179 | ||
46c5874e | 180 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
181 | addr = rtas_pci_cfgaddr(addr); |
182 | ||
183 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
184 | /* Access must be to a valid device, within bounds and | |
185 | * naturally aligned */ | |
a64d325d | 186 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
187 | return; |
188 | } | |
189 | ||
190 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
191 | val, size); | |
192 | ||
a64d325d | 193 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
194 | } |
195 | ||
28e02042 | 196 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
197 | uint32_t token, uint32_t nargs, |
198 | target_ulong args, | |
199 | uint32_t nret, target_ulong rets) | |
200 | { | |
92615a5a | 201 | uint64_t buid; |
3384f95c | 202 | uint32_t val, size, addr; |
3384f95c | 203 | |
92615a5a | 204 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 205 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
206 | return; |
207 | } | |
92615a5a DG |
208 | |
209 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c DG |
210 | val = rtas_ld(args, 4); |
211 | size = rtas_ld(args, 3); | |
92615a5a DG |
212 | addr = rtas_ld(args, 0); |
213 | ||
214 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
215 | } |
216 | ||
28e02042 | 217 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
218 | uint32_t token, uint32_t nargs, |
219 | target_ulong args, | |
220 | uint32_t nret, target_ulong rets) | |
221 | { | |
222 | uint32_t val, size, addr; | |
3384f95c | 223 | |
92615a5a | 224 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 225 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
226 | return; |
227 | } | |
92615a5a DG |
228 | |
229 | ||
3384f95c DG |
230 | val = rtas_ld(args, 2); |
231 | size = rtas_ld(args, 1); | |
92615a5a DG |
232 | addr = rtas_ld(args, 0); |
233 | ||
234 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
235 | } |
236 | ||
0ee2c058 AK |
237 | /* |
238 | * Set MSI/MSIX message data. | |
239 | * This is required for msi_notify()/msix_notify() which | |
240 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
241 | * |
242 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
243 | * table will be reset. | |
0ee2c058 | 244 | */ |
f1c2dc7c AK |
245 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
246 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
247 | { |
248 | unsigned i; | |
f1c2dc7c | 249 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
250 | |
251 | if (!msix) { | |
252 | msi_set_message(pdev, msg); | |
253 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
254 | return; | |
255 | } | |
256 | ||
9a321e92 | 257 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
258 | msix_set_message(pdev, i, msg); |
259 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
260 | if (addr) { |
261 | ++msg.data; | |
262 | } | |
0ee2c058 AK |
263 | } |
264 | } | |
265 | ||
28e02042 | 266 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
0ee2c058 AK |
267 | uint32_t token, uint32_t nargs, |
268 | target_ulong args, uint32_t nret, | |
269 | target_ulong rets) | |
270 | { | |
271 | uint32_t config_addr = rtas_ld(args, 0); | |
272 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
273 | unsigned int func = rtas_ld(args, 3); | |
274 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
275 | unsigned int seq_num = rtas_ld(args, 5); | |
276 | unsigned int ret_intr_type; | |
9a321e92 | 277 | unsigned int irq, max_irqs = 0, num = 0; |
0ee2c058 AK |
278 | sPAPRPHBState *phb = NULL; |
279 | PCIDevice *pdev = NULL; | |
9a321e92 AK |
280 | spapr_pci_msi *msi; |
281 | int *config_addr_key; | |
0ee2c058 AK |
282 | |
283 | switch (func) { | |
284 | case RTAS_CHANGE_MSI_FN: | |
285 | case RTAS_CHANGE_FN: | |
286 | ret_intr_type = RTAS_TYPE_MSI; | |
287 | break; | |
288 | case RTAS_CHANGE_MSIX_FN: | |
289 | ret_intr_type = RTAS_TYPE_MSIX; | |
290 | break; | |
291 | default: | |
295d51aa | 292 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 293 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
294 | return; |
295 | } | |
296 | ||
297 | /* Fins sPAPRPHBState */ | |
46c5874e | 298 | phb = spapr_pci_find_phb(spapr, buid); |
0ee2c058 | 299 | if (phb) { |
46c5874e | 300 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
0ee2c058 AK |
301 | } |
302 | if (!phb || !pdev) { | |
a64d325d | 303 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
304 | return; |
305 | } | |
306 | ||
307 | /* Releasing MSIs */ | |
308 | if (!req_num) { | |
9a321e92 AK |
309 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
310 | if (!msi) { | |
311 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 312 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
313 | return; |
314 | } | |
9a321e92 AK |
315 | |
316 | xics_free(spapr->icp, msi->first_irq, msi->num); | |
32420522 AK |
317 | if (msi_present(pdev)) { |
318 | spapr_msi_setmsg(pdev, 0, false, 0, num); | |
319 | } | |
320 | if (msix_present(pdev)) { | |
321 | spapr_msi_setmsg(pdev, 0, true, 0, num); | |
322 | } | |
9a321e92 AK |
323 | g_hash_table_remove(phb->msi, &config_addr); |
324 | ||
325 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 326 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
327 | rtas_st(rets, 1, 0); |
328 | return; | |
329 | } | |
330 | ||
331 | /* Enabling MSI */ | |
332 | ||
28668b5f AK |
333 | /* Check if the device supports as many IRQs as requested */ |
334 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
335 | max_irqs = msi_nr_vectors_allocated(pdev); | |
336 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
337 | max_irqs = pdev->msix_entries_nr; | |
338 | } | |
339 | if (!max_irqs) { | |
9a321e92 AK |
340 | error_report("Requested interrupt type %d is not enabled for device %x", |
341 | ret_intr_type, config_addr); | |
28668b5f AK |
342 | rtas_st(rets, 0, -1); /* Hardware error */ |
343 | return; | |
344 | } | |
345 | /* Correct the number if the guest asked for too many */ | |
346 | if (req_num > max_irqs) { | |
9a321e92 | 347 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 348 | req_num = max_irqs; |
9a321e92 AK |
349 | irq = 0; /* to avoid misleading trace */ |
350 | goto out; | |
28668b5f AK |
351 | } |
352 | ||
9a321e92 AK |
353 | /* Allocate MSIs */ |
354 | irq = xics_alloc_block(spapr->icp, 0, req_num, false, | |
355 | ret_intr_type == RTAS_TYPE_MSI); | |
356 | if (!irq) { | |
357 | error_report("Cannot allocate MSIs for device %x", config_addr); | |
a64d325d | 358 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
359 | return; |
360 | } | |
361 | ||
0ee2c058 | 362 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 363 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 364 | irq, req_num); |
0ee2c058 | 365 | |
9a321e92 AK |
366 | /* Add MSI device to cache */ |
367 | msi = g_new(spapr_pci_msi, 1); | |
368 | msi->first_irq = irq; | |
369 | msi->num = req_num; | |
370 | config_addr_key = g_new(int, 1); | |
371 | *config_addr_key = config_addr; | |
372 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
373 | ||
374 | out: | |
a64d325d | 375 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
376 | rtas_st(rets, 1, req_num); |
377 | rtas_st(rets, 2, ++seq_num); | |
378 | rtas_st(rets, 3, ret_intr_type); | |
379 | ||
9a321e92 | 380 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
381 | } |
382 | ||
210b580b | 383 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
28e02042 | 384 | sPAPRMachineState *spapr, |
0ee2c058 AK |
385 | uint32_t token, |
386 | uint32_t nargs, | |
387 | target_ulong args, | |
388 | uint32_t nret, | |
389 | target_ulong rets) | |
390 | { | |
391 | uint32_t config_addr = rtas_ld(args, 0); | |
392 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
393 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); | |
0ee2c058 | 394 | sPAPRPHBState *phb = NULL; |
9a321e92 AK |
395 | PCIDevice *pdev = NULL; |
396 | spapr_pci_msi *msi; | |
0ee2c058 | 397 | |
9a321e92 | 398 | /* Find sPAPRPHBState */ |
46c5874e | 399 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 400 | if (phb) { |
46c5874e | 401 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
402 | } |
403 | if (!phb || !pdev) { | |
a64d325d | 404 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
405 | return; |
406 | } | |
407 | ||
408 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
409 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
410 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
411 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 412 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
413 | return; |
414 | } | |
9a321e92 | 415 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
416 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
417 | intr_src_num); | |
418 | ||
a64d325d | 419 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
420 | rtas_st(rets, 1, intr_src_num); |
421 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
422 | } | |
423 | ||
ee954280 | 424 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
28e02042 | 425 | sPAPRMachineState *spapr, |
ee954280 GS |
426 | uint32_t token, uint32_t nargs, |
427 | target_ulong args, uint32_t nret, | |
428 | target_ulong rets) | |
429 | { | |
430 | sPAPRPHBState *sphb; | |
431 | sPAPRPHBClass *spc; | |
7cb18007 | 432 | PCIDevice *pdev; |
ee954280 GS |
433 | uint32_t addr, option; |
434 | uint64_t buid; | |
435 | int ret; | |
436 | ||
437 | if ((nargs != 4) || (nret != 1)) { | |
438 | goto param_error_exit; | |
439 | } | |
440 | ||
441 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
442 | addr = rtas_ld(args, 0); | |
443 | option = rtas_ld(args, 3); | |
444 | ||
46c5874e | 445 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
446 | if (!sphb) { |
447 | goto param_error_exit; | |
448 | } | |
449 | ||
7cb18007 GS |
450 | pdev = pci_find_device(PCI_HOST_BRIDGE(sphb)->bus, |
451 | (addr >> 16) & 0xFF, (addr >> 8) & 0xFF); | |
452 | if (!pdev || !object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
453 | goto param_error_exit; | |
454 | } | |
455 | ||
ee954280 GS |
456 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); |
457 | if (!spc->eeh_set_option) { | |
458 | goto param_error_exit; | |
459 | } | |
460 | ||
461 | ret = spc->eeh_set_option(sphb, addr, option); | |
462 | rtas_st(rets, 0, ret); | |
463 | return; | |
464 | ||
465 | param_error_exit: | |
466 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
467 | } | |
468 | ||
469 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
28e02042 | 470 | sPAPRMachineState *spapr, |
ee954280 GS |
471 | uint32_t token, uint32_t nargs, |
472 | target_ulong args, uint32_t nret, | |
473 | target_ulong rets) | |
474 | { | |
475 | sPAPRPHBState *sphb; | |
476 | sPAPRPHBClass *spc; | |
477 | PCIDevice *pdev; | |
478 | uint32_t addr, option; | |
479 | uint64_t buid; | |
480 | ||
481 | if ((nargs != 4) || (nret != 2)) { | |
482 | goto param_error_exit; | |
483 | } | |
484 | ||
485 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 486 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
487 | if (!sphb) { |
488 | goto param_error_exit; | |
489 | } | |
490 | ||
491 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
492 | if (!spc->eeh_set_option) { | |
493 | goto param_error_exit; | |
494 | } | |
495 | ||
496 | /* | |
497 | * We always have PE address of form "00BB0001". "BB" | |
498 | * represents the bus number of PE's primary bus. | |
499 | */ | |
500 | option = rtas_ld(args, 3); | |
501 | switch (option) { | |
502 | case RTAS_GET_PE_ADDR: | |
503 | addr = rtas_ld(args, 0); | |
46c5874e | 504 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
505 | if (!pdev) { |
506 | goto param_error_exit; | |
507 | } | |
508 | ||
509 | rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); | |
510 | break; | |
511 | case RTAS_GET_PE_MODE: | |
512 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
513 | break; | |
514 | default: | |
515 | goto param_error_exit; | |
516 | } | |
517 | ||
518 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
519 | return; | |
520 | ||
521 | param_error_exit: | |
522 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
523 | } | |
524 | ||
525 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
28e02042 | 526 | sPAPRMachineState *spapr, |
ee954280 GS |
527 | uint32_t token, uint32_t nargs, |
528 | target_ulong args, uint32_t nret, | |
529 | target_ulong rets) | |
530 | { | |
531 | sPAPRPHBState *sphb; | |
532 | sPAPRPHBClass *spc; | |
533 | uint64_t buid; | |
534 | int state, ret; | |
535 | ||
536 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
537 | goto param_error_exit; | |
538 | } | |
539 | ||
540 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 541 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
542 | if (!sphb) { |
543 | goto param_error_exit; | |
544 | } | |
545 | ||
546 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
547 | if (!spc->eeh_get_state) { | |
548 | goto param_error_exit; | |
549 | } | |
550 | ||
551 | ret = spc->eeh_get_state(sphb, &state); | |
552 | rtas_st(rets, 0, ret); | |
553 | if (ret != RTAS_OUT_SUCCESS) { | |
554 | return; | |
555 | } | |
556 | ||
557 | rtas_st(rets, 1, state); | |
558 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
559 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
560 | if (nret >= 5) { | |
561 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
562 | } | |
563 | return; | |
564 | ||
565 | param_error_exit: | |
566 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
567 | } | |
568 | ||
569 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
28e02042 | 570 | sPAPRMachineState *spapr, |
ee954280 GS |
571 | uint32_t token, uint32_t nargs, |
572 | target_ulong args, uint32_t nret, | |
573 | target_ulong rets) | |
574 | { | |
575 | sPAPRPHBState *sphb; | |
576 | sPAPRPHBClass *spc; | |
577 | uint32_t option; | |
578 | uint64_t buid; | |
579 | int ret; | |
580 | ||
581 | if ((nargs != 4) || (nret != 1)) { | |
582 | goto param_error_exit; | |
583 | } | |
584 | ||
585 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
586 | option = rtas_ld(args, 3); | |
46c5874e | 587 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
588 | if (!sphb) { |
589 | goto param_error_exit; | |
590 | } | |
591 | ||
592 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
593 | if (!spc->eeh_reset) { | |
594 | goto param_error_exit; | |
595 | } | |
596 | ||
597 | ret = spc->eeh_reset(sphb, option); | |
598 | rtas_st(rets, 0, ret); | |
599 | return; | |
600 | ||
601 | param_error_exit: | |
602 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
603 | } | |
604 | ||
605 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
28e02042 | 606 | sPAPRMachineState *spapr, |
ee954280 GS |
607 | uint32_t token, uint32_t nargs, |
608 | target_ulong args, uint32_t nret, | |
609 | target_ulong rets) | |
610 | { | |
611 | sPAPRPHBState *sphb; | |
612 | sPAPRPHBClass *spc; | |
613 | uint64_t buid; | |
614 | int ret; | |
615 | ||
616 | if ((nargs != 3) || (nret != 1)) { | |
617 | goto param_error_exit; | |
618 | } | |
619 | ||
620 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 621 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
622 | if (!sphb) { |
623 | goto param_error_exit; | |
624 | } | |
625 | ||
626 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
627 | if (!spc->eeh_configure) { | |
628 | goto param_error_exit; | |
629 | } | |
630 | ||
631 | ret = spc->eeh_configure(sphb); | |
632 | rtas_st(rets, 0, ret); | |
633 | return; | |
634 | ||
635 | param_error_exit: | |
636 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
637 | } | |
638 | ||
639 | /* To support it later */ | |
640 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
28e02042 | 641 | sPAPRMachineState *spapr, |
ee954280 GS |
642 | uint32_t token, uint32_t nargs, |
643 | target_ulong args, uint32_t nret, | |
644 | target_ulong rets) | |
645 | { | |
646 | sPAPRPHBState *sphb; | |
647 | sPAPRPHBClass *spc; | |
648 | int option; | |
649 | uint64_t buid; | |
650 | ||
651 | if ((nargs != 8) || (nret != 1)) { | |
652 | goto param_error_exit; | |
653 | } | |
654 | ||
655 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 656 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
657 | if (!sphb) { |
658 | goto param_error_exit; | |
659 | } | |
660 | ||
661 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
662 | if (!spc->eeh_set_option) { | |
663 | goto param_error_exit; | |
664 | } | |
665 | ||
666 | option = rtas_ld(args, 7); | |
667 | switch (option) { | |
668 | case RTAS_SLOT_TEMP_ERR_LOG: | |
669 | case RTAS_SLOT_PERM_ERR_LOG: | |
670 | break; | |
671 | default: | |
672 | goto param_error_exit; | |
673 | } | |
674 | ||
675 | /* We don't have error log yet */ | |
676 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
677 | return; | |
678 | ||
679 | param_error_exit: | |
680 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
681 | } | |
682 | ||
7fb0bd34 DG |
683 | static int pci_spapr_swizzle(int slot, int pin) |
684 | { | |
685 | return (slot + pin) % PCI_NUM_PINS; | |
686 | } | |
687 | ||
3384f95c DG |
688 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
689 | { | |
690 | /* | |
691 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
692 | * which is less than number of IRQs on the specific bus (4). We |
693 | * use standard PCI swizzling, that is (slot number + pin number) | |
694 | * % 4. | |
3384f95c | 695 | */ |
7fb0bd34 | 696 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
697 | } |
698 | ||
699 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
700 | { | |
701 | /* | |
702 | * Here we use the number returned by pci_spapr_map_irq to find a | |
703 | * corresponding qemu_irq. | |
704 | */ | |
705 | sPAPRPHBState *phb = opaque; | |
706 | ||
caae58cb | 707 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 708 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
709 | } |
710 | ||
5cc7a967 AK |
711 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
712 | { | |
713 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); | |
714 | PCIINTxRoute route; | |
715 | ||
716 | route.mode = PCI_INTX_ENABLED; | |
717 | route.irq = sphb->lsi_table[pin].irq; | |
718 | ||
719 | return route; | |
720 | } | |
721 | ||
0ee2c058 AK |
722 | /* |
723 | * MSI/MSIX memory region implementation. | |
724 | * The handler handles both MSI and MSIX. | |
725 | * For MSI-X, the vector number is encoded as a part of the address, | |
726 | * data is set to 0. | |
727 | * For MSI, the vector number is encoded in least bits in data. | |
728 | */ | |
a8170e5e | 729 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
730 | uint64_t data, unsigned size) |
731 | { | |
28e02042 | 732 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
f1c2dc7c | 733 | uint32_t irq = data; |
0ee2c058 AK |
734 | |
735 | trace_spapr_pci_msi_write(addr, data, irq); | |
736 | ||
737 | qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); | |
738 | } | |
739 | ||
740 | static const MemoryRegionOps spapr_msi_ops = { | |
741 | /* There is no .read as the read result is undefined by PCI spec */ | |
742 | .read = NULL, | |
743 | .write = spapr_msi_write, | |
744 | .endianness = DEVICE_LITTLE_ENDIAN | |
745 | }; | |
746 | ||
298a9710 DG |
747 | /* |
748 | * PHB PCI device | |
749 | */ | |
e00387d5 | 750 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
751 | { |
752 | sPAPRPHBState *phb = opaque; | |
753 | ||
e00387d5 | 754 | return &phb->iommu_as; |
edded454 DG |
755 | } |
756 | ||
16b0ea1d ND |
757 | static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) |
758 | { | |
759 | char *path = NULL, *buf = NULL, *host = NULL; | |
760 | ||
761 | /* Get the PCI VFIO host id */ | |
762 | host = object_property_get_str(OBJECT(pdev), "host", NULL); | |
763 | if (!host) { | |
764 | goto err_out; | |
765 | } | |
766 | ||
767 | /* Construct the path of the file that will give us the DT location */ | |
768 | path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); | |
769 | g_free(host); | |
770 | if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { | |
771 | goto err_out; | |
772 | } | |
773 | g_free(path); | |
774 | ||
775 | /* Construct and read from host device tree the loc-code */ | |
776 | path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); | |
777 | g_free(buf); | |
778 | if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { | |
779 | goto err_out; | |
780 | } | |
781 | return buf; | |
782 | ||
783 | err_out: | |
784 | g_free(path); | |
785 | return NULL; | |
786 | } | |
787 | ||
788 | static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) | |
789 | { | |
790 | char *buf; | |
791 | const char *devtype = "qemu"; | |
792 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
793 | ||
794 | if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
795 | buf = spapr_phb_vfio_get_loc_code(sphb, pdev); | |
796 | if (buf) { | |
797 | return buf; | |
798 | } | |
799 | devtype = "vfio"; | |
800 | } | |
801 | /* | |
802 | * For emulated devices and VFIO-failure case, make up | |
803 | * the loc-code. | |
804 | */ | |
805 | buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", | |
806 | devtype, pdev->name, sphb->index, busnr, | |
807 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
808 | return buf; | |
809 | } | |
810 | ||
7454c7af MR |
811 | /* Macros to operate with address in OF binding to PCI */ |
812 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
813 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
814 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
815 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
816 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
817 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
818 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
819 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
820 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
821 | ||
822 | /* for 'reg'/'assigned-addresses' OF properties */ | |
823 | #define RESOURCE_CELLS_SIZE 2 | |
824 | #define RESOURCE_CELLS_ADDRESS 3 | |
825 | ||
826 | typedef struct ResourceFields { | |
827 | uint32_t phys_hi; | |
828 | uint32_t phys_mid; | |
829 | uint32_t phys_lo; | |
830 | uint32_t size_hi; | |
831 | uint32_t size_lo; | |
832 | } QEMU_PACKED ResourceFields; | |
833 | ||
834 | typedef struct ResourceProps { | |
835 | ResourceFields reg[8]; | |
836 | ResourceFields assigned[7]; | |
837 | uint32_t reg_len; | |
838 | uint32_t assigned_len; | |
839 | } ResourceProps; | |
840 | ||
841 | /* fill in the 'reg'/'assigned-resources' OF properties for | |
842 | * a PCI device. 'reg' describes resource requirements for a | |
843 | * device's IO/MEM regions, 'assigned-addresses' describes the | |
844 | * actual resource assignments. | |
845 | * | |
846 | * the properties are arrays of ('phys-addr', 'size') pairs describing | |
847 | * the addressable regions of the PCI device, where 'phys-addr' is a | |
848 | * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to | |
849 | * (phys.hi, phys.mid, phys.lo), and 'size' is a | |
850 | * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). | |
851 | * | |
852 | * phys.hi = 0xYYXXXXZZ, where: | |
853 | * 0xYY = npt000ss | |
854 | * ||| | | |
72187935 ND |
855 | * ||| +-- space code |
856 | * ||| | | |
857 | * ||| + 00 if configuration space | |
858 | * ||| + 01 if IO region, | |
859 | * ||| + 10 if 32-bit MEM region | |
860 | * ||| + 11 if 64-bit MEM region | |
861 | * ||| | |
7454c7af MR |
862 | * ||+------ for non-relocatable IO: 1 if aliased |
863 | * || for relocatable IO: 1 if below 64KB | |
864 | * || for MEM: 1 if below 1MB | |
865 | * |+------- 1 if region is prefetchable | |
866 | * +-------- 1 if region is non-relocatable | |
867 | * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function | |
868 | * bits respectively | |
869 | * 0xZZ = rrrrrrrr, the register number of the BAR corresponding | |
870 | * to the region | |
871 | * | |
872 | * phys.mid and phys.lo correspond respectively to the hi/lo portions | |
873 | * of the actual address of the region. | |
874 | * | |
875 | * how the phys-addr/size values are used differ slightly between | |
876 | * 'reg' and 'assigned-addresses' properties. namely, 'reg' has | |
877 | * an additional description for the config space region of the | |
878 | * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 | |
879 | * to describe the region as relocatable, with an address-mapping | |
880 | * that corresponds directly to the PHB's address space for the | |
881 | * resource. 'assigned-addresses' always has n=1 set with an absolute | |
882 | * address assigned for the resource. in general, 'assigned-addresses' | |
883 | * won't be populated, since addresses for PCI devices are generally | |
884 | * unmapped initially and left to the guest to assign. | |
885 | * | |
886 | * note also that addresses defined in these properties are, at least | |
887 | * for PAPR guests, relative to the PHBs IO/MEM windows, and | |
888 | * correspond directly to the addresses in the BARs. | |
889 | * | |
890 | * in accordance with PCI Bus Binding to Open Firmware, | |
891 | * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, | |
892 | * Appendix C. | |
893 | */ | |
894 | static void populate_resource_props(PCIDevice *d, ResourceProps *rp) | |
895 | { | |
896 | int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); | |
897 | uint32_t dev_id = (b_bbbbbbbb(bus_num) | | |
898 | b_ddddd(PCI_SLOT(d->devfn)) | | |
899 | b_fff(PCI_FUNC(d->devfn))); | |
900 | ResourceFields *reg, *assigned; | |
901 | int i, reg_idx = 0, assigned_idx = 0; | |
902 | ||
903 | /* config space region */ | |
904 | reg = &rp->reg[reg_idx++]; | |
905 | reg->phys_hi = cpu_to_be32(dev_id); | |
906 | reg->phys_mid = 0; | |
907 | reg->phys_lo = 0; | |
908 | reg->size_hi = 0; | |
909 | reg->size_lo = 0; | |
910 | ||
911 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
912 | if (!d->io_regions[i].size) { | |
913 | continue; | |
914 | } | |
915 | ||
916 | reg = &rp->reg[reg_idx++]; | |
917 | ||
918 | reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); | |
919 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
920 | reg->phys_hi |= cpu_to_be32(b_ss(1)); | |
72187935 ND |
921 | } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
922 | reg->phys_hi |= cpu_to_be32(b_ss(3)); | |
7454c7af MR |
923 | } else { |
924 | reg->phys_hi |= cpu_to_be32(b_ss(2)); | |
925 | } | |
926 | reg->phys_mid = 0; | |
927 | reg->phys_lo = 0; | |
928 | reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); | |
929 | reg->size_lo = cpu_to_be32(d->io_regions[i].size); | |
930 | ||
931 | if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { | |
932 | continue; | |
933 | } | |
934 | ||
935 | assigned = &rp->assigned[assigned_idx++]; | |
936 | assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); | |
937 | assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); | |
938 | assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); | |
939 | assigned->size_hi = reg->size_hi; | |
940 | assigned->size_lo = reg->size_lo; | |
941 | } | |
942 | ||
943 | rp->reg_len = reg_idx * sizeof(ResourceFields); | |
944 | rp->assigned_len = assigned_idx * sizeof(ResourceFields); | |
945 | } | |
946 | ||
e634b89c ND |
947 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
948 | PCIDevice *pdev); | |
949 | ||
7454c7af | 950 | static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, |
16b0ea1d | 951 | sPAPRPHBState *sphb) |
7454c7af MR |
952 | { |
953 | ResourceProps rp; | |
954 | bool is_bridge = false; | |
16b0ea1d ND |
955 | int pci_status, err; |
956 | char *buf = NULL; | |
e634b89c | 957 | uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); |
7454c7af MR |
958 | |
959 | if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == | |
960 | PCI_HEADER_TYPE_BRIDGE) { | |
961 | is_bridge = true; | |
962 | } | |
963 | ||
964 | /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ | |
965 | _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", | |
966 | pci_default_read_config(dev, PCI_VENDOR_ID, 2))); | |
967 | _FDT(fdt_setprop_cell(fdt, offset, "device-id", | |
968 | pci_default_read_config(dev, PCI_DEVICE_ID, 2))); | |
969 | _FDT(fdt_setprop_cell(fdt, offset, "revision-id", | |
970 | pci_default_read_config(dev, PCI_REVISION_ID, 1))); | |
971 | _FDT(fdt_setprop_cell(fdt, offset, "class-code", | |
4a7c3474 | 972 | pci_default_read_config(dev, PCI_CLASS_PROG, 3))); |
7454c7af MR |
973 | if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { |
974 | _FDT(fdt_setprop_cell(fdt, offset, "interrupts", | |
975 | pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); | |
976 | } | |
977 | ||
978 | if (!is_bridge) { | |
979 | _FDT(fdt_setprop_cell(fdt, offset, "min-grant", | |
980 | pci_default_read_config(dev, PCI_MIN_GNT, 1))); | |
981 | _FDT(fdt_setprop_cell(fdt, offset, "max-latency", | |
982 | pci_default_read_config(dev, PCI_MAX_LAT, 1))); | |
983 | } | |
984 | ||
985 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { | |
986 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", | |
987 | pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); | |
988 | } | |
989 | ||
990 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { | |
991 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", | |
992 | pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); | |
993 | } | |
994 | ||
995 | _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", | |
996 | pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); | |
997 | ||
998 | /* the following fdt cells are masked off the pci status register */ | |
999 | pci_status = pci_default_read_config(dev, PCI_STATUS, 2); | |
1000 | _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", | |
1001 | PCI_STATUS_DEVSEL_MASK & pci_status)); | |
1002 | ||
1003 | if (pci_status & PCI_STATUS_FAST_BACK) { | |
1004 | _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); | |
1005 | } | |
1006 | if (pci_status & PCI_STATUS_66MHZ) { | |
1007 | _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); | |
1008 | } | |
1009 | if (pci_status & PCI_STATUS_UDF) { | |
1010 | _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); | |
1011 | } | |
1012 | ||
1013 | /* NOTE: this is normally generated by firmware via path/unit name, | |
1014 | * but in our case we must set it manually since it does not get | |
1015 | * processed by OF beforehand | |
1016 | */ | |
1017 | _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); | |
16b0ea1d ND |
1018 | buf = spapr_phb_get_loc_code(sphb, dev); |
1019 | if (!buf) { | |
1020 | error_report("Failed setting the ibm,loc-code"); | |
1021 | return -1; | |
1022 | } | |
1023 | ||
1024 | err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); | |
1025 | g_free(buf); | |
1026 | if (err < 0) { | |
1027 | return err; | |
1028 | } | |
1029 | ||
e634b89c ND |
1030 | if (drc_index) { |
1031 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); | |
1032 | } | |
7454c7af MR |
1033 | |
1034 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", | |
1035 | RESOURCE_CELLS_ADDRESS)); | |
1036 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", | |
1037 | RESOURCE_CELLS_SIZE)); | |
1038 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", | |
1039 | RESOURCE_CELLS_SIZE)); | |
1040 | ||
1041 | populate_resource_props(dev, &rp); | |
1042 | _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); | |
1043 | _FDT(fdt_setprop(fdt, offset, "assigned-addresses", | |
1044 | (uint8_t *)rp.assigned, rp.assigned_len)); | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | /* create OF node for pci device and required OF DT properties */ | |
1d2d9742 | 1050 | static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, |
1d2d9742 | 1051 | void *fdt, int node_offset) |
7454c7af | 1052 | { |
1d2d9742 | 1053 | int offset, ret; |
7454c7af MR |
1054 | int slot = PCI_SLOT(dev->devfn); |
1055 | int func = PCI_FUNC(dev->devfn); | |
9b7d9284 | 1056 | char nodename[FDT_NAME_MAX]; |
7454c7af | 1057 | |
7454c7af | 1058 | if (func != 0) { |
9b7d9284 | 1059 | snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); |
7454c7af | 1060 | } else { |
9b7d9284 | 1061 | snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); |
7454c7af | 1062 | } |
1d2d9742 | 1063 | offset = fdt_add_subnode(fdt, node_offset, nodename); |
e634b89c ND |
1064 | ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); |
1065 | ||
7454c7af | 1066 | g_assert(!ret); |
1d2d9742 ND |
1067 | if (ret) { |
1068 | return 0; | |
1069 | } | |
1070 | return offset; | |
7454c7af MR |
1071 | } |
1072 | ||
1073 | static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, | |
1074 | sPAPRPHBState *phb, | |
1075 | PCIDevice *pdev, | |
1076 | Error **errp) | |
1077 | { | |
1078 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1079 | DeviceState *dev = DEVICE(pdev); | |
7454c7af | 1080 | void *fdt = NULL; |
1d2d9742 | 1081 | int fdt_start_offset = 0, fdt_size; |
7454c7af | 1082 | |
7454c7af | 1083 | if (dev->hotplugged) { |
1d2d9742 | 1084 | fdt = create_device_tree(&fdt_size); |
e634b89c | 1085 | fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); |
1d2d9742 ND |
1086 | if (!fdt_start_offset) { |
1087 | error_setg(errp, "Failed to create pci child device tree node"); | |
1088 | goto out; | |
1089 | } | |
7454c7af MR |
1090 | } |
1091 | ||
1092 | drck->attach(drc, DEVICE(pdev), | |
1093 | fdt, fdt_start_offset, !dev->hotplugged, errp); | |
1d2d9742 | 1094 | out: |
7454c7af MR |
1095 | if (*errp) { |
1096 | g_free(fdt); | |
1097 | } | |
1098 | } | |
1099 | ||
1100 | static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) | |
1101 | { | |
1102 | /* some version guests do not wait for completion of a device | |
1103 | * cleanup (generally done asynchronously by the kernel) before | |
1104 | * signaling to QEMU that the device is safe, but instead sleep | |
1105 | * for some 'safe' period of time. unfortunately on a busy host | |
1106 | * this sleep isn't guaranteed to be long enough, resulting in | |
1107 | * bad things like IRQ lines being left asserted during final | |
1108 | * device removal. to deal with this we call reset just prior | |
1109 | * to finalizing the device, which will put the device back into | |
1110 | * an 'idle' state, as the device cleanup code expects. | |
1111 | */ | |
1112 | pci_device_reset(PCI_DEVICE(dev)); | |
1113 | object_unparent(OBJECT(dev)); | |
1114 | } | |
1115 | ||
1116 | static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, | |
1117 | sPAPRPHBState *phb, | |
1118 | PCIDevice *pdev, | |
1119 | Error **errp) | |
1120 | { | |
1121 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1122 | ||
1123 | drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); | |
1124 | } | |
1125 | ||
1126 | static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, | |
1127 | PCIDevice *pdev) | |
1128 | { | |
1129 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
1130 | return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, | |
1131 | (phb->index << 16) | | |
1132 | (busnr << 8) | | |
1133 | pdev->devfn); | |
1134 | } | |
1135 | ||
1d2d9742 ND |
1136 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
1137 | PCIDevice *pdev) | |
1138 | { | |
1139 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1140 | sPAPRDRConnectorClass *drck; | |
1141 | ||
1142 | if (!drc) { | |
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1147 | return drck->get_index(drc); | |
1148 | } | |
1149 | ||
7454c7af MR |
1150 | static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, |
1151 | DeviceState *plugged_dev, Error **errp) | |
1152 | { | |
1153 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1154 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1155 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1156 | Error *local_err = NULL; | |
1157 | ||
1158 | /* if DR is disabled we don't need to do anything in the case of | |
1159 | * hotplug or coldplug callbacks | |
1160 | */ | |
1161 | if (!phb->dr_enabled) { | |
1162 | /* if this is a hotplug operation initiated by the user | |
1163 | * we need to let them know it's not enabled | |
1164 | */ | |
1165 | if (plugged_dev->hotplugged) { | |
c6bd8c70 MA |
1166 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1167 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1168 | } |
1169 | return; | |
1170 | } | |
1171 | ||
1172 | g_assert(drc); | |
1173 | ||
1174 | spapr_phb_add_pci_device(drc, phb, pdev, &local_err); | |
1175 | if (local_err) { | |
1176 | error_propagate(errp, local_err); | |
1177 | return; | |
1178 | } | |
c5bc152b TD |
1179 | if (plugged_dev->hotplugged) { |
1180 | spapr_hotplug_req_add_event(drc); | |
1181 | } | |
7454c7af MR |
1182 | } |
1183 | ||
1184 | static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, | |
1185 | DeviceState *plugged_dev, Error **errp) | |
1186 | { | |
1187 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1188 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1189 | sPAPRDRConnectorClass *drck; | |
1190 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1191 | Error *local_err = NULL; | |
1192 | ||
1193 | if (!phb->dr_enabled) { | |
c6bd8c70 MA |
1194 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1195 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1196 | return; |
1197 | } | |
1198 | ||
1199 | g_assert(drc); | |
1200 | ||
1201 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1202 | if (!drck->release_pending(drc)) { | |
1203 | spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); | |
1204 | if (local_err) { | |
1205 | error_propagate(errp, local_err); | |
1206 | return; | |
1207 | } | |
c5bc152b | 1208 | spapr_hotplug_req_remove_event(drc); |
7454c7af MR |
1209 | } |
1210 | } | |
1211 | ||
c6ba42f6 | 1212 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 1213 | { |
28e02042 | 1214 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
c6ba42f6 | 1215 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
8c9f64df | 1216 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 1217 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
da6ccee4 | 1218 | sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); |
298a9710 DG |
1219 | char *namebuf; |
1220 | int i; | |
3384f95c | 1221 | PCIBus *bus; |
8c46f7ec | 1222 | uint64_t msi_window_size = 4096; |
3384f95c | 1223 | |
421b1b27 | 1224 | if (sphb->index != (uint32_t)-1) { |
caae58cb DG |
1225 | hwaddr windows_base; |
1226 | ||
421b1b27 DG |
1227 | if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) |
1228 | || (sphb->mem_win_addr != (hwaddr)-1) | |
1229 | || (sphb->io_win_addr != (hwaddr)-1)) { | |
c6ba42f6 AK |
1230 | error_setg(errp, "Either \"index\" or other parameters must" |
1231 | " be specified for PAPR PHB, not both"); | |
1232 | return; | |
caae58cb DG |
1233 | } |
1234 | ||
3e4ac968 DG |
1235 | if (sphb->index > SPAPR_PCI_MAX_INDEX) { |
1236 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
1237 | SPAPR_PCI_MAX_INDEX); | |
1238 | return; | |
1239 | } | |
1240 | ||
caae58cb | 1241 | sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; |
c8545818 | 1242 | sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); |
caae58cb DG |
1243 | |
1244 | windows_base = SPAPR_PCI_WINDOW_BASE | |
1245 | + sphb->index * SPAPR_PCI_WINDOW_SPACING; | |
1246 | sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; | |
1247 | sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; | |
caae58cb DG |
1248 | } |
1249 | ||
421b1b27 | 1250 | if (sphb->buid == (uint64_t)-1) { |
c6ba42f6 AK |
1251 | error_setg(errp, "BUID not specified for PHB"); |
1252 | return; | |
caae58cb DG |
1253 | } |
1254 | ||
421b1b27 | 1255 | if (sphb->dma_liobn == (uint32_t)-1) { |
c6ba42f6 AK |
1256 | error_setg(errp, "LIOBN not specified for PHB"); |
1257 | return; | |
caae58cb DG |
1258 | } |
1259 | ||
421b1b27 | 1260 | if (sphb->mem_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1261 | error_setg(errp, "Memory window address not specified for PHB"); |
1262 | return; | |
caae58cb DG |
1263 | } |
1264 | ||
421b1b27 | 1265 | if (sphb->io_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1266 | error_setg(errp, "IO window address not specified for PHB"); |
1267 | return; | |
caae58cb DG |
1268 | } |
1269 | ||
46c5874e | 1270 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
c6ba42f6 AK |
1271 | error_setg(errp, "PCI host bridges must have unique BUIDs"); |
1272 | return; | |
caae58cb DG |
1273 | } |
1274 | ||
8c9f64df | 1275 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 1276 | |
8c9f64df | 1277 | namebuf = alloca(strlen(sphb->dtbusname) + 32); |
3384f95c | 1278 | |
298a9710 | 1279 | /* Initialize memory regions */ |
8c9f64df | 1280 | sprintf(namebuf, "%s.mmio", sphb->dtbusname); |
92b8e39c | 1281 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
3384f95c | 1282 | |
8c9f64df | 1283 | sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); |
40c5dce9 PB |
1284 | memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), |
1285 | namebuf, &sphb->memspace, | |
8c9f64df AF |
1286 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
1287 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, | |
1288 | &sphb->memwindow); | |
3384f95c | 1289 | |
fabe9ee1 | 1290 | /* Initialize IO regions */ |
8c9f64df | 1291 | sprintf(namebuf, "%s.io", sphb->dtbusname); |
40c5dce9 PB |
1292 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
1293 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
3384f95c | 1294 | |
a3cfa18e | 1295 | sprintf(namebuf, "%s.io-alias", sphb->dtbusname); |
66aab867 | 1296 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 1297 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
8c9f64df | 1298 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 1299 | &sphb->iowindow); |
1b8601b0 AK |
1300 | |
1301 | bus = pci_register_bus(dev, NULL, | |
8c9f64df AF |
1302 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, |
1303 | &sphb->memspace, &sphb->iospace, | |
60a0e443 | 1304 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); |
8c9f64df | 1305 | phb->bus = bus; |
7454c7af | 1306 | qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); |
298a9710 | 1307 | |
cca7fad5 AK |
1308 | /* |
1309 | * Initialize PHB address space. | |
1310 | * By default there will be at least one subregion for default | |
1311 | * 32bit DMA window. | |
1312 | * Later the guest might want to create another DMA window | |
1313 | * which will become another memory subregion. | |
1314 | */ | |
1315 | sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); | |
1316 | ||
1317 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), | |
1318 | namebuf, UINT64_MAX); | |
1319 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, | |
1320 | sphb->dtbusname); | |
1321 | ||
8c46f7ec GK |
1322 | /* |
1323 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
1324 | * we need to allocate some memory to catch those writes coming | |
1325 | * from msi_notify()/msix_notify(). | |
1326 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
1327 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
1328 | * be used. | |
1329 | * | |
1330 | * For KVM we want to ensure that this memory is a full page so that | |
1331 | * our memory slot is of page size granularity. | |
1332 | */ | |
1333 | #ifdef CONFIG_KVM | |
1334 | if (kvm_enabled()) { | |
1335 | msi_window_size = getpagesize(); | |
1336 | } | |
1337 | #endif | |
1338 | ||
1339 | memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, | |
1340 | "msi", msi_window_size); | |
1341 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
1342 | &sphb->msiwindow); | |
1343 | ||
e00387d5 | 1344 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 1345 | |
5cc7a967 AK |
1346 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
1347 | ||
8c9f64df | 1348 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
1349 | |
1350 | /* Initialize the LSI table */ | |
7fb0bd34 | 1351 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 1352 | uint32_t irq; |
298a9710 | 1353 | |
bee763db | 1354 | irq = xics_alloc_block(spapr->icp, 0, 1, true, false); |
a307d594 | 1355 | if (!irq) { |
c6ba42f6 AK |
1356 | error_setg(errp, "spapr_allocate_lsi failed"); |
1357 | return; | |
298a9710 DG |
1358 | } |
1359 | ||
8c9f64df | 1360 | sphb->lsi_table[i].irq = irq; |
298a9710 | 1361 | } |
da6ccee4 | 1362 | |
62083979 MR |
1363 | /* allocate connectors for child PCI devices */ |
1364 | if (sphb->dr_enabled) { | |
1365 | for (i = 0; i < PCI_SLOT_MAX * 8; i++) { | |
1366 | spapr_dr_connector_new(OBJECT(phb), | |
1367 | SPAPR_DR_CONNECTOR_TYPE_PCI, | |
1368 | (sphb->index << 16) | i); | |
1369 | } | |
1370 | } | |
1371 | ||
da6ccee4 AK |
1372 | if (!info->finish_realize) { |
1373 | error_setg(errp, "finish_realize not defined"); | |
1374 | return; | |
1375 | } | |
1376 | ||
1377 | info->finish_realize(sphb, errp); | |
9a321e92 AK |
1378 | |
1379 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); | |
da6ccee4 AK |
1380 | } |
1381 | ||
1382 | static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) | |
1383 | { | |
e28c16f6 | 1384 | sPAPRTCETable *tcet; |
3e1a01cb | 1385 | uint32_t nb_table; |
e28c16f6 | 1386 | |
3e1a01cb | 1387 | nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; |
e28c16f6 | 1388 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, |
3e1a01cb | 1389 | 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); |
e28c16f6 | 1390 | if (!tcet) { |
da6ccee4 AK |
1391 | error_setg(errp, "Unable to create TCE table for %s", |
1392 | sphb->dtbusname); | |
1393 | return ; | |
1394 | } | |
cca7fad5 AK |
1395 | |
1396 | /* Register default 32bit DMA window */ | |
1397 | memory_region_add_subregion(&sphb->iommu_root, 0, | |
e28c16f6 | 1398 | spapr_tce_get_iommu(tcet)); |
298a9710 DG |
1399 | } |
1400 | ||
e28c16f6 | 1401 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 1402 | { |
e28c16f6 AK |
1403 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
1404 | ||
1405 | if (dev) { | |
1406 | device_reset(dev); | |
1407 | } | |
eddeed26 | 1408 | |
e28c16f6 AK |
1409 | return 0; |
1410 | } | |
1411 | ||
1412 | static void spapr_phb_reset(DeviceState *qdev) | |
1413 | { | |
eddeed26 | 1414 | /* Reset the IOMMU state */ |
e28c16f6 | 1415 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
eddeed26 DG |
1416 | } |
1417 | ||
298a9710 | 1418 | static Property spapr_phb_properties[] = { |
3e4ac968 | 1419 | DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), |
c7bcc85d PB |
1420 | DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), |
1421 | DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), | |
1422 | DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), | |
1423 | DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, | |
1424 | SPAPR_PCI_MMIO_WIN_SIZE), | |
1425 | DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), | |
1426 | DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, | |
1427 | SPAPR_PCI_IO_WIN_SIZE), | |
7619c7b0 MR |
1428 | DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, |
1429 | true), | |
298a9710 DG |
1430 | DEFINE_PROP_END_OF_LIST(), |
1431 | }; | |
1432 | ||
1112cf94 DG |
1433 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
1434 | .name = "spapr_pci/lsi", | |
1435 | .version_id = 1, | |
1436 | .minimum_version_id = 1, | |
3aff6c2f | 1437 | .fields = (VMStateField[]) { |
1112cf94 DG |
1438 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), |
1439 | ||
1440 | VMSTATE_END_OF_LIST() | |
1441 | }, | |
1442 | }; | |
1443 | ||
1444 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 1445 | .name = "spapr_pci/msi", |
1112cf94 DG |
1446 | .version_id = 1, |
1447 | .minimum_version_id = 1, | |
9a321e92 AK |
1448 | .fields = (VMStateField []) { |
1449 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
1450 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
1451 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
1452 | VMSTATE_END_OF_LIST() |
1453 | }, | |
1454 | }; | |
1455 | ||
9a321e92 AK |
1456 | static void spapr_pci_pre_save(void *opaque) |
1457 | { | |
1458 | sPAPRPHBState *sphb = opaque; | |
708414f0 MA |
1459 | GHashTableIter iter; |
1460 | gpointer key, value; | |
1461 | int i; | |
9a321e92 | 1462 | |
012aef07 MA |
1463 | g_free(sphb->msi_devs); |
1464 | sphb->msi_devs = NULL; | |
708414f0 MA |
1465 | sphb->msi_devs_num = g_hash_table_size(sphb->msi); |
1466 | if (!sphb->msi_devs_num) { | |
9a321e92 AK |
1467 | return; |
1468 | } | |
708414f0 | 1469 | sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); |
9a321e92 | 1470 | |
708414f0 MA |
1471 | g_hash_table_iter_init(&iter, sphb->msi); |
1472 | for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { | |
1473 | sphb->msi_devs[i].key = *(uint32_t *) key; | |
1474 | sphb->msi_devs[i].value = *(spapr_pci_msi *) value; | |
1475 | } | |
9a321e92 AK |
1476 | } |
1477 | ||
1478 | static int spapr_pci_post_load(void *opaque, int version_id) | |
1479 | { | |
1480 | sPAPRPHBState *sphb = opaque; | |
1481 | gpointer key, value; | |
1482 | int i; | |
1483 | ||
1484 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
1485 | key = g_memdup(&sphb->msi_devs[i].key, | |
1486 | sizeof(sphb->msi_devs[i].key)); | |
1487 | value = g_memdup(&sphb->msi_devs[i].value, | |
1488 | sizeof(sphb->msi_devs[i].value)); | |
1489 | g_hash_table_insert(sphb->msi, key, value); | |
1490 | } | |
012aef07 MA |
1491 | g_free(sphb->msi_devs); |
1492 | sphb->msi_devs = NULL; | |
9a321e92 AK |
1493 | sphb->msi_devs_num = 0; |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1112cf94 DG |
1498 | static const VMStateDescription vmstate_spapr_pci = { |
1499 | .name = "spapr_pci", | |
9a321e92 AK |
1500 | .version_id = 2, |
1501 | .minimum_version_id = 2, | |
1502 | .pre_save = spapr_pci_pre_save, | |
1503 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 1504 | .fields = (VMStateField[]) { |
1112cf94 DG |
1505 | VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), |
1506 | VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), | |
1507 | VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), | |
1508 | VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), | |
1509 | VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), | |
1510 | VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), | |
1112cf94 DG |
1511 | VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, |
1512 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), | |
9a321e92 AK |
1513 | VMSTATE_INT32(msi_devs_num, sPAPRPHBState), |
1514 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, | |
1515 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), | |
1112cf94 DG |
1516 | VMSTATE_END_OF_LIST() |
1517 | }, | |
1518 | }; | |
1519 | ||
568f0690 DG |
1520 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
1521 | PCIBus *rootbus) | |
1522 | { | |
1523 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
1524 | ||
1525 | return sphb->dtbusname; | |
1526 | } | |
1527 | ||
298a9710 DG |
1528 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
1529 | { | |
568f0690 | 1530 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 1531 | DeviceClass *dc = DEVICE_CLASS(klass); |
da6ccee4 | 1532 | sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); |
7454c7af | 1533 | HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); |
298a9710 | 1534 | |
568f0690 | 1535 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 1536 | dc->realize = spapr_phb_realize; |
298a9710 | 1537 | dc->props = spapr_phb_properties; |
eddeed26 | 1538 | dc->reset = spapr_phb_reset; |
1112cf94 | 1539 | dc->vmsd = &vmstate_spapr_pci; |
09aa9a52 AK |
1540 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
1541 | dc->cannot_instantiate_with_device_add_yet = false; | |
da6ccee4 | 1542 | spc->finish_realize = spapr_phb_finish_realize; |
7454c7af MR |
1543 | hp->plug = spapr_phb_hot_plug_child; |
1544 | hp->unplug = spapr_phb_hot_unplug_child; | |
298a9710 | 1545 | } |
3384f95c | 1546 | |
4240abff | 1547 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 1548 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 1549 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
1550 | .instance_size = sizeof(sPAPRPHBState), |
1551 | .class_init = spapr_phb_class_init, | |
da6ccee4 | 1552 | .class_size = sizeof(sPAPRPHBClass), |
7454c7af MR |
1553 | .interfaces = (InterfaceInfo[]) { |
1554 | { TYPE_HOTPLUG_HANDLER }, | |
1555 | { } | |
1556 | } | |
298a9710 DG |
1557 | }; |
1558 | ||
28e02042 | 1559 | PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) |
298a9710 DG |
1560 | { |
1561 | DeviceState *dev; | |
1562 | ||
8c9f64df | 1563 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 1564 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 1565 | qdev_init_nofail(dev); |
caae58cb DG |
1566 | |
1567 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
1568 | } |
1569 | ||
1d2d9742 ND |
1570 | typedef struct sPAPRFDT { |
1571 | void *fdt; | |
1572 | int node_off; | |
1573 | sPAPRPHBState *sphb; | |
1574 | } sPAPRFDT; | |
1575 | ||
1576 | static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, | |
1577 | void *opaque) | |
1578 | { | |
1579 | PCIBus *sec_bus; | |
1580 | sPAPRFDT *p = opaque; | |
1581 | int offset; | |
1582 | sPAPRFDT s_fdt; | |
1d2d9742 | 1583 | |
e634b89c | 1584 | offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); |
1d2d9742 ND |
1585 | if (!offset) { |
1586 | error_report("Failed to create pci child device tree node"); | |
1587 | return; | |
1588 | } | |
1589 | ||
1590 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
1591 | PCI_HEADER_TYPE_BRIDGE)) { | |
1592 | return; | |
1593 | } | |
1594 | ||
1595 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
1596 | if (!sec_bus) { | |
1597 | return; | |
1598 | } | |
1599 | ||
1600 | s_fdt.fdt = p->fdt; | |
1601 | s_fdt.node_off = offset; | |
1602 | s_fdt.sphb = p->sphb; | |
1603 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
1604 | spapr_populate_pci_devices_dt, | |
1605 | &s_fdt); | |
1606 | } | |
1607 | ||
1608 | static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, | |
1609 | void *opaque) | |
1610 | { | |
1611 | unsigned int *bus_no = opaque; | |
1612 | unsigned int primary = *bus_no; | |
1613 | unsigned int subordinate = 0xff; | |
1614 | PCIBus *sec_bus = NULL; | |
1615 | ||
1616 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
1617 | PCI_HEADER_TYPE_BRIDGE)) { | |
1618 | return; | |
1619 | } | |
1620 | ||
1621 | (*bus_no)++; | |
1622 | pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); | |
1623 | pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); | |
1624 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
1625 | ||
1626 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
1627 | if (!sec_bus) { | |
1628 | return; | |
1629 | } | |
1630 | ||
1631 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); | |
1632 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
1633 | spapr_phb_pci_enumerate_bridge, bus_no); | |
1634 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
1635 | } | |
1636 | ||
1637 | static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) | |
1638 | { | |
1639 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; | |
1640 | unsigned int bus_no = 0; | |
1641 | ||
1642 | pci_for_each_device(bus, pci_bus_num(bus), | |
1643 | spapr_phb_pci_enumerate_bridge, | |
1644 | &bus_no); | |
1645 | ||
1646 | } | |
1647 | ||
e0fdbd7c AK |
1648 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
1649 | uint32_t xics_phandle, | |
1650 | void *fdt) | |
3384f95c | 1651 | { |
62083979 | 1652 | int bus_off, i, j, ret; |
9b7d9284 | 1653 | char nodename[FDT_NAME_MAX]; |
3384f95c | 1654 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
b194df47 AK |
1655 | const uint64_t mmiosize = memory_region_size(&phb->memwindow); |
1656 | const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; | |
1657 | const uint64_t w32size = MIN(w32max, mmiosize); | |
1658 | const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; | |
3384f95c DG |
1659 | struct { |
1660 | uint32_t hi; | |
1661 | uint64_t child; | |
1662 | uint64_t parent; | |
1663 | uint64_t size; | |
c4889f54 | 1664 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
1665 | { |
1666 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
1667 | cpu_to_be64(phb->io_win_addr), | |
1668 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
1669 | }, | |
1670 | { | |
1671 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
1672 | cpu_to_be64(phb->mem_win_addr), | |
b194df47 AK |
1673 | cpu_to_be64(w32size), |
1674 | }, | |
1675 | { | |
1676 | cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), | |
1677 | cpu_to_be64(phb->mem_win_addr + w32size), | |
1678 | cpu_to_be64(w64size) | |
3384f95c DG |
1679 | }, |
1680 | }; | |
b194df47 | 1681 | const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); |
3384f95c DG |
1682 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
1683 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
1684 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
1685 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
ccf9ff85 | 1686 | sPAPRTCETable *tcet; |
1d2d9742 ND |
1687 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; |
1688 | sPAPRFDT s_fdt; | |
3384f95c DG |
1689 | |
1690 | /* Start populating the FDT */ | |
9b7d9284 | 1691 | snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); |
3384f95c DG |
1692 | bus_off = fdt_add_subnode(fdt, 0, nodename); |
1693 | if (bus_off < 0) { | |
1694 | return bus_off; | |
1695 | } | |
1696 | ||
3384f95c DG |
1697 | /* Write PHB properties */ |
1698 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
1699 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
1700 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
1701 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
1702 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
1703 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
1704 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 1705 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 1706 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 1707 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
9dbae977 | 1708 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); |
3384f95c | 1709 | |
4d8d5467 BH |
1710 | /* Build the interrupt-map, this must matches what is done |
1711 | * in pci_spapr_map_irq | |
1712 | */ | |
1713 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
1714 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
1715 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
1716 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
1717 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
1718 | int lsi_num = pci_spapr_swizzle(i, j); | |
1719 | ||
1720 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
1721 | irqmap[1] = 0; | |
1722 | irqmap[2] = 0; | |
1723 | irqmap[3] = cpu_to_be32(j+1); | |
1724 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 1725 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
1726 | irqmap[6] = cpu_to_be32(0x8); |
1727 | } | |
3384f95c | 1728 | } |
3384f95c DG |
1729 | /* Write interrupt map */ |
1730 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 1731 | sizeof(interrupt_map))); |
3384f95c | 1732 | |
ccf9ff85 AK |
1733 | tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); |
1734 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", | |
1735 | tcet->liobn, tcet->bus_offset, | |
1736 | tcet->nb_table << tcet->page_shift); | |
edded454 | 1737 | |
1d2d9742 ND |
1738 | /* Walk the bridges and program the bus numbers*/ |
1739 | spapr_phb_pci_enumerate(phb); | |
1740 | _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); | |
1741 | ||
1742 | /* Populate tree nodes with PCI devices attached */ | |
1743 | s_fdt.fdt = fdt; | |
1744 | s_fdt.node_off = bus_off; | |
1745 | s_fdt.sphb = phb; | |
1746 | pci_for_each_device(bus, pci_bus_num(bus), | |
1747 | spapr_populate_pci_devices_dt, | |
1748 | &s_fdt); | |
1749 | ||
62083979 MR |
1750 | ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), |
1751 | SPAPR_DR_CONNECTOR_TYPE_PCI); | |
1752 | if (ret) { | |
1753 | return ret; | |
1754 | } | |
1755 | ||
3384f95c DG |
1756 | return 0; |
1757 | } | |
298a9710 | 1758 | |
fa28f71b AK |
1759 | void spapr_pci_rtas_init(void) |
1760 | { | |
3a3b8502 AK |
1761 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
1762 | rtas_read_pci_config); | |
1763 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
1764 | rtas_write_pci_config); | |
1765 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
1766 | rtas_ibm_read_pci_config); | |
1767 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
1768 | rtas_ibm_write_pci_config); | |
0ee2c058 | 1769 | if (msi_supported) { |
3a3b8502 AK |
1770 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
1771 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 1772 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
1773 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
1774 | rtas_ibm_change_msi); | |
0ee2c058 | 1775 | } |
ee954280 GS |
1776 | |
1777 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
1778 | "ibm,set-eeh-option", | |
1779 | rtas_ibm_set_eeh_option); | |
1780 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
1781 | "ibm,get-config-addr-info2", | |
1782 | rtas_ibm_get_config_addr_info2); | |
1783 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
1784 | "ibm,read-slot-reset-state2", | |
1785 | rtas_ibm_read_slot_reset_state2); | |
1786 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
1787 | "ibm,set-slot-reset", | |
1788 | rtas_ibm_set_slot_reset); | |
1789 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
1790 | "ibm,configure-pe", | |
1791 | rtas_ibm_configure_pe); | |
1792 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
1793 | "ibm,slot-error-detail", | |
1794 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
1795 | } |
1796 | ||
8c9f64df | 1797 | static void spapr_pci_register_types(void) |
298a9710 DG |
1798 | { |
1799 | type_register_static(&spapr_phb_info); | |
1800 | } | |
8c9f64df AF |
1801 | |
1802 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
1803 | |
1804 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
1805 | { | |
1806 | bool be = *(bool *)opaque; | |
1807 | ||
1808 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
1809 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
1810 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
1811 | &error_abort); | |
1812 | } | |
1813 | return 0; | |
1814 | } | |
1815 | ||
1816 | void spapr_pci_switch_vga(bool big_endian) | |
1817 | { | |
28e02042 | 1818 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
eefaccc0 DG |
1819 | sPAPRPHBState *sphb; |
1820 | ||
1821 | /* | |
1822 | * For backward compatibility with existing guests, we switch | |
1823 | * the endianness of the VGA controller when changing the guest | |
1824 | * interrupt mode | |
1825 | */ | |
1826 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
1827 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
1828 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
1829 | &big_endian); | |
1830 | } | |
1831 | } |