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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/pci/pci.h" | |
27 | #include "hw/pci/msi.h" | |
28 | #include "hw/pci/msix.h" | |
29 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
30 | #include "hw/ppc/spapr.h" |
31 | #include "hw/pci-host/spapr.h" | |
022c62cb | 32 | #include "exec/address-spaces.h" |
3384f95c | 33 | #include <libfdt.h> |
a2950fb6 | 34 | #include "trace.h" |
295d51aa | 35 | #include "qemu/error-report.h" |
3384f95c | 36 | |
06aac7bd | 37 | #include "hw/pci/pci_bus.h" |
3384f95c | 38 | |
0ee2c058 AK |
39 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
40 | #define RTAS_QUERY_FN 0 | |
41 | #define RTAS_CHANGE_FN 1 | |
42 | #define RTAS_RESET_FN 2 | |
43 | #define RTAS_CHANGE_MSI_FN 3 | |
44 | #define RTAS_CHANGE_MSIX_FN 4 | |
45 | ||
46 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
47 | #define RTAS_TYPE_MSI 1 | |
48 | #define RTAS_TYPE_MSIX 2 | |
49 | ||
9894c5d4 | 50 | static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid) |
3384f95c | 51 | { |
8c9f64df | 52 | sPAPRPHBState *sphb; |
3384f95c | 53 | |
8c9f64df AF |
54 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
55 | if (sphb->buid != buid) { | |
3384f95c DG |
56 | continue; |
57 | } | |
8c9f64df | 58 | return sphb; |
9894c5d4 AK |
59 | } |
60 | ||
61 | return NULL; | |
62 | } | |
63 | ||
64 | static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid, | |
65 | uint32_t config_addr) | |
66 | { | |
8c9f64df | 67 | sPAPRPHBState *sphb = find_phb(spapr, buid); |
8558d942 | 68 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 69 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
70 | int devfn = (config_addr >> 8) & 0xFF; |
71 | ||
72 | if (!phb) { | |
73 | return NULL; | |
74 | } | |
3384f95c | 75 | |
5dac82ce | 76 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
77 | } |
78 | ||
3f7565c9 BH |
79 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
80 | { | |
92615a5a | 81 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
82 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
83 | } | |
84 | ||
92615a5a DG |
85 | static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, |
86 | uint32_t addr, uint32_t size, | |
87 | target_ulong rets) | |
88045ac5 | 88 | { |
92615a5a DG |
89 | PCIDevice *pci_dev; |
90 | uint32_t val; | |
91 | ||
92 | if ((size != 1) && (size != 2) && (size != 4)) { | |
93 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 94 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 95 | return; |
88045ac5 | 96 | } |
88045ac5 | 97 | |
92615a5a DG |
98 | pci_dev = find_dev(spapr, buid, addr); |
99 | addr = rtas_pci_cfgaddr(addr); | |
100 | ||
101 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
102 | /* Access must be to a valid device, within bounds and | |
103 | * naturally aligned */ | |
a64d325d | 104 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 105 | return; |
88045ac5 | 106 | } |
92615a5a DG |
107 | |
108 | val = pci_host_config_read_common(pci_dev, addr, | |
109 | pci_config_size(pci_dev), size); | |
110 | ||
a64d325d | 111 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 112 | rtas_st(rets, 1, val); |
88045ac5 AG |
113 | } |
114 | ||
210b580b | 115 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
116 | uint32_t token, uint32_t nargs, |
117 | target_ulong args, | |
118 | uint32_t nret, target_ulong rets) | |
119 | { | |
92615a5a DG |
120 | uint64_t buid; |
121 | uint32_t size, addr; | |
3384f95c | 122 | |
92615a5a | 123 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 124 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
125 | return; |
126 | } | |
92615a5a DG |
127 | |
128 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c | 129 | size = rtas_ld(args, 3); |
92615a5a DG |
130 | addr = rtas_ld(args, 0); |
131 | ||
132 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
133 | } |
134 | ||
210b580b | 135 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
136 | uint32_t token, uint32_t nargs, |
137 | target_ulong args, | |
138 | uint32_t nret, target_ulong rets) | |
139 | { | |
92615a5a | 140 | uint32_t size, addr; |
3384f95c | 141 | |
92615a5a | 142 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 143 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
144 | return; |
145 | } | |
92615a5a | 146 | |
3384f95c | 147 | size = rtas_ld(args, 1); |
92615a5a DG |
148 | addr = rtas_ld(args, 0); |
149 | ||
150 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
151 | } | |
152 | ||
153 | static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, | |
154 | uint32_t addr, uint32_t size, | |
155 | uint32_t val, target_ulong rets) | |
156 | { | |
157 | PCIDevice *pci_dev; | |
158 | ||
159 | if ((size != 1) && (size != 2) && (size != 4)) { | |
160 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 161 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
162 | return; |
163 | } | |
164 | ||
165 | pci_dev = find_dev(spapr, buid, addr); | |
166 | addr = rtas_pci_cfgaddr(addr); | |
167 | ||
168 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
169 | /* Access must be to a valid device, within bounds and | |
170 | * naturally aligned */ | |
a64d325d | 171 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
172 | return; |
173 | } | |
174 | ||
175 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
176 | val, size); | |
177 | ||
a64d325d | 178 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
179 | } |
180 | ||
210b580b | 181 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
182 | uint32_t token, uint32_t nargs, |
183 | target_ulong args, | |
184 | uint32_t nret, target_ulong rets) | |
185 | { | |
92615a5a | 186 | uint64_t buid; |
3384f95c | 187 | uint32_t val, size, addr; |
3384f95c | 188 | |
92615a5a | 189 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 190 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
191 | return; |
192 | } | |
92615a5a DG |
193 | |
194 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c DG |
195 | val = rtas_ld(args, 4); |
196 | size = rtas_ld(args, 3); | |
92615a5a DG |
197 | addr = rtas_ld(args, 0); |
198 | ||
199 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
200 | } |
201 | ||
210b580b | 202 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
203 | uint32_t token, uint32_t nargs, |
204 | target_ulong args, | |
205 | uint32_t nret, target_ulong rets) | |
206 | { | |
207 | uint32_t val, size, addr; | |
3384f95c | 208 | |
92615a5a | 209 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 210 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
211 | return; |
212 | } | |
92615a5a DG |
213 | |
214 | ||
3384f95c DG |
215 | val = rtas_ld(args, 2); |
216 | size = rtas_ld(args, 1); | |
92615a5a DG |
217 | addr = rtas_ld(args, 0); |
218 | ||
219 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
220 | } |
221 | ||
0ee2c058 AK |
222 | /* |
223 | * Set MSI/MSIX message data. | |
224 | * This is required for msi_notify()/msix_notify() which | |
225 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
226 | * |
227 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
228 | * table will be reset. | |
0ee2c058 | 229 | */ |
f1c2dc7c AK |
230 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
231 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
232 | { |
233 | unsigned i; | |
f1c2dc7c | 234 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
235 | |
236 | if (!msix) { | |
237 | msi_set_message(pdev, msg); | |
238 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
239 | return; | |
240 | } | |
241 | ||
9a321e92 | 242 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
243 | msix_set_message(pdev, i, msg); |
244 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
245 | if (addr) { |
246 | ++msg.data; | |
247 | } | |
0ee2c058 AK |
248 | } |
249 | } | |
250 | ||
210b580b | 251 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
0ee2c058 AK |
252 | uint32_t token, uint32_t nargs, |
253 | target_ulong args, uint32_t nret, | |
254 | target_ulong rets) | |
255 | { | |
256 | uint32_t config_addr = rtas_ld(args, 0); | |
257 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
258 | unsigned int func = rtas_ld(args, 3); | |
259 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
260 | unsigned int seq_num = rtas_ld(args, 5); | |
261 | unsigned int ret_intr_type; | |
9a321e92 | 262 | unsigned int irq, max_irqs = 0, num = 0; |
0ee2c058 AK |
263 | sPAPRPHBState *phb = NULL; |
264 | PCIDevice *pdev = NULL; | |
9a321e92 AK |
265 | spapr_pci_msi *msi; |
266 | int *config_addr_key; | |
0ee2c058 AK |
267 | |
268 | switch (func) { | |
269 | case RTAS_CHANGE_MSI_FN: | |
270 | case RTAS_CHANGE_FN: | |
271 | ret_intr_type = RTAS_TYPE_MSI; | |
272 | break; | |
273 | case RTAS_CHANGE_MSIX_FN: | |
274 | ret_intr_type = RTAS_TYPE_MSIX; | |
275 | break; | |
276 | default: | |
295d51aa | 277 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 278 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
279 | return; |
280 | } | |
281 | ||
282 | /* Fins sPAPRPHBState */ | |
283 | phb = find_phb(spapr, buid); | |
284 | if (phb) { | |
285 | pdev = find_dev(spapr, buid, config_addr); | |
286 | } | |
287 | if (!phb || !pdev) { | |
a64d325d | 288 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
289 | return; |
290 | } | |
291 | ||
292 | /* Releasing MSIs */ | |
293 | if (!req_num) { | |
9a321e92 AK |
294 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
295 | if (!msi) { | |
296 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 297 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
298 | return; |
299 | } | |
9a321e92 AK |
300 | |
301 | xics_free(spapr->icp, msi->first_irq, msi->num); | |
32420522 AK |
302 | if (msi_present(pdev)) { |
303 | spapr_msi_setmsg(pdev, 0, false, 0, num); | |
304 | } | |
305 | if (msix_present(pdev)) { | |
306 | spapr_msi_setmsg(pdev, 0, true, 0, num); | |
307 | } | |
9a321e92 AK |
308 | g_hash_table_remove(phb->msi, &config_addr); |
309 | ||
310 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 311 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
312 | rtas_st(rets, 1, 0); |
313 | return; | |
314 | } | |
315 | ||
316 | /* Enabling MSI */ | |
317 | ||
28668b5f AK |
318 | /* Check if the device supports as many IRQs as requested */ |
319 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
320 | max_irqs = msi_nr_vectors_allocated(pdev); | |
321 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
322 | max_irqs = pdev->msix_entries_nr; | |
323 | } | |
324 | if (!max_irqs) { | |
9a321e92 AK |
325 | error_report("Requested interrupt type %d is not enabled for device %x", |
326 | ret_intr_type, config_addr); | |
28668b5f AK |
327 | rtas_st(rets, 0, -1); /* Hardware error */ |
328 | return; | |
329 | } | |
330 | /* Correct the number if the guest asked for too many */ | |
331 | if (req_num > max_irqs) { | |
9a321e92 | 332 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 333 | req_num = max_irqs; |
9a321e92 AK |
334 | irq = 0; /* to avoid misleading trace */ |
335 | goto out; | |
28668b5f AK |
336 | } |
337 | ||
9a321e92 AK |
338 | /* Allocate MSIs */ |
339 | irq = xics_alloc_block(spapr->icp, 0, req_num, false, | |
340 | ret_intr_type == RTAS_TYPE_MSI); | |
341 | if (!irq) { | |
342 | error_report("Cannot allocate MSIs for device %x", config_addr); | |
a64d325d | 343 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
344 | return; |
345 | } | |
346 | ||
0ee2c058 | 347 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 348 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 349 | irq, req_num); |
0ee2c058 | 350 | |
9a321e92 AK |
351 | /* Add MSI device to cache */ |
352 | msi = g_new(spapr_pci_msi, 1); | |
353 | msi->first_irq = irq; | |
354 | msi->num = req_num; | |
355 | config_addr_key = g_new(int, 1); | |
356 | *config_addr_key = config_addr; | |
357 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
358 | ||
359 | out: | |
a64d325d | 360 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
361 | rtas_st(rets, 1, req_num); |
362 | rtas_st(rets, 2, ++seq_num); | |
363 | rtas_st(rets, 3, ret_intr_type); | |
364 | ||
9a321e92 | 365 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
366 | } |
367 | ||
210b580b AL |
368 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
369 | sPAPREnvironment *spapr, | |
0ee2c058 AK |
370 | uint32_t token, |
371 | uint32_t nargs, | |
372 | target_ulong args, | |
373 | uint32_t nret, | |
374 | target_ulong rets) | |
375 | { | |
376 | uint32_t config_addr = rtas_ld(args, 0); | |
377 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
378 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); | |
0ee2c058 | 379 | sPAPRPHBState *phb = NULL; |
9a321e92 AK |
380 | PCIDevice *pdev = NULL; |
381 | spapr_pci_msi *msi; | |
0ee2c058 | 382 | |
9a321e92 | 383 | /* Find sPAPRPHBState */ |
0ee2c058 | 384 | phb = find_phb(spapr, buid); |
9a321e92 AK |
385 | if (phb) { |
386 | pdev = find_dev(spapr, buid, config_addr); | |
387 | } | |
388 | if (!phb || !pdev) { | |
a64d325d | 389 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
390 | return; |
391 | } | |
392 | ||
393 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
394 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
395 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
396 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 397 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
398 | return; |
399 | } | |
9a321e92 | 400 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
401 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
402 | intr_src_num); | |
403 | ||
a64d325d | 404 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
405 | rtas_st(rets, 1, intr_src_num); |
406 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
407 | } | |
408 | ||
7fb0bd34 DG |
409 | static int pci_spapr_swizzle(int slot, int pin) |
410 | { | |
411 | return (slot + pin) % PCI_NUM_PINS; | |
412 | } | |
413 | ||
3384f95c DG |
414 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
415 | { | |
416 | /* | |
417 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
418 | * which is less than number of IRQs on the specific bus (4). We |
419 | * use standard PCI swizzling, that is (slot number + pin number) | |
420 | * % 4. | |
3384f95c | 421 | */ |
7fb0bd34 | 422 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
423 | } |
424 | ||
425 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
426 | { | |
427 | /* | |
428 | * Here we use the number returned by pci_spapr_map_irq to find a | |
429 | * corresponding qemu_irq. | |
430 | */ | |
431 | sPAPRPHBState *phb = opaque; | |
432 | ||
caae58cb | 433 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 434 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
435 | } |
436 | ||
5cc7a967 AK |
437 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
438 | { | |
439 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); | |
440 | PCIINTxRoute route; | |
441 | ||
442 | route.mode = PCI_INTX_ENABLED; | |
443 | route.irq = sphb->lsi_table[pin].irq; | |
444 | ||
445 | return route; | |
446 | } | |
447 | ||
0ee2c058 AK |
448 | /* |
449 | * MSI/MSIX memory region implementation. | |
450 | * The handler handles both MSI and MSIX. | |
451 | * For MSI-X, the vector number is encoded as a part of the address, | |
452 | * data is set to 0. | |
453 | * For MSI, the vector number is encoded in least bits in data. | |
454 | */ | |
a8170e5e | 455 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
456 | uint64_t data, unsigned size) |
457 | { | |
f1c2dc7c | 458 | uint32_t irq = data; |
0ee2c058 AK |
459 | |
460 | trace_spapr_pci_msi_write(addr, data, irq); | |
461 | ||
462 | qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); | |
463 | } | |
464 | ||
465 | static const MemoryRegionOps spapr_msi_ops = { | |
466 | /* There is no .read as the read result is undefined by PCI spec */ | |
467 | .read = NULL, | |
468 | .write = spapr_msi_write, | |
469 | .endianness = DEVICE_LITTLE_ENDIAN | |
470 | }; | |
471 | ||
298a9710 DG |
472 | /* |
473 | * PHB PCI device | |
474 | */ | |
e00387d5 | 475 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
476 | { |
477 | sPAPRPHBState *phb = opaque; | |
478 | ||
e00387d5 | 479 | return &phb->iommu_as; |
edded454 DG |
480 | } |
481 | ||
c6ba42f6 | 482 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 483 | { |
c6ba42f6 | 484 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
8c9f64df | 485 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 486 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
da6ccee4 | 487 | sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); |
298a9710 DG |
488 | char *namebuf; |
489 | int i; | |
3384f95c | 490 | PCIBus *bus; |
8c46f7ec | 491 | uint64_t msi_window_size = 4096; |
3384f95c | 492 | |
caae58cb DG |
493 | if (sphb->index != -1) { |
494 | hwaddr windows_base; | |
495 | ||
496 | if ((sphb->buid != -1) || (sphb->dma_liobn != -1) | |
497 | || (sphb->mem_win_addr != -1) | |
f1c2dc7c | 498 | || (sphb->io_win_addr != -1)) { |
c6ba42f6 AK |
499 | error_setg(errp, "Either \"index\" or other parameters must" |
500 | " be specified for PAPR PHB, not both"); | |
501 | return; | |
caae58cb DG |
502 | } |
503 | ||
504 | sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; | |
505 | sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN + sphb->index; | |
506 | ||
507 | windows_base = SPAPR_PCI_WINDOW_BASE | |
508 | + sphb->index * SPAPR_PCI_WINDOW_SPACING; | |
509 | sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; | |
510 | sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; | |
caae58cb DG |
511 | } |
512 | ||
513 | if (sphb->buid == -1) { | |
c6ba42f6 AK |
514 | error_setg(errp, "BUID not specified for PHB"); |
515 | return; | |
caae58cb DG |
516 | } |
517 | ||
518 | if (sphb->dma_liobn == -1) { | |
c6ba42f6 AK |
519 | error_setg(errp, "LIOBN not specified for PHB"); |
520 | return; | |
caae58cb DG |
521 | } |
522 | ||
523 | if (sphb->mem_win_addr == -1) { | |
c6ba42f6 AK |
524 | error_setg(errp, "Memory window address not specified for PHB"); |
525 | return; | |
caae58cb DG |
526 | } |
527 | ||
528 | if (sphb->io_win_addr == -1) { | |
c6ba42f6 AK |
529 | error_setg(errp, "IO window address not specified for PHB"); |
530 | return; | |
caae58cb DG |
531 | } |
532 | ||
caae58cb | 533 | if (find_phb(spapr, sphb->buid)) { |
c6ba42f6 AK |
534 | error_setg(errp, "PCI host bridges must have unique BUIDs"); |
535 | return; | |
caae58cb DG |
536 | } |
537 | ||
8c9f64df | 538 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 539 | |
8c9f64df | 540 | namebuf = alloca(strlen(sphb->dtbusname) + 32); |
3384f95c | 541 | |
298a9710 | 542 | /* Initialize memory regions */ |
8c9f64df | 543 | sprintf(namebuf, "%s.mmio", sphb->dtbusname); |
92b8e39c | 544 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
3384f95c | 545 | |
8c9f64df | 546 | sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); |
40c5dce9 PB |
547 | memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), |
548 | namebuf, &sphb->memspace, | |
8c9f64df AF |
549 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
550 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, | |
551 | &sphb->memwindow); | |
3384f95c | 552 | |
fabe9ee1 | 553 | /* Initialize IO regions */ |
8c9f64df | 554 | sprintf(namebuf, "%s.io", sphb->dtbusname); |
40c5dce9 PB |
555 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
556 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
3384f95c | 557 | |
a3cfa18e | 558 | sprintf(namebuf, "%s.io-alias", sphb->dtbusname); |
66aab867 | 559 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 560 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
8c9f64df | 561 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 562 | &sphb->iowindow); |
1b8601b0 AK |
563 | |
564 | bus = pci_register_bus(dev, NULL, | |
8c9f64df AF |
565 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, |
566 | &sphb->memspace, &sphb->iospace, | |
60a0e443 | 567 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); |
8c9f64df | 568 | phb->bus = bus; |
298a9710 | 569 | |
cca7fad5 AK |
570 | /* |
571 | * Initialize PHB address space. | |
572 | * By default there will be at least one subregion for default | |
573 | * 32bit DMA window. | |
574 | * Later the guest might want to create another DMA window | |
575 | * which will become another memory subregion. | |
576 | */ | |
577 | sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); | |
578 | ||
579 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), | |
580 | namebuf, UINT64_MAX); | |
581 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, | |
582 | sphb->dtbusname); | |
583 | ||
8c46f7ec GK |
584 | /* |
585 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
586 | * we need to allocate some memory to catch those writes coming | |
587 | * from msi_notify()/msix_notify(). | |
588 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
589 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
590 | * be used. | |
591 | * | |
592 | * For KVM we want to ensure that this memory is a full page so that | |
593 | * our memory slot is of page size granularity. | |
594 | */ | |
595 | #ifdef CONFIG_KVM | |
596 | if (kvm_enabled()) { | |
597 | msi_window_size = getpagesize(); | |
598 | } | |
599 | #endif | |
600 | ||
601 | memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, | |
602 | "msi", msi_window_size); | |
603 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
604 | &sphb->msiwindow); | |
605 | ||
e00387d5 | 606 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 607 | |
5cc7a967 AK |
608 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
609 | ||
8c9f64df | 610 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
611 | |
612 | /* Initialize the LSI table */ | |
7fb0bd34 | 613 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 614 | uint32_t irq; |
298a9710 | 615 | |
bee763db | 616 | irq = xics_alloc_block(spapr->icp, 0, 1, true, false); |
a307d594 | 617 | if (!irq) { |
c6ba42f6 AK |
618 | error_setg(errp, "spapr_allocate_lsi failed"); |
619 | return; | |
298a9710 DG |
620 | } |
621 | ||
8c9f64df | 622 | sphb->lsi_table[i].irq = irq; |
298a9710 | 623 | } |
da6ccee4 AK |
624 | |
625 | if (!info->finish_realize) { | |
626 | error_setg(errp, "finish_realize not defined"); | |
627 | return; | |
628 | } | |
629 | ||
630 | info->finish_realize(sphb, errp); | |
9a321e92 AK |
631 | |
632 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); | |
da6ccee4 AK |
633 | } |
634 | ||
635 | static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) | |
636 | { | |
e28c16f6 AK |
637 | sPAPRTCETable *tcet; |
638 | ||
e28c16f6 | 639 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, |
1b8eceee | 640 | 0, |
650f33ad | 641 | SPAPR_TCE_PAGE_SHIFT, |
9bb62a07 | 642 | 0x40000000 >> SPAPR_TCE_PAGE_SHIFT, false); |
e28c16f6 | 643 | if (!tcet) { |
da6ccee4 AK |
644 | error_setg(errp, "Unable to create TCE table for %s", |
645 | sphb->dtbusname); | |
646 | return ; | |
647 | } | |
cca7fad5 AK |
648 | |
649 | /* Register default 32bit DMA window */ | |
650 | memory_region_add_subregion(&sphb->iommu_root, 0, | |
e28c16f6 | 651 | spapr_tce_get_iommu(tcet)); |
298a9710 DG |
652 | } |
653 | ||
e28c16f6 | 654 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 655 | { |
e28c16f6 AK |
656 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
657 | ||
658 | if (dev) { | |
659 | device_reset(dev); | |
660 | } | |
eddeed26 | 661 | |
e28c16f6 AK |
662 | return 0; |
663 | } | |
664 | ||
665 | static void spapr_phb_reset(DeviceState *qdev) | |
666 | { | |
eddeed26 | 667 | /* Reset the IOMMU state */ |
e28c16f6 | 668 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
eddeed26 DG |
669 | } |
670 | ||
298a9710 | 671 | static Property spapr_phb_properties[] = { |
caae58cb | 672 | DEFINE_PROP_INT32("index", sPAPRPHBState, index, -1), |
c7bcc85d PB |
673 | DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), |
674 | DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), | |
675 | DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), | |
676 | DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, | |
677 | SPAPR_PCI_MMIO_WIN_SIZE), | |
678 | DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), | |
679 | DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, | |
680 | SPAPR_PCI_IO_WIN_SIZE), | |
298a9710 DG |
681 | DEFINE_PROP_END_OF_LIST(), |
682 | }; | |
683 | ||
1112cf94 DG |
684 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
685 | .name = "spapr_pci/lsi", | |
686 | .version_id = 1, | |
687 | .minimum_version_id = 1, | |
3aff6c2f | 688 | .fields = (VMStateField[]) { |
1112cf94 DG |
689 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), |
690 | ||
691 | VMSTATE_END_OF_LIST() | |
692 | }, | |
693 | }; | |
694 | ||
695 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 696 | .name = "spapr_pci/msi", |
1112cf94 DG |
697 | .version_id = 1, |
698 | .minimum_version_id = 1, | |
9a321e92 AK |
699 | .fields = (VMStateField []) { |
700 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
701 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
702 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
703 | VMSTATE_END_OF_LIST() |
704 | }, | |
705 | }; | |
706 | ||
f8833a37 PM |
707 | static void spapr_pci_fill_msi_devs(gpointer key, gpointer value, |
708 | gpointer opaque) | |
709 | { | |
710 | sPAPRPHBState *sphb = opaque; | |
711 | ||
712 | sphb->msi_devs[sphb->msi_devs_num].key = *(uint32_t *)key; | |
713 | sphb->msi_devs[sphb->msi_devs_num].value = *(spapr_pci_msi *)value; | |
714 | sphb->msi_devs_num++; | |
715 | } | |
716 | ||
9a321e92 AK |
717 | static void spapr_pci_pre_save(void *opaque) |
718 | { | |
719 | sPAPRPHBState *sphb = opaque; | |
f8833a37 | 720 | int msi_devs_num; |
9a321e92 AK |
721 | |
722 | if (sphb->msi_devs) { | |
723 | g_free(sphb->msi_devs); | |
724 | sphb->msi_devs = NULL; | |
725 | } | |
f8833a37 PM |
726 | sphb->msi_devs_num = 0; |
727 | msi_devs_num = g_hash_table_size(sphb->msi); | |
728 | if (!msi_devs_num) { | |
9a321e92 AK |
729 | return; |
730 | } | |
f8833a37 | 731 | sphb->msi_devs = g_malloc(msi_devs_num * sizeof(spapr_pci_msi_mig)); |
9a321e92 | 732 | |
f8833a37 PM |
733 | g_hash_table_foreach(sphb->msi, spapr_pci_fill_msi_devs, sphb); |
734 | assert(sphb->msi_devs_num == msi_devs_num); | |
9a321e92 AK |
735 | } |
736 | ||
737 | static int spapr_pci_post_load(void *opaque, int version_id) | |
738 | { | |
739 | sPAPRPHBState *sphb = opaque; | |
740 | gpointer key, value; | |
741 | int i; | |
742 | ||
743 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
744 | key = g_memdup(&sphb->msi_devs[i].key, | |
745 | sizeof(sphb->msi_devs[i].key)); | |
746 | value = g_memdup(&sphb->msi_devs[i].value, | |
747 | sizeof(sphb->msi_devs[i].value)); | |
748 | g_hash_table_insert(sphb->msi, key, value); | |
749 | } | |
750 | if (sphb->msi_devs) { | |
751 | g_free(sphb->msi_devs); | |
752 | sphb->msi_devs = NULL; | |
753 | } | |
754 | sphb->msi_devs_num = 0; | |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
1112cf94 DG |
759 | static const VMStateDescription vmstate_spapr_pci = { |
760 | .name = "spapr_pci", | |
9a321e92 AK |
761 | .version_id = 2, |
762 | .minimum_version_id = 2, | |
763 | .pre_save = spapr_pci_pre_save, | |
764 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 765 | .fields = (VMStateField[]) { |
1112cf94 DG |
766 | VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), |
767 | VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), | |
768 | VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), | |
769 | VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), | |
770 | VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), | |
771 | VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), | |
1112cf94 DG |
772 | VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, |
773 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), | |
9a321e92 AK |
774 | VMSTATE_INT32(msi_devs_num, sPAPRPHBState), |
775 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, | |
776 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), | |
1112cf94 DG |
777 | VMSTATE_END_OF_LIST() |
778 | }, | |
779 | }; | |
780 | ||
568f0690 DG |
781 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
782 | PCIBus *rootbus) | |
783 | { | |
784 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
785 | ||
786 | return sphb->dtbusname; | |
787 | } | |
788 | ||
298a9710 DG |
789 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
790 | { | |
568f0690 | 791 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 792 | DeviceClass *dc = DEVICE_CLASS(klass); |
da6ccee4 | 793 | sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 794 | |
568f0690 | 795 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 796 | dc->realize = spapr_phb_realize; |
298a9710 | 797 | dc->props = spapr_phb_properties; |
eddeed26 | 798 | dc->reset = spapr_phb_reset; |
1112cf94 | 799 | dc->vmsd = &vmstate_spapr_pci; |
09aa9a52 AK |
800 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
801 | dc->cannot_instantiate_with_device_add_yet = false; | |
da6ccee4 | 802 | spc->finish_realize = spapr_phb_finish_realize; |
298a9710 | 803 | } |
3384f95c | 804 | |
4240abff | 805 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 806 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 807 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
808 | .instance_size = sizeof(sPAPRPHBState), |
809 | .class_init = spapr_phb_class_init, | |
da6ccee4 | 810 | .class_size = sizeof(sPAPRPHBClass), |
298a9710 DG |
811 | }; |
812 | ||
89dfd6e1 | 813 | PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index) |
298a9710 DG |
814 | { |
815 | DeviceState *dev; | |
816 | ||
8c9f64df | 817 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 818 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 819 | qdev_init_nofail(dev); |
caae58cb DG |
820 | |
821 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
822 | } |
823 | ||
824 | /* Macros to operate with address in OF binding to PCI */ | |
825 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
826 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
827 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
828 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
829 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
830 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
831 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
832 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
833 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
834 | ||
e28c16f6 AK |
835 | typedef struct sPAPRTCEDT { |
836 | void *fdt; | |
837 | int node_off; | |
838 | } sPAPRTCEDT; | |
839 | ||
840 | static int spapr_phb_children_dt(Object *child, void *opaque) | |
841 | { | |
842 | sPAPRTCEDT *p = opaque; | |
843 | sPAPRTCETable *tcet; | |
844 | ||
845 | tcet = (sPAPRTCETable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE); | |
846 | if (!tcet) { | |
847 | return 0; | |
848 | } | |
849 | ||
850 | spapr_dma_dt(p->fdt, p->node_off, "ibm,dma-window", | |
1b8eceee AK |
851 | tcet->liobn, tcet->bus_offset, |
852 | tcet->nb_table << tcet->page_shift); | |
e28c16f6 AK |
853 | /* Stop after the first window */ |
854 | ||
855 | return 1; | |
856 | } | |
857 | ||
e0fdbd7c AK |
858 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
859 | uint32_t xics_phandle, | |
860 | void *fdt) | |
3384f95c | 861 | { |
7fb0bd34 | 862 | int bus_off, i, j; |
3384f95c | 863 | char nodename[256]; |
3384f95c DG |
864 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
865 | struct { | |
866 | uint32_t hi; | |
867 | uint64_t child; | |
868 | uint64_t parent; | |
869 | uint64_t size; | |
c4889f54 | 870 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
871 | { |
872 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
873 | cpu_to_be64(phb->io_win_addr), | |
874 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
875 | }, | |
876 | { | |
877 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
878 | cpu_to_be64(phb->mem_win_addr), | |
879 | cpu_to_be64(memory_region_size(&phb->memwindow)), | |
880 | }, | |
881 | }; | |
882 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; | |
883 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
884 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
885 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
3384f95c DG |
886 | |
887 | /* Start populating the FDT */ | |
888 | sprintf(nodename, "pci@%" PRIx64, phb->buid); | |
889 | bus_off = fdt_add_subnode(fdt, 0, nodename); | |
890 | if (bus_off < 0) { | |
891 | return bus_off; | |
892 | } | |
893 | ||
894 | #define _FDT(exp) \ | |
895 | do { \ | |
896 | int ret = (exp); \ | |
897 | if (ret < 0) { \ | |
898 | return ret; \ | |
899 | } \ | |
900 | } while (0) | |
901 | ||
902 | /* Write PHB properties */ | |
903 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
904 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
905 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
906 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
907 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
908 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
909 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
910 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges))); | |
911 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); | |
3f7565c9 | 912 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
9dbae977 | 913 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); |
3384f95c | 914 | |
4d8d5467 BH |
915 | /* Build the interrupt-map, this must matches what is done |
916 | * in pci_spapr_map_irq | |
917 | */ | |
918 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
919 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
920 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
921 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
922 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
923 | int lsi_num = pci_spapr_swizzle(i, j); | |
924 | ||
925 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
926 | irqmap[1] = 0; | |
927 | irqmap[2] = 0; | |
928 | irqmap[3] = cpu_to_be32(j+1); | |
929 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 930 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
931 | irqmap[6] = cpu_to_be32(0x8); |
932 | } | |
3384f95c | 933 | } |
3384f95c DG |
934 | /* Write interrupt map */ |
935 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 936 | sizeof(interrupt_map))); |
3384f95c | 937 | |
e28c16f6 AK |
938 | object_child_foreach(OBJECT(phb), spapr_phb_children_dt, |
939 | &((sPAPRTCEDT){ .fdt = fdt, .node_off = bus_off })); | |
edded454 | 940 | |
3384f95c DG |
941 | return 0; |
942 | } | |
298a9710 | 943 | |
fa28f71b AK |
944 | void spapr_pci_rtas_init(void) |
945 | { | |
3a3b8502 AK |
946 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
947 | rtas_read_pci_config); | |
948 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
949 | rtas_write_pci_config); | |
950 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
951 | rtas_ibm_read_pci_config); | |
952 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
953 | rtas_ibm_write_pci_config); | |
0ee2c058 | 954 | if (msi_supported) { |
3a3b8502 AK |
955 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
956 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 957 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
958 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
959 | rtas_ibm_change_msi); | |
0ee2c058 | 960 | } |
fa28f71b AK |
961 | } |
962 | ||
8c9f64df | 963 | static void spapr_pci_register_types(void) |
298a9710 DG |
964 | { |
965 | type_register_static(&spapr_phb_info); | |
966 | } | |
8c9f64df AF |
967 | |
968 | type_init(spapr_pci_register_types) |