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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0d75590d | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 PB |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" | |
83c9f4ca | 29 | #include "hw/hw.h" |
1d2d9742 | 30 | #include "hw/sysbus.h" |
83c9f4ca PB |
31 | #include "hw/pci/pci.h" |
32 | #include "hw/pci/msi.h" | |
33 | #include "hw/pci/msix.h" | |
34 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
35 | #include "hw/ppc/spapr.h" |
36 | #include "hw/pci-host/spapr.h" | |
022c62cb | 37 | #include "exec/address-spaces.h" |
ae4de14c | 38 | #include "exec/ram_addr.h" |
3384f95c | 39 | #include <libfdt.h> |
a2950fb6 | 40 | #include "trace.h" |
295d51aa | 41 | #include "qemu/error-report.h" |
7454c7af | 42 | #include "qapi/qmp/qerror.h" |
99372e78 | 43 | #include "hw/ppc/fdt.h" |
1d2d9742 | 44 | #include "hw/pci/pci_bridge.h" |
06aac7bd | 45 | #include "hw/pci/pci_bus.h" |
2530a1a5 | 46 | #include "hw/pci/pci_ids.h" |
62083979 | 47 | #include "hw/ppc/spapr_drc.h" |
7454c7af | 48 | #include "sysemu/device_tree.h" |
77ac58dd | 49 | #include "sysemu/kvm.h" |
ae4de14c | 50 | #include "sysemu/hostmem.h" |
4814401f | 51 | #include "sysemu/numa.h" |
3384f95c | 52 | |
0ee2c058 AK |
53 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
54 | #define RTAS_QUERY_FN 0 | |
55 | #define RTAS_CHANGE_FN 1 | |
56 | #define RTAS_RESET_FN 2 | |
57 | #define RTAS_CHANGE_MSI_FN 3 | |
58 | #define RTAS_CHANGE_MSIX_FN 4 | |
59 | ||
60 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
61 | #define RTAS_TYPE_MSI 1 | |
62 | #define RTAS_TYPE_MSIX 2 | |
63 | ||
28e02042 | 64 | sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) |
3384f95c | 65 | { |
8c9f64df | 66 | sPAPRPHBState *sphb; |
3384f95c | 67 | |
8c9f64df AF |
68 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
69 | if (sphb->buid != buid) { | |
3384f95c DG |
70 | continue; |
71 | } | |
8c9f64df | 72 | return sphb; |
9894c5d4 AK |
73 | } |
74 | ||
75 | return NULL; | |
76 | } | |
77 | ||
28e02042 | 78 | PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, |
46c5874e | 79 | uint32_t config_addr) |
9894c5d4 | 80 | { |
46c5874e | 81 | sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 82 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 83 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
84 | int devfn = (config_addr >> 8) & 0xFF; |
85 | ||
86 | if (!phb) { | |
87 | return NULL; | |
88 | } | |
3384f95c | 89 | |
5dac82ce | 90 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
91 | } |
92 | ||
3f7565c9 BH |
93 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
94 | { | |
92615a5a | 95 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
96 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
97 | } | |
98 | ||
28e02042 | 99 | static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
100 | uint32_t addr, uint32_t size, |
101 | target_ulong rets) | |
88045ac5 | 102 | { |
92615a5a DG |
103 | PCIDevice *pci_dev; |
104 | uint32_t val; | |
105 | ||
106 | if ((size != 1) && (size != 2) && (size != 4)) { | |
107 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 108 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 109 | return; |
88045ac5 | 110 | } |
88045ac5 | 111 | |
46c5874e | 112 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
113 | addr = rtas_pci_cfgaddr(addr); |
114 | ||
115 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
116 | /* Access must be to a valid device, within bounds and | |
117 | * naturally aligned */ | |
a64d325d | 118 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 119 | return; |
88045ac5 | 120 | } |
92615a5a DG |
121 | |
122 | val = pci_host_config_read_common(pci_dev, addr, | |
123 | pci_config_size(pci_dev), size); | |
124 | ||
a64d325d | 125 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 126 | rtas_st(rets, 1, val); |
88045ac5 AG |
127 | } |
128 | ||
28e02042 | 129 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
130 | uint32_t token, uint32_t nargs, |
131 | target_ulong args, | |
132 | uint32_t nret, target_ulong rets) | |
133 | { | |
92615a5a DG |
134 | uint64_t buid; |
135 | uint32_t size, addr; | |
3384f95c | 136 | |
92615a5a | 137 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 138 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
139 | return; |
140 | } | |
92615a5a | 141 | |
a14aa92b | 142 | buid = rtas_ldq(args, 1); |
3384f95c | 143 | size = rtas_ld(args, 3); |
92615a5a DG |
144 | addr = rtas_ld(args, 0); |
145 | ||
146 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
147 | } |
148 | ||
28e02042 | 149 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
150 | uint32_t token, uint32_t nargs, |
151 | target_ulong args, | |
152 | uint32_t nret, target_ulong rets) | |
153 | { | |
92615a5a | 154 | uint32_t size, addr; |
3384f95c | 155 | |
92615a5a | 156 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 157 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
158 | return; |
159 | } | |
92615a5a | 160 | |
3384f95c | 161 | size = rtas_ld(args, 1); |
92615a5a DG |
162 | addr = rtas_ld(args, 0); |
163 | ||
164 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
165 | } | |
166 | ||
28e02042 | 167 | static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
168 | uint32_t addr, uint32_t size, |
169 | uint32_t val, target_ulong rets) | |
170 | { | |
171 | PCIDevice *pci_dev; | |
172 | ||
173 | if ((size != 1) && (size != 2) && (size != 4)) { | |
174 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 175 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
176 | return; |
177 | } | |
178 | ||
46c5874e | 179 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
180 | addr = rtas_pci_cfgaddr(addr); |
181 | ||
182 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
183 | /* Access must be to a valid device, within bounds and | |
184 | * naturally aligned */ | |
a64d325d | 185 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
186 | return; |
187 | } | |
188 | ||
189 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
190 | val, size); | |
191 | ||
a64d325d | 192 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
193 | } |
194 | ||
28e02042 | 195 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
196 | uint32_t token, uint32_t nargs, |
197 | target_ulong args, | |
198 | uint32_t nret, target_ulong rets) | |
199 | { | |
92615a5a | 200 | uint64_t buid; |
3384f95c | 201 | uint32_t val, size, addr; |
3384f95c | 202 | |
92615a5a | 203 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 204 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
205 | return; |
206 | } | |
92615a5a | 207 | |
a14aa92b | 208 | buid = rtas_ldq(args, 1); |
3384f95c DG |
209 | val = rtas_ld(args, 4); |
210 | size = rtas_ld(args, 3); | |
92615a5a DG |
211 | addr = rtas_ld(args, 0); |
212 | ||
213 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
214 | } |
215 | ||
28e02042 | 216 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
217 | uint32_t token, uint32_t nargs, |
218 | target_ulong args, | |
219 | uint32_t nret, target_ulong rets) | |
220 | { | |
221 | uint32_t val, size, addr; | |
3384f95c | 222 | |
92615a5a | 223 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 224 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
225 | return; |
226 | } | |
92615a5a DG |
227 | |
228 | ||
3384f95c DG |
229 | val = rtas_ld(args, 2); |
230 | size = rtas_ld(args, 1); | |
92615a5a DG |
231 | addr = rtas_ld(args, 0); |
232 | ||
233 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
234 | } |
235 | ||
0ee2c058 AK |
236 | /* |
237 | * Set MSI/MSIX message data. | |
238 | * This is required for msi_notify()/msix_notify() which | |
239 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
240 | * |
241 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
242 | * table will be reset. | |
0ee2c058 | 243 | */ |
f1c2dc7c AK |
244 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
245 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
246 | { |
247 | unsigned i; | |
f1c2dc7c | 248 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
249 | |
250 | if (!msix) { | |
251 | msi_set_message(pdev, msg); | |
252 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
253 | return; | |
254 | } | |
255 | ||
9a321e92 | 256 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
257 | msix_set_message(pdev, i, msg); |
258 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
259 | if (addr) { |
260 | ++msg.data; | |
261 | } | |
0ee2c058 AK |
262 | } |
263 | } | |
264 | ||
28e02042 | 265 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
0ee2c058 AK |
266 | uint32_t token, uint32_t nargs, |
267 | target_ulong args, uint32_t nret, | |
268 | target_ulong rets) | |
269 | { | |
270 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 271 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 AK |
272 | unsigned int func = rtas_ld(args, 3); |
273 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
274 | unsigned int seq_num = rtas_ld(args, 5); | |
275 | unsigned int ret_intr_type; | |
d4a63ac8 | 276 | unsigned int irq, max_irqs = 0; |
0ee2c058 AK |
277 | sPAPRPHBState *phb = NULL; |
278 | PCIDevice *pdev = NULL; | |
9a321e92 AK |
279 | spapr_pci_msi *msi; |
280 | int *config_addr_key; | |
a005b3ef | 281 | Error *err = NULL; |
4fe75a8c | 282 | int i; |
0ee2c058 | 283 | |
9cbe305b GK |
284 | /* Fins sPAPRPHBState */ |
285 | phb = spapr_pci_find_phb(spapr, buid); | |
286 | if (phb) { | |
287 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); | |
288 | } | |
289 | if (!phb || !pdev) { | |
290 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
291 | return; | |
292 | } | |
293 | ||
0ee2c058 | 294 | switch (func) { |
0ee2c058 | 295 | case RTAS_CHANGE_FN: |
9cbe305b GK |
296 | if (msi_present(pdev)) { |
297 | ret_intr_type = RTAS_TYPE_MSI; | |
298 | } else if (msix_present(pdev)) { | |
299 | ret_intr_type = RTAS_TYPE_MSIX; | |
300 | } else { | |
301 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
302 | return; | |
303 | } | |
304 | break; | |
305 | case RTAS_CHANGE_MSI_FN: | |
306 | if (msi_present(pdev)) { | |
307 | ret_intr_type = RTAS_TYPE_MSI; | |
308 | } else { | |
309 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
310 | return; | |
311 | } | |
0ee2c058 AK |
312 | break; |
313 | case RTAS_CHANGE_MSIX_FN: | |
9cbe305b GK |
314 | if (msix_present(pdev)) { |
315 | ret_intr_type = RTAS_TYPE_MSIX; | |
316 | } else { | |
317 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
318 | return; | |
319 | } | |
0ee2c058 AK |
320 | break; |
321 | default: | |
295d51aa | 322 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 323 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
324 | return; |
325 | } | |
326 | ||
ce266b75 GK |
327 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
328 | ||
0ee2c058 AK |
329 | /* Releasing MSIs */ |
330 | if (!req_num) { | |
9a321e92 AK |
331 | if (!msi) { |
332 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 333 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
334 | return; |
335 | } | |
9a321e92 | 336 | |
60c6823b | 337 | spapr_irq_free(spapr, msi->first_irq, msi->num); |
32420522 | 338 | if (msi_present(pdev)) { |
d4a63ac8 | 339 | spapr_msi_setmsg(pdev, 0, false, 0, 0); |
32420522 AK |
340 | } |
341 | if (msix_present(pdev)) { | |
d4a63ac8 | 342 | spapr_msi_setmsg(pdev, 0, true, 0, 0); |
32420522 | 343 | } |
9a321e92 AK |
344 | g_hash_table_remove(phb->msi, &config_addr); |
345 | ||
346 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 347 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
348 | rtas_st(rets, 1, 0); |
349 | return; | |
350 | } | |
351 | ||
352 | /* Enabling MSI */ | |
353 | ||
28668b5f AK |
354 | /* Check if the device supports as many IRQs as requested */ |
355 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
356 | max_irqs = msi_nr_vectors_allocated(pdev); | |
357 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
358 | max_irqs = pdev->msix_entries_nr; | |
359 | } | |
360 | if (!max_irqs) { | |
9a321e92 AK |
361 | error_report("Requested interrupt type %d is not enabled for device %x", |
362 | ret_intr_type, config_addr); | |
28668b5f AK |
363 | rtas_st(rets, 0, -1); /* Hardware error */ |
364 | return; | |
365 | } | |
366 | /* Correct the number if the guest asked for too many */ | |
367 | if (req_num > max_irqs) { | |
9a321e92 | 368 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 369 | req_num = max_irqs; |
9a321e92 AK |
370 | irq = 0; /* to avoid misleading trace */ |
371 | goto out; | |
28668b5f AK |
372 | } |
373 | ||
9a321e92 | 374 | /* Allocate MSIs */ |
4fe75a8c | 375 | irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, &err); |
a005b3ef GK |
376 | if (err) { |
377 | error_reportf_err(err, "Can't allocate MSIs for device %x: ", | |
378 | config_addr); | |
a64d325d | 379 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
380 | return; |
381 | } | |
382 | ||
4fe75a8c CLG |
383 | for (i = 0; i < req_num; i++) { |
384 | spapr_irq_claim(spapr, irq + i, false, &err); | |
385 | if (err) { | |
386 | error_reportf_err(err, "Can't allocate MSIs for device %x: ", | |
387 | config_addr); | |
388 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); | |
389 | return; | |
390 | } | |
391 | } | |
392 | ||
ce266b75 GK |
393 | /* Release previous MSIs */ |
394 | if (msi) { | |
60c6823b | 395 | spapr_irq_free(spapr, msi->first_irq, msi->num); |
ce266b75 GK |
396 | g_hash_table_remove(phb->msi, &config_addr); |
397 | } | |
398 | ||
0ee2c058 | 399 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 400 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 401 | irq, req_num); |
0ee2c058 | 402 | |
9a321e92 AK |
403 | /* Add MSI device to cache */ |
404 | msi = g_new(spapr_pci_msi, 1); | |
405 | msi->first_irq = irq; | |
406 | msi->num = req_num; | |
407 | config_addr_key = g_new(int, 1); | |
408 | *config_addr_key = config_addr; | |
409 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
410 | ||
411 | out: | |
a64d325d | 412 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
413 | rtas_st(rets, 1, req_num); |
414 | rtas_st(rets, 2, ++seq_num); | |
b359bd6a SB |
415 | if (nret > 3) { |
416 | rtas_st(rets, 3, ret_intr_type); | |
417 | } | |
0ee2c058 | 418 | |
9a321e92 | 419 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
420 | } |
421 | ||
210b580b | 422 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
28e02042 | 423 | sPAPRMachineState *spapr, |
0ee2c058 AK |
424 | uint32_t token, |
425 | uint32_t nargs, | |
426 | target_ulong args, | |
427 | uint32_t nret, | |
428 | target_ulong rets) | |
429 | { | |
430 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 431 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 | 432 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); |
0ee2c058 | 433 | sPAPRPHBState *phb = NULL; |
9a321e92 AK |
434 | PCIDevice *pdev = NULL; |
435 | spapr_pci_msi *msi; | |
0ee2c058 | 436 | |
9a321e92 | 437 | /* Find sPAPRPHBState */ |
46c5874e | 438 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 439 | if (phb) { |
46c5874e | 440 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
441 | } |
442 | if (!phb || !pdev) { | |
a64d325d | 443 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
444 | return; |
445 | } | |
446 | ||
447 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
448 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
449 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
450 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 451 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
452 | return; |
453 | } | |
9a321e92 | 454 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
455 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
456 | intr_src_num); | |
457 | ||
a64d325d | 458 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
459 | rtas_st(rets, 1, intr_src_num); |
460 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
461 | } | |
462 | ||
ee954280 | 463 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
28e02042 | 464 | sPAPRMachineState *spapr, |
ee954280 GS |
465 | uint32_t token, uint32_t nargs, |
466 | target_ulong args, uint32_t nret, | |
467 | target_ulong rets) | |
468 | { | |
469 | sPAPRPHBState *sphb; | |
ee954280 GS |
470 | uint32_t addr, option; |
471 | uint64_t buid; | |
472 | int ret; | |
473 | ||
474 | if ((nargs != 4) || (nret != 1)) { | |
475 | goto param_error_exit; | |
476 | } | |
477 | ||
a14aa92b | 478 | buid = rtas_ldq(args, 1); |
ee954280 GS |
479 | addr = rtas_ld(args, 0); |
480 | option = rtas_ld(args, 3); | |
481 | ||
46c5874e | 482 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
483 | if (!sphb) { |
484 | goto param_error_exit; | |
485 | } | |
486 | ||
fbb4e983 | 487 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
488 | goto param_error_exit; |
489 | } | |
490 | ||
fbb4e983 | 491 | ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); |
ee954280 GS |
492 | rtas_st(rets, 0, ret); |
493 | return; | |
494 | ||
495 | param_error_exit: | |
496 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
497 | } | |
498 | ||
499 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
28e02042 | 500 | sPAPRMachineState *spapr, |
ee954280 GS |
501 | uint32_t token, uint32_t nargs, |
502 | target_ulong args, uint32_t nret, | |
503 | target_ulong rets) | |
504 | { | |
505 | sPAPRPHBState *sphb; | |
ee954280 GS |
506 | PCIDevice *pdev; |
507 | uint32_t addr, option; | |
508 | uint64_t buid; | |
509 | ||
510 | if ((nargs != 4) || (nret != 2)) { | |
511 | goto param_error_exit; | |
512 | } | |
513 | ||
a14aa92b | 514 | buid = rtas_ldq(args, 1); |
46c5874e | 515 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
516 | if (!sphb) { |
517 | goto param_error_exit; | |
518 | } | |
519 | ||
fbb4e983 | 520 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
521 | goto param_error_exit; |
522 | } | |
523 | ||
524 | /* | |
525 | * We always have PE address of form "00BB0001". "BB" | |
526 | * represents the bus number of PE's primary bus. | |
527 | */ | |
528 | option = rtas_ld(args, 3); | |
529 | switch (option) { | |
530 | case RTAS_GET_PE_ADDR: | |
531 | addr = rtas_ld(args, 0); | |
46c5874e | 532 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
533 | if (!pdev) { |
534 | goto param_error_exit; | |
535 | } | |
536 | ||
fd56e061 | 537 | rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); |
ee954280 GS |
538 | break; |
539 | case RTAS_GET_PE_MODE: | |
540 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
541 | break; | |
542 | default: | |
543 | goto param_error_exit; | |
544 | } | |
545 | ||
546 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
547 | return; | |
548 | ||
549 | param_error_exit: | |
550 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
551 | } | |
552 | ||
553 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
28e02042 | 554 | sPAPRMachineState *spapr, |
ee954280 GS |
555 | uint32_t token, uint32_t nargs, |
556 | target_ulong args, uint32_t nret, | |
557 | target_ulong rets) | |
558 | { | |
559 | sPAPRPHBState *sphb; | |
ee954280 GS |
560 | uint64_t buid; |
561 | int state, ret; | |
562 | ||
563 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
564 | goto param_error_exit; | |
565 | } | |
566 | ||
a14aa92b | 567 | buid = rtas_ldq(args, 1); |
46c5874e | 568 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
569 | if (!sphb) { |
570 | goto param_error_exit; | |
571 | } | |
572 | ||
fbb4e983 | 573 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
574 | goto param_error_exit; |
575 | } | |
576 | ||
fbb4e983 | 577 | ret = spapr_phb_vfio_eeh_get_state(sphb, &state); |
ee954280 GS |
578 | rtas_st(rets, 0, ret); |
579 | if (ret != RTAS_OUT_SUCCESS) { | |
580 | return; | |
581 | } | |
582 | ||
583 | rtas_st(rets, 1, state); | |
584 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
585 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
586 | if (nret >= 5) { | |
587 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
588 | } | |
589 | return; | |
590 | ||
591 | param_error_exit: | |
592 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
593 | } | |
594 | ||
595 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
28e02042 | 596 | sPAPRMachineState *spapr, |
ee954280 GS |
597 | uint32_t token, uint32_t nargs, |
598 | target_ulong args, uint32_t nret, | |
599 | target_ulong rets) | |
600 | { | |
601 | sPAPRPHBState *sphb; | |
ee954280 GS |
602 | uint32_t option; |
603 | uint64_t buid; | |
604 | int ret; | |
605 | ||
606 | if ((nargs != 4) || (nret != 1)) { | |
607 | goto param_error_exit; | |
608 | } | |
609 | ||
a14aa92b | 610 | buid = rtas_ldq(args, 1); |
ee954280 | 611 | option = rtas_ld(args, 3); |
46c5874e | 612 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
613 | if (!sphb) { |
614 | goto param_error_exit; | |
615 | } | |
616 | ||
fbb4e983 | 617 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
618 | goto param_error_exit; |
619 | } | |
620 | ||
fbb4e983 | 621 | ret = spapr_phb_vfio_eeh_reset(sphb, option); |
ee954280 GS |
622 | rtas_st(rets, 0, ret); |
623 | return; | |
624 | ||
625 | param_error_exit: | |
626 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
627 | } | |
628 | ||
629 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
28e02042 | 630 | sPAPRMachineState *spapr, |
ee954280 GS |
631 | uint32_t token, uint32_t nargs, |
632 | target_ulong args, uint32_t nret, | |
633 | target_ulong rets) | |
634 | { | |
635 | sPAPRPHBState *sphb; | |
ee954280 GS |
636 | uint64_t buid; |
637 | int ret; | |
638 | ||
639 | if ((nargs != 3) || (nret != 1)) { | |
640 | goto param_error_exit; | |
641 | } | |
642 | ||
a14aa92b | 643 | buid = rtas_ldq(args, 1); |
46c5874e | 644 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
645 | if (!sphb) { |
646 | goto param_error_exit; | |
647 | } | |
648 | ||
fbb4e983 | 649 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
650 | goto param_error_exit; |
651 | } | |
652 | ||
fbb4e983 | 653 | ret = spapr_phb_vfio_eeh_configure(sphb); |
ee954280 GS |
654 | rtas_st(rets, 0, ret); |
655 | return; | |
656 | ||
657 | param_error_exit: | |
658 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
659 | } | |
660 | ||
661 | /* To support it later */ | |
662 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
28e02042 | 663 | sPAPRMachineState *spapr, |
ee954280 GS |
664 | uint32_t token, uint32_t nargs, |
665 | target_ulong args, uint32_t nret, | |
666 | target_ulong rets) | |
667 | { | |
668 | sPAPRPHBState *sphb; | |
ee954280 GS |
669 | int option; |
670 | uint64_t buid; | |
671 | ||
672 | if ((nargs != 8) || (nret != 1)) { | |
673 | goto param_error_exit; | |
674 | } | |
675 | ||
a14aa92b | 676 | buid = rtas_ldq(args, 1); |
46c5874e | 677 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
678 | if (!sphb) { |
679 | goto param_error_exit; | |
680 | } | |
681 | ||
fbb4e983 | 682 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
683 | goto param_error_exit; |
684 | } | |
685 | ||
686 | option = rtas_ld(args, 7); | |
687 | switch (option) { | |
688 | case RTAS_SLOT_TEMP_ERR_LOG: | |
689 | case RTAS_SLOT_PERM_ERR_LOG: | |
690 | break; | |
691 | default: | |
692 | goto param_error_exit; | |
693 | } | |
694 | ||
695 | /* We don't have error log yet */ | |
696 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
697 | return; | |
698 | ||
699 | param_error_exit: | |
700 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
701 | } | |
702 | ||
7fb0bd34 DG |
703 | static int pci_spapr_swizzle(int slot, int pin) |
704 | { | |
705 | return (slot + pin) % PCI_NUM_PINS; | |
706 | } | |
707 | ||
3384f95c DG |
708 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
709 | { | |
710 | /* | |
711 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
712 | * which is less than number of IRQs on the specific bus (4). We |
713 | * use standard PCI swizzling, that is (slot number + pin number) | |
714 | * % 4. | |
3384f95c | 715 | */ |
7fb0bd34 | 716 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
717 | } |
718 | ||
719 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
720 | { | |
721 | /* | |
722 | * Here we use the number returned by pci_spapr_map_irq to find a | |
723 | * corresponding qemu_irq. | |
724 | */ | |
725 | sPAPRPHBState *phb = opaque; | |
726 | ||
caae58cb | 727 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 728 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
729 | } |
730 | ||
5cc7a967 AK |
731 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
732 | { | |
733 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); | |
734 | PCIINTxRoute route; | |
735 | ||
736 | route.mode = PCI_INTX_ENABLED; | |
737 | route.irq = sphb->lsi_table[pin].irq; | |
738 | ||
739 | return route; | |
740 | } | |
741 | ||
0ee2c058 AK |
742 | /* |
743 | * MSI/MSIX memory region implementation. | |
744 | * The handler handles both MSI and MSIX. | |
18f2330e | 745 | * The vector number is encoded in least bits in data. |
0ee2c058 | 746 | */ |
a8170e5e | 747 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
748 | uint64_t data, unsigned size) |
749 | { | |
28e02042 | 750 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
f1c2dc7c | 751 | uint32_t irq = data; |
0ee2c058 AK |
752 | |
753 | trace_spapr_pci_msi_write(addr, data, irq); | |
754 | ||
77183755 | 755 | qemu_irq_pulse(spapr_qirq(spapr, irq)); |
0ee2c058 AK |
756 | } |
757 | ||
758 | static const MemoryRegionOps spapr_msi_ops = { | |
759 | /* There is no .read as the read result is undefined by PCI spec */ | |
760 | .read = NULL, | |
761 | .write = spapr_msi_write, | |
762 | .endianness = DEVICE_LITTLE_ENDIAN | |
763 | }; | |
764 | ||
298a9710 DG |
765 | /* |
766 | * PHB PCI device | |
767 | */ | |
e00387d5 | 768 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
769 | { |
770 | sPAPRPHBState *phb = opaque; | |
771 | ||
e00387d5 | 772 | return &phb->iommu_as; |
edded454 DG |
773 | } |
774 | ||
16b0ea1d ND |
775 | static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) |
776 | { | |
777 | char *path = NULL, *buf = NULL, *host = NULL; | |
778 | ||
779 | /* Get the PCI VFIO host id */ | |
780 | host = object_property_get_str(OBJECT(pdev), "host", NULL); | |
781 | if (!host) { | |
782 | goto err_out; | |
783 | } | |
784 | ||
785 | /* Construct the path of the file that will give us the DT location */ | |
786 | path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); | |
787 | g_free(host); | |
8f687605 | 788 | if (!g_file_get_contents(path, &buf, NULL, NULL)) { |
16b0ea1d ND |
789 | goto err_out; |
790 | } | |
791 | g_free(path); | |
792 | ||
793 | /* Construct and read from host device tree the loc-code */ | |
794 | path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); | |
795 | g_free(buf); | |
8f687605 | 796 | if (!g_file_get_contents(path, &buf, NULL, NULL)) { |
16b0ea1d ND |
797 | goto err_out; |
798 | } | |
799 | return buf; | |
800 | ||
801 | err_out: | |
802 | g_free(path); | |
803 | return NULL; | |
804 | } | |
805 | ||
806 | static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) | |
807 | { | |
808 | char *buf; | |
809 | const char *devtype = "qemu"; | |
810 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
811 | ||
812 | if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
813 | buf = spapr_phb_vfio_get_loc_code(sphb, pdev); | |
814 | if (buf) { | |
815 | return buf; | |
816 | } | |
817 | devtype = "vfio"; | |
818 | } | |
819 | /* | |
820 | * For emulated devices and VFIO-failure case, make up | |
821 | * the loc-code. | |
822 | */ | |
823 | buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", | |
824 | devtype, pdev->name, sphb->index, busnr, | |
825 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
826 | return buf; | |
827 | } | |
828 | ||
7454c7af MR |
829 | /* Macros to operate with address in OF binding to PCI */ |
830 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
831 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
832 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
833 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
834 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
835 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
836 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
837 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
838 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
839 | ||
840 | /* for 'reg'/'assigned-addresses' OF properties */ | |
841 | #define RESOURCE_CELLS_SIZE 2 | |
842 | #define RESOURCE_CELLS_ADDRESS 3 | |
843 | ||
844 | typedef struct ResourceFields { | |
845 | uint32_t phys_hi; | |
846 | uint32_t phys_mid; | |
847 | uint32_t phys_lo; | |
848 | uint32_t size_hi; | |
849 | uint32_t size_lo; | |
850 | } QEMU_PACKED ResourceFields; | |
851 | ||
852 | typedef struct ResourceProps { | |
853 | ResourceFields reg[8]; | |
854 | ResourceFields assigned[7]; | |
855 | uint32_t reg_len; | |
856 | uint32_t assigned_len; | |
857 | } ResourceProps; | |
858 | ||
859 | /* fill in the 'reg'/'assigned-resources' OF properties for | |
860 | * a PCI device. 'reg' describes resource requirements for a | |
861 | * device's IO/MEM regions, 'assigned-addresses' describes the | |
862 | * actual resource assignments. | |
863 | * | |
864 | * the properties are arrays of ('phys-addr', 'size') pairs describing | |
865 | * the addressable regions of the PCI device, where 'phys-addr' is a | |
866 | * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to | |
867 | * (phys.hi, phys.mid, phys.lo), and 'size' is a | |
868 | * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). | |
869 | * | |
870 | * phys.hi = 0xYYXXXXZZ, where: | |
871 | * 0xYY = npt000ss | |
872 | * ||| | | |
72187935 ND |
873 | * ||| +-- space code |
874 | * ||| | | |
875 | * ||| + 00 if configuration space | |
876 | * ||| + 01 if IO region, | |
877 | * ||| + 10 if 32-bit MEM region | |
878 | * ||| + 11 if 64-bit MEM region | |
879 | * ||| | |
7454c7af MR |
880 | * ||+------ for non-relocatable IO: 1 if aliased |
881 | * || for relocatable IO: 1 if below 64KB | |
882 | * || for MEM: 1 if below 1MB | |
883 | * |+------- 1 if region is prefetchable | |
884 | * +-------- 1 if region is non-relocatable | |
885 | * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function | |
886 | * bits respectively | |
887 | * 0xZZ = rrrrrrrr, the register number of the BAR corresponding | |
888 | * to the region | |
889 | * | |
890 | * phys.mid and phys.lo correspond respectively to the hi/lo portions | |
891 | * of the actual address of the region. | |
892 | * | |
893 | * how the phys-addr/size values are used differ slightly between | |
894 | * 'reg' and 'assigned-addresses' properties. namely, 'reg' has | |
895 | * an additional description for the config space region of the | |
896 | * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 | |
897 | * to describe the region as relocatable, with an address-mapping | |
898 | * that corresponds directly to the PHB's address space for the | |
899 | * resource. 'assigned-addresses' always has n=1 set with an absolute | |
900 | * address assigned for the resource. in general, 'assigned-addresses' | |
901 | * won't be populated, since addresses for PCI devices are generally | |
902 | * unmapped initially and left to the guest to assign. | |
903 | * | |
904 | * note also that addresses defined in these properties are, at least | |
905 | * for PAPR guests, relative to the PHBs IO/MEM windows, and | |
906 | * correspond directly to the addresses in the BARs. | |
907 | * | |
908 | * in accordance with PCI Bus Binding to Open Firmware, | |
909 | * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, | |
910 | * Appendix C. | |
911 | */ | |
912 | static void populate_resource_props(PCIDevice *d, ResourceProps *rp) | |
913 | { | |
914 | int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); | |
915 | uint32_t dev_id = (b_bbbbbbbb(bus_num) | | |
916 | b_ddddd(PCI_SLOT(d->devfn)) | | |
917 | b_fff(PCI_FUNC(d->devfn))); | |
918 | ResourceFields *reg, *assigned; | |
919 | int i, reg_idx = 0, assigned_idx = 0; | |
920 | ||
921 | /* config space region */ | |
922 | reg = &rp->reg[reg_idx++]; | |
923 | reg->phys_hi = cpu_to_be32(dev_id); | |
924 | reg->phys_mid = 0; | |
925 | reg->phys_lo = 0; | |
926 | reg->size_hi = 0; | |
927 | reg->size_lo = 0; | |
928 | ||
929 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
930 | if (!d->io_regions[i].size) { | |
931 | continue; | |
932 | } | |
933 | ||
934 | reg = &rp->reg[reg_idx++]; | |
935 | ||
936 | reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); | |
937 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
938 | reg->phys_hi |= cpu_to_be32(b_ss(1)); | |
72187935 ND |
939 | } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
940 | reg->phys_hi |= cpu_to_be32(b_ss(3)); | |
7454c7af MR |
941 | } else { |
942 | reg->phys_hi |= cpu_to_be32(b_ss(2)); | |
943 | } | |
944 | reg->phys_mid = 0; | |
945 | reg->phys_lo = 0; | |
946 | reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); | |
947 | reg->size_lo = cpu_to_be32(d->io_regions[i].size); | |
948 | ||
949 | if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { | |
950 | continue; | |
951 | } | |
952 | ||
953 | assigned = &rp->assigned[assigned_idx++]; | |
954 | assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); | |
955 | assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); | |
956 | assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); | |
957 | assigned->size_hi = reg->size_hi; | |
958 | assigned->size_lo = reg->size_lo; | |
959 | } | |
960 | ||
961 | rp->reg_len = reg_idx * sizeof(ResourceFields); | |
962 | rp->assigned_len = assigned_idx * sizeof(ResourceFields); | |
963 | } | |
964 | ||
2530a1a5 LV |
965 | typedef struct PCIClass PCIClass; |
966 | typedef struct PCISubClass PCISubClass; | |
967 | typedef struct PCIIFace PCIIFace; | |
968 | ||
969 | struct PCIIFace { | |
970 | int iface; | |
971 | const char *name; | |
972 | }; | |
973 | ||
974 | struct PCISubClass { | |
975 | int subclass; | |
976 | const char *name; | |
977 | const PCIIFace *iface; | |
978 | }; | |
979 | ||
980 | struct PCIClass { | |
981 | const char *name; | |
982 | const PCISubClass *subc; | |
983 | }; | |
984 | ||
985 | static const PCISubClass undef_subclass[] = { | |
986 | { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, | |
987 | { 0xFF, NULL, NULL }, | |
988 | }; | |
989 | ||
990 | static const PCISubClass mass_subclass[] = { | |
991 | { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, | |
992 | { PCI_CLASS_STORAGE_IDE, "ide", NULL }, | |
993 | { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, | |
994 | { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, | |
995 | { PCI_CLASS_STORAGE_RAID, "raid", NULL }, | |
996 | { PCI_CLASS_STORAGE_ATA, "ata", NULL }, | |
997 | { PCI_CLASS_STORAGE_SATA, "sata", NULL }, | |
998 | { PCI_CLASS_STORAGE_SAS, "sas", NULL }, | |
999 | { 0xFF, NULL, NULL }, | |
1000 | }; | |
1001 | ||
1002 | static const PCISubClass net_subclass[] = { | |
1003 | { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, | |
1004 | { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, | |
1005 | { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, | |
1006 | { PCI_CLASS_NETWORK_ATM, "atm", NULL }, | |
1007 | { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, | |
1008 | { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, | |
1009 | { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, | |
1010 | { 0xFF, NULL, NULL }, | |
1011 | }; | |
1012 | ||
1013 | static const PCISubClass displ_subclass[] = { | |
1014 | { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, | |
1015 | { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, | |
1016 | { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, | |
1017 | { 0xFF, NULL, NULL }, | |
1018 | }; | |
1019 | ||
1020 | static const PCISubClass media_subclass[] = { | |
1021 | { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, | |
1022 | { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, | |
1023 | { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, | |
1024 | { 0xFF, NULL, NULL }, | |
1025 | }; | |
1026 | ||
1027 | static const PCISubClass mem_subclass[] = { | |
1028 | { PCI_CLASS_MEMORY_RAM, "memory", NULL }, | |
1029 | { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, | |
1030 | { 0xFF, NULL, NULL }, | |
1031 | }; | |
1032 | ||
1033 | static const PCISubClass bridg_subclass[] = { | |
1034 | { PCI_CLASS_BRIDGE_HOST, "host", NULL }, | |
1035 | { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, | |
1036 | { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, | |
1037 | { PCI_CLASS_BRIDGE_MC, "mca", NULL }, | |
1038 | { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, | |
1039 | { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, | |
1040 | { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, | |
1041 | { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, | |
1042 | { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, | |
1043 | { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, | |
1044 | { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, | |
1045 | { 0xFF, NULL, NULL }, | |
1046 | }; | |
1047 | ||
1048 | static const PCISubClass comm_subclass[] = { | |
1049 | { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, | |
1050 | { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, | |
1051 | { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, | |
1052 | { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, | |
1053 | { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, | |
1054 | { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, | |
1055 | { 0xFF, NULL, NULL, }, | |
1056 | }; | |
1057 | ||
1058 | static const PCIIFace pic_iface[] = { | |
1059 | { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, | |
1060 | { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, | |
1061 | { 0xFF, NULL }, | |
1062 | }; | |
1063 | ||
1064 | static const PCISubClass sys_subclass[] = { | |
1065 | { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, | |
1066 | { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, | |
1067 | { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, | |
1068 | { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, | |
1069 | { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, | |
1070 | { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, | |
1071 | { 0xFF, NULL, NULL }, | |
1072 | }; | |
1073 | ||
1074 | static const PCISubClass inp_subclass[] = { | |
1075 | { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, | |
1076 | { PCI_CLASS_INPUT_PEN, "pen", NULL }, | |
1077 | { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, | |
1078 | { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, | |
1079 | { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, | |
1080 | { 0xFF, NULL, NULL }, | |
1081 | }; | |
1082 | ||
1083 | static const PCISubClass dock_subclass[] = { | |
1084 | { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, | |
1085 | { 0xFF, NULL, NULL }, | |
1086 | }; | |
1087 | ||
1088 | static const PCISubClass cpu_subclass[] = { | |
1089 | { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, | |
1090 | { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, | |
1091 | { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, | |
1092 | { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, | |
1093 | { 0xFF, NULL, NULL }, | |
1094 | }; | |
1095 | ||
1096 | static const PCIIFace usb_iface[] = { | |
1097 | { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, | |
1098 | { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, | |
1099 | { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, | |
1100 | { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, | |
1101 | { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, | |
1102 | { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, | |
1103 | { 0xFF, NULL }, | |
1104 | }; | |
1105 | ||
1106 | static const PCISubClass ser_subclass[] = { | |
1107 | { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, | |
1108 | { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, | |
1109 | { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, | |
1110 | { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, | |
1111 | { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, | |
1112 | { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, | |
1113 | { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, | |
1114 | { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, | |
1115 | { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, | |
1116 | { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, | |
1117 | { 0xFF, NULL, NULL }, | |
1118 | }; | |
1119 | ||
1120 | static const PCISubClass wrl_subclass[] = { | |
1121 | { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, | |
1122 | { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, | |
1123 | { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, | |
1124 | { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, | |
1125 | { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, | |
1126 | { 0xFF, NULL, NULL }, | |
1127 | }; | |
1128 | ||
1129 | static const PCISubClass sat_subclass[] = { | |
1130 | { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, | |
1131 | { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, | |
1132 | { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, | |
1133 | { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, | |
1134 | { 0xFF, NULL, NULL }, | |
1135 | }; | |
1136 | ||
1137 | static const PCISubClass crypt_subclass[] = { | |
1138 | { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, | |
1139 | { PCI_CLASS_CRYPT_ENTERTAINMENT, | |
1140 | "entertainment-encryption", NULL }, | |
1141 | { 0xFF, NULL, NULL }, | |
1142 | }; | |
1143 | ||
1144 | static const PCISubClass spc_subclass[] = { | |
1145 | { PCI_CLASS_SP_DPIO, "dpio", NULL }, | |
1146 | { PCI_CLASS_SP_PERF, "counter", NULL }, | |
1147 | { PCI_CLASS_SP_SYNCH, "measurement", NULL }, | |
1148 | { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, | |
1149 | { 0xFF, NULL, NULL }, | |
1150 | }; | |
1151 | ||
1152 | static const PCIClass pci_classes[] = { | |
1153 | { "legacy-device", undef_subclass }, | |
1154 | { "mass-storage", mass_subclass }, | |
1155 | { "network", net_subclass }, | |
1156 | { "display", displ_subclass, }, | |
1157 | { "multimedia-device", media_subclass }, | |
1158 | { "memory-controller", mem_subclass }, | |
1159 | { "unknown-bridge", bridg_subclass }, | |
1160 | { "communication-controller", comm_subclass}, | |
1161 | { "system-peripheral", sys_subclass }, | |
1162 | { "input-controller", inp_subclass }, | |
1163 | { "docking-station", dock_subclass }, | |
1164 | { "cpu", cpu_subclass }, | |
1165 | { "serial-bus", ser_subclass }, | |
1166 | { "wireless-controller", wrl_subclass }, | |
1167 | { "intelligent-io", NULL }, | |
1168 | { "satellite-device", sat_subclass }, | |
1169 | { "encryption", crypt_subclass }, | |
1170 | { "data-processing-controller", spc_subclass }, | |
1171 | }; | |
1172 | ||
1173 | static const char *pci_find_device_name(uint8_t class, uint8_t subclass, | |
1174 | uint8_t iface) | |
1175 | { | |
1176 | const PCIClass *pclass; | |
1177 | const PCISubClass *psubclass; | |
1178 | const PCIIFace *piface; | |
1179 | const char *name; | |
1180 | ||
1181 | if (class >= ARRAY_SIZE(pci_classes)) { | |
1182 | return "pci"; | |
1183 | } | |
1184 | ||
1185 | pclass = pci_classes + class; | |
1186 | name = pclass->name; | |
1187 | ||
1188 | if (pclass->subc == NULL) { | |
1189 | return name; | |
1190 | } | |
1191 | ||
1192 | psubclass = pclass->subc; | |
1193 | while ((psubclass->subclass & 0xff) != 0xff) { | |
1194 | if ((psubclass->subclass & 0xff) == subclass) { | |
1195 | name = psubclass->name; | |
1196 | break; | |
1197 | } | |
1198 | psubclass++; | |
1199 | } | |
1200 | ||
1201 | piface = psubclass->iface; | |
1202 | if (piface == NULL) { | |
1203 | return name; | |
1204 | } | |
1205 | while ((piface->iface & 0xff) != 0xff) { | |
1206 | if ((piface->iface & 0xff) == iface) { | |
1207 | name = piface->name; | |
1208 | break; | |
1209 | } | |
1210 | piface++; | |
1211 | } | |
1212 | ||
1213 | return name; | |
1214 | } | |
1215 | ||
549ce59e | 1216 | static gchar *pci_get_node_name(PCIDevice *dev) |
2530a1a5 LV |
1217 | { |
1218 | int slot = PCI_SLOT(dev->devfn); | |
1219 | int func = PCI_FUNC(dev->devfn); | |
1220 | uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); | |
1221 | const char *name; | |
1222 | ||
1223 | name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, | |
1224 | ccode & 0xff); | |
1225 | ||
1226 | if (func != 0) { | |
549ce59e | 1227 | return g_strdup_printf("%s@%x,%x", name, slot, func); |
2530a1a5 | 1228 | } else { |
549ce59e | 1229 | return g_strdup_printf("%s@%x", name, slot); |
2530a1a5 LV |
1230 | } |
1231 | } | |
1232 | ||
e634b89c ND |
1233 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
1234 | PCIDevice *pdev); | |
1235 | ||
9ba25536 | 1236 | static void spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, |
16b0ea1d | 1237 | sPAPRPHBState *sphb) |
7454c7af MR |
1238 | { |
1239 | ResourceProps rp; | |
1240 | bool is_bridge = false; | |
9ba25536 | 1241 | int pci_status; |
16b0ea1d | 1242 | char *buf = NULL; |
e634b89c | 1243 | uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); |
2530a1a5 | 1244 | uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); |
a8ad731a | 1245 | uint32_t max_msi, max_msix; |
7454c7af MR |
1246 | |
1247 | if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == | |
1248 | PCI_HEADER_TYPE_BRIDGE) { | |
1249 | is_bridge = true; | |
1250 | } | |
1251 | ||
1252 | /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ | |
1253 | _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", | |
1254 | pci_default_read_config(dev, PCI_VENDOR_ID, 2))); | |
1255 | _FDT(fdt_setprop_cell(fdt, offset, "device-id", | |
1256 | pci_default_read_config(dev, PCI_DEVICE_ID, 2))); | |
1257 | _FDT(fdt_setprop_cell(fdt, offset, "revision-id", | |
1258 | pci_default_read_config(dev, PCI_REVISION_ID, 1))); | |
2530a1a5 | 1259 | _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); |
7454c7af MR |
1260 | if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { |
1261 | _FDT(fdt_setprop_cell(fdt, offset, "interrupts", | |
1262 | pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); | |
1263 | } | |
1264 | ||
1265 | if (!is_bridge) { | |
1266 | _FDT(fdt_setprop_cell(fdt, offset, "min-grant", | |
1267 | pci_default_read_config(dev, PCI_MIN_GNT, 1))); | |
1268 | _FDT(fdt_setprop_cell(fdt, offset, "max-latency", | |
1269 | pci_default_read_config(dev, PCI_MAX_LAT, 1))); | |
1270 | } | |
1271 | ||
1272 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { | |
1273 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", | |
1274 | pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); | |
1275 | } | |
1276 | ||
1277 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { | |
1278 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", | |
1279 | pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); | |
1280 | } | |
1281 | ||
1282 | _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", | |
1283 | pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); | |
1284 | ||
1285 | /* the following fdt cells are masked off the pci status register */ | |
1286 | pci_status = pci_default_read_config(dev, PCI_STATUS, 2); | |
1287 | _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", | |
1288 | PCI_STATUS_DEVSEL_MASK & pci_status)); | |
1289 | ||
1290 | if (pci_status & PCI_STATUS_FAST_BACK) { | |
1291 | _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); | |
1292 | } | |
1293 | if (pci_status & PCI_STATUS_66MHZ) { | |
1294 | _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); | |
1295 | } | |
1296 | if (pci_status & PCI_STATUS_UDF) { | |
1297 | _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); | |
1298 | } | |
1299 | ||
2530a1a5 LV |
1300 | _FDT(fdt_setprop_string(fdt, offset, "name", |
1301 | pci_find_device_name((ccode >> 16) & 0xff, | |
1302 | (ccode >> 8) & 0xff, | |
1303 | ccode & 0xff))); | |
16b0ea1d | 1304 | |
d049bde6 | 1305 | buf = spapr_phb_get_loc_code(sphb, dev); |
9ba25536 | 1306 | _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", buf)); |
16b0ea1d | 1307 | g_free(buf); |
16b0ea1d | 1308 | |
e634b89c ND |
1309 | if (drc_index) { |
1310 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); | |
1311 | } | |
7454c7af MR |
1312 | |
1313 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", | |
1314 | RESOURCE_CELLS_ADDRESS)); | |
1315 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", | |
1316 | RESOURCE_CELLS_SIZE)); | |
a8ad731a | 1317 | |
9cbe305b GK |
1318 | if (msi_present(dev)) { |
1319 | max_msi = msi_nr_vectors_allocated(dev); | |
1320 | if (max_msi) { | |
1321 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); | |
1322 | } | |
a8ad731a | 1323 | } |
9cbe305b GK |
1324 | if (msix_present(dev)) { |
1325 | max_msix = dev->msix_entries_nr; | |
1326 | if (max_msix) { | |
1327 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); | |
1328 | } | |
a8ad731a | 1329 | } |
7454c7af MR |
1330 | |
1331 | populate_resource_props(dev, &rp); | |
1332 | _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); | |
1333 | _FDT(fdt_setprop(fdt, offset, "assigned-addresses", | |
1334 | (uint8_t *)rp.assigned, rp.assigned_len)); | |
1335 | ||
82516263 | 1336 | if (sphb->pcie_ecs && pci_is_express(dev)) { |
bb998645 DG |
1337 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); |
1338 | } | |
7454c7af MR |
1339 | } |
1340 | ||
1341 | /* create OF node for pci device and required OF DT properties */ | |
1d2d9742 | 1342 | static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, |
1d2d9742 | 1343 | void *fdt, int node_offset) |
7454c7af | 1344 | { |
9ba25536 | 1345 | int offset; |
549ce59e | 1346 | gchar *nodename; |
7454c7af | 1347 | |
549ce59e | 1348 | nodename = pci_get_node_name(dev); |
9ba25536 | 1349 | _FDT(offset = fdt_add_subnode(fdt, node_offset, nodename)); |
549ce59e GK |
1350 | g_free(nodename); |
1351 | ||
9ba25536 | 1352 | spapr_populate_pci_child_dt(dev, fdt, offset, phb); |
e634b89c | 1353 | |
1d2d9742 | 1354 | return offset; |
7454c7af MR |
1355 | } |
1356 | ||
31834723 DHB |
1357 | /* Callback to be called during DRC release. */ |
1358 | void spapr_phb_remove_pci_device_cb(DeviceState *dev) | |
7454c7af MR |
1359 | { |
1360 | /* some version guests do not wait for completion of a device | |
1361 | * cleanup (generally done asynchronously by the kernel) before | |
1362 | * signaling to QEMU that the device is safe, but instead sleep | |
1363 | * for some 'safe' period of time. unfortunately on a busy host | |
1364 | * this sleep isn't guaranteed to be long enough, resulting in | |
1365 | * bad things like IRQ lines being left asserted during final | |
1366 | * device removal. to deal with this we call reset just prior | |
1367 | * to finalizing the device, which will put the device back into | |
1368 | * an 'idle' state, as the device cleanup code expects. | |
1369 | */ | |
1370 | pci_device_reset(PCI_DEVICE(dev)); | |
1371 | object_unparent(OBJECT(dev)); | |
1372 | } | |
1373 | ||
788d2599 MR |
1374 | static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb, |
1375 | uint32_t busnr, | |
1376 | int32_t devfn) | |
7454c7af | 1377 | { |
fbf55397 DG |
1378 | return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, |
1379 | (phb->index << 16) | (busnr << 8) | devfn); | |
788d2599 MR |
1380 | } |
1381 | ||
1382 | static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, | |
1383 | PCIDevice *pdev) | |
1384 | { | |
1385 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
1386 | return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn); | |
7454c7af MR |
1387 | } |
1388 | ||
1d2d9742 ND |
1389 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
1390 | PCIDevice *pdev) | |
1391 | { | |
1392 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1d2d9742 ND |
1393 | |
1394 | if (!drc) { | |
1395 | return 0; | |
1396 | } | |
1397 | ||
0b55aa91 | 1398 | return spapr_drc_index(drc); |
1d2d9742 ND |
1399 | } |
1400 | ||
3340e5c4 DG |
1401 | static void spapr_pci_plug(HotplugHandler *plug_handler, |
1402 | DeviceState *plugged_dev, Error **errp) | |
7454c7af MR |
1403 | { |
1404 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1405 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1406 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1407 | Error *local_err = NULL; | |
788d2599 MR |
1408 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); |
1409 | uint32_t slotnr = PCI_SLOT(pdev->devfn); | |
6304fd27 DG |
1410 | void *fdt = NULL; |
1411 | int fdt_start_offset, fdt_size; | |
7454c7af MR |
1412 | |
1413 | /* if DR is disabled we don't need to do anything in the case of | |
1414 | * hotplug or coldplug callbacks | |
1415 | */ | |
1416 | if (!phb->dr_enabled) { | |
1417 | /* if this is a hotplug operation initiated by the user | |
1418 | * we need to let them know it's not enabled | |
1419 | */ | |
1420 | if (plugged_dev->hotplugged) { | |
6304fd27 | 1421 | error_setg(&local_err, QERR_BUS_NO_HOTPLUG, |
c6bd8c70 | 1422 | object_get_typename(OBJECT(phb))); |
7454c7af | 1423 | } |
6304fd27 | 1424 | goto out; |
7454c7af MR |
1425 | } |
1426 | ||
1427 | g_assert(drc); | |
1428 | ||
788d2599 MR |
1429 | /* Following the QEMU convention used for PCIe multifunction |
1430 | * hotplug, we do not allow functions to be hotplugged to a | |
1431 | * slot that already has function 0 present | |
1432 | */ | |
1433 | if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && | |
1434 | PCI_FUNC(pdev->devfn) != 0) { | |
6304fd27 | 1435 | error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s," |
788d2599 MR |
1436 | " additional functions can no longer be exposed to guest.", |
1437 | slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); | |
6304fd27 DG |
1438 | goto out; |
1439 | } | |
1440 | ||
1441 | fdt = create_device_tree(&fdt_size); | |
1442 | fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); | |
788d2599 | 1443 | |
5c1da812 | 1444 | spapr_drc_attach(drc, DEVICE(pdev), fdt, fdt_start_offset, &local_err); |
7454c7af | 1445 | if (local_err) { |
6304fd27 | 1446 | goto out; |
7454c7af | 1447 | } |
788d2599 MR |
1448 | |
1449 | /* If this is function 0, signal hotplug for all the device functions. | |
1450 | * Otherwise defer sending the hotplug event. | |
1451 | */ | |
94fd9cba LV |
1452 | if (!spapr_drc_hotplugged(plugged_dev)) { |
1453 | spapr_drc_reset(drc); | |
1454 | } else if (PCI_FUNC(pdev->devfn) == 0) { | |
788d2599 MR |
1455 | int i; |
1456 | ||
1457 | for (i = 0; i < 8; i++) { | |
1458 | sPAPRDRConnector *func_drc; | |
1459 | sPAPRDRConnectorClass *func_drck; | |
1460 | sPAPRDREntitySense state; | |
1461 | ||
1462 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1463 | PCI_DEVFN(slotnr, i)); | |
1464 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
f224d35b | 1465 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 MR |
1466 | |
1467 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { | |
1468 | spapr_hotplug_req_add_by_index(func_drc); | |
1469 | } | |
1470 | } | |
c5bc152b | 1471 | } |
6304fd27 DG |
1472 | |
1473 | out: | |
1474 | if (local_err) { | |
1475 | error_propagate(errp, local_err); | |
1476 | g_free(fdt); | |
1477 | } | |
7454c7af MR |
1478 | } |
1479 | ||
3340e5c4 DG |
1480 | static void spapr_pci_unplug_request(HotplugHandler *plug_handler, |
1481 | DeviceState *plugged_dev, Error **errp) | |
7454c7af MR |
1482 | { |
1483 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1484 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
7454c7af | 1485 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); |
7454c7af MR |
1486 | |
1487 | if (!phb->dr_enabled) { | |
c6bd8c70 MA |
1488 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1489 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1490 | return; |
1491 | } | |
1492 | ||
1493 | g_assert(drc); | |
3340e5c4 | 1494 | g_assert(drc->dev == plugged_dev); |
7454c7af | 1495 | |
f1c52354 | 1496 | if (!spapr_drc_unplug_requested(drc)) { |
788d2599 MR |
1497 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); |
1498 | uint32_t slotnr = PCI_SLOT(pdev->devfn); | |
1499 | sPAPRDRConnector *func_drc; | |
1500 | sPAPRDRConnectorClass *func_drck; | |
1501 | sPAPRDREntitySense state; | |
1502 | int i; | |
1503 | ||
1504 | /* ensure any other present functions are pending unplug */ | |
1505 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1506 | for (i = 1; i < 8; i++) { | |
1507 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1508 | PCI_DEVFN(slotnr, i)); | |
1509 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
f224d35b | 1510 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 | 1511 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT |
f1c52354 | 1512 | && !spapr_drc_unplug_requested(func_drc)) { |
788d2599 MR |
1513 | error_setg(errp, |
1514 | "PCI: slot %d, function %d still present. " | |
1515 | "Must unplug all non-0 functions first.", | |
1516 | slotnr, i); | |
1517 | return; | |
1518 | } | |
1519 | } | |
1520 | } | |
1521 | ||
a8dc47fd | 1522 | spapr_drc_detach(drc); |
788d2599 MR |
1523 | |
1524 | /* if this isn't func 0, defer unplug event. otherwise signal removal | |
1525 | * for all present functions | |
1526 | */ | |
1527 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1528 | for (i = 7; i >= 0; i--) { | |
1529 | func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus), | |
1530 | PCI_DEVFN(slotnr, i)); | |
1531 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); | |
f224d35b | 1532 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 MR |
1533 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { |
1534 | spapr_hotplug_req_remove_by_index(func_drc); | |
1535 | } | |
1536 | } | |
1537 | } | |
7454c7af MR |
1538 | } |
1539 | } | |
1540 | ||
c6ba42f6 | 1541 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 1542 | { |
f7d6bfcd GK |
1543 | /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user |
1544 | * tries to add a sPAPR PHB to a non-pseries machine. | |
1545 | */ | |
1546 | sPAPRMachineState *spapr = | |
1547 | (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), | |
1548 | TYPE_SPAPR_MACHINE); | |
c6ba42f6 | 1549 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
8c9f64df | 1550 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 1551 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
298a9710 DG |
1552 | char *namebuf; |
1553 | int i; | |
3384f95c | 1554 | PCIBus *bus; |
8c46f7ec | 1555 | uint64_t msi_window_size = 4096; |
a36304fd | 1556 | sPAPRTCETable *tcet; |
ae4de14c AK |
1557 | const unsigned windows_supported = |
1558 | sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; | |
3384f95c | 1559 | |
f7d6bfcd GK |
1560 | if (!spapr) { |
1561 | error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); | |
1562 | return; | |
1563 | } | |
1564 | ||
421b1b27 | 1565 | if (sphb->index != (uint32_t)-1) { |
6737d9ad DG |
1566 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
1567 | Error *local_err = NULL; | |
caae58cb | 1568 | |
daa23699 DG |
1569 | smc->phb_placement(spapr, sphb->index, |
1570 | &sphb->buid, &sphb->io_win_addr, | |
1571 | &sphb->mem_win_addr, &sphb->mem64_win_addr, | |
6737d9ad DG |
1572 | windows_supported, sphb->dma_liobn, &local_err); |
1573 | if (local_err) { | |
1574 | error_propagate(errp, local_err); | |
3e4ac968 DG |
1575 | return; |
1576 | } | |
30b3bc5a GK |
1577 | } else { |
1578 | error_setg(errp, "\"index\" for PAPR PHB is mandatory"); | |
c6ba42f6 | 1579 | return; |
caae58cb DG |
1580 | } |
1581 | ||
daa23699 | 1582 | if (sphb->mem64_win_size != 0) { |
daa23699 DG |
1583 | if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { |
1584 | error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx | |
1585 | " (max 2 GiB)", sphb->mem_win_size); | |
1586 | return; | |
1587 | } | |
1588 | ||
30b3bc5a GK |
1589 | /* 64-bit window defaults to identity mapping */ |
1590 | sphb->mem64_win_pciaddr = sphb->mem64_win_addr; | |
daa23699 DG |
1591 | } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { |
1592 | /* | |
1593 | * For compatibility with old configuration, if no 64-bit MMIO | |
1594 | * window is specified, but the ordinary (32-bit) memory | |
1595 | * window is specified as > 2GiB, we treat it as a 2GiB 32-bit | |
1596 | * window, with a 64-bit MMIO window following on immediately | |
1597 | * afterwards | |
1598 | */ | |
1599 | sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; | |
1600 | sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; | |
1601 | sphb->mem64_win_pciaddr = | |
1602 | SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; | |
1603 | sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; | |
1604 | } | |
1605 | ||
46c5874e | 1606 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
c6ba42f6 AK |
1607 | error_setg(errp, "PCI host bridges must have unique BUIDs"); |
1608 | return; | |
caae58cb DG |
1609 | } |
1610 | ||
4bcfa56c MR |
1611 | if (sphb->numa_node != -1 && |
1612 | (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) { | |
1613 | error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); | |
1614 | return; | |
1615 | } | |
1616 | ||
8c9f64df | 1617 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 1618 | |
298a9710 | 1619 | /* Initialize memory regions */ |
1d36da76 | 1620 | namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); |
92b8e39c | 1621 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
1d36da76 | 1622 | g_free(namebuf); |
3384f95c | 1623 | |
1d36da76 | 1624 | namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); |
daa23699 | 1625 | memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), |
40c5dce9 | 1626 | namebuf, &sphb->memspace, |
8c9f64df | 1627 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
1d36da76 | 1628 | g_free(namebuf); |
8c9f64df | 1629 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, |
daa23699 DG |
1630 | &sphb->mem32window); |
1631 | ||
30b3bc5a | 1632 | if (sphb->mem64_win_size != 0) { |
96dbc9af GK |
1633 | namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); |
1634 | memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), | |
1635 | namebuf, &sphb->memspace, | |
1636 | sphb->mem64_win_pciaddr, sphb->mem64_win_size); | |
1637 | g_free(namebuf); | |
1638 | ||
30b3bc5a GK |
1639 | memory_region_add_subregion(get_system_memory(), |
1640 | sphb->mem64_win_addr, | |
1641 | &sphb->mem64window); | |
96dbc9af | 1642 | } |
3384f95c | 1643 | |
fabe9ee1 | 1644 | /* Initialize IO regions */ |
1d36da76 | 1645 | namebuf = g_strdup_printf("%s.io", sphb->dtbusname); |
40c5dce9 PB |
1646 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
1647 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
1d36da76 | 1648 | g_free(namebuf); |
3384f95c | 1649 | |
1d36da76 | 1650 | namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); |
66aab867 | 1651 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 1652 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
1d36da76 | 1653 | g_free(namebuf); |
8c9f64df | 1654 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 1655 | &sphb->iowindow); |
1b8601b0 | 1656 | |
1115ff6d DG |
1657 | bus = pci_register_root_bus(dev, NULL, |
1658 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, | |
1659 | &sphb->memspace, &sphb->iospace, | |
1660 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); | |
8c9f64df | 1661 | phb->bus = bus; |
7454c7af | 1662 | qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); |
298a9710 | 1663 | |
cca7fad5 AK |
1664 | /* |
1665 | * Initialize PHB address space. | |
1666 | * By default there will be at least one subregion for default | |
1667 | * 32bit DMA window. | |
1668 | * Later the guest might want to create another DMA window | |
1669 | * which will become another memory subregion. | |
1670 | */ | |
1d36da76 | 1671 | namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); |
cca7fad5 AK |
1672 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), |
1673 | namebuf, UINT64_MAX); | |
1d36da76 | 1674 | g_free(namebuf); |
cca7fad5 AK |
1675 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, |
1676 | sphb->dtbusname); | |
1677 | ||
8c46f7ec GK |
1678 | /* |
1679 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
1680 | * we need to allocate some memory to catch those writes coming | |
1681 | * from msi_notify()/msix_notify(). | |
1682 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
1683 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
1684 | * be used. | |
1685 | * | |
1686 | * For KVM we want to ensure that this memory is a full page so that | |
1687 | * our memory slot is of page size granularity. | |
1688 | */ | |
1689 | #ifdef CONFIG_KVM | |
1690 | if (kvm_enabled()) { | |
1691 | msi_window_size = getpagesize(); | |
1692 | } | |
1693 | #endif | |
1694 | ||
dba95ebb | 1695 | memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, |
8c46f7ec GK |
1696 | "msi", msi_window_size); |
1697 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
1698 | &sphb->msiwindow); | |
1699 | ||
e00387d5 | 1700 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 1701 | |
5cc7a967 AK |
1702 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
1703 | ||
8c9f64df | 1704 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
1705 | |
1706 | /* Initialize the LSI table */ | |
7fb0bd34 | 1707 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 1708 | uint32_t irq; |
a005b3ef | 1709 | Error *local_err = NULL; |
298a9710 | 1710 | |
4fe75a8c CLG |
1711 | irq = spapr_irq_findone(spapr, &local_err); |
1712 | if (local_err) { | |
1713 | error_propagate(errp, local_err); | |
1714 | error_prepend(errp, "can't allocate LSIs: "); | |
1715 | return; | |
1716 | } | |
1717 | ||
1718 | spapr_irq_claim(spapr, irq, true, &local_err); | |
a005b3ef GK |
1719 | if (local_err) { |
1720 | error_propagate(errp, local_err); | |
1721 | error_prepend(errp, "can't allocate LSIs: "); | |
c6ba42f6 | 1722 | return; |
298a9710 DG |
1723 | } |
1724 | ||
8c9f64df | 1725 | sphb->lsi_table[i].irq = irq; |
298a9710 | 1726 | } |
da6ccee4 | 1727 | |
62083979 MR |
1728 | /* allocate connectors for child PCI devices */ |
1729 | if (sphb->dr_enabled) { | |
1730 | for (i = 0; i < PCI_SLOT_MAX * 8; i++) { | |
2d335818 | 1731 | spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI, |
62083979 MR |
1732 | (sphb->index << 16) | i); |
1733 | } | |
1734 | } | |
1735 | ||
ae4de14c AK |
1736 | /* DMA setup */ |
1737 | for (i = 0; i < windows_supported; ++i) { | |
1738 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); | |
1739 | if (!tcet) { | |
1740 | error_setg(errp, "Creating window#%d failed for %s", | |
1741 | i, sphb->dtbusname); | |
1742 | return; | |
1743 | } | |
5c3d70e9 GK |
1744 | memory_region_add_subregion(&sphb->iommu_root, 0, |
1745 | spapr_tce_get_iommu(tcet)); | |
da6ccee4 | 1746 | } |
cca7fad5 | 1747 | |
a36304fd | 1748 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); |
298a9710 DG |
1749 | } |
1750 | ||
e28c16f6 | 1751 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 1752 | { |
e28c16f6 AK |
1753 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
1754 | ||
1755 | if (dev) { | |
1756 | device_reset(dev); | |
1757 | } | |
eddeed26 | 1758 | |
e28c16f6 AK |
1759 | return 0; |
1760 | } | |
1761 | ||
b3162f22 | 1762 | void spapr_phb_dma_reset(sPAPRPHBState *sphb) |
e28c16f6 | 1763 | { |
ae4de14c AK |
1764 | int i; |
1765 | sPAPRTCETable *tcet; | |
1766 | ||
1767 | for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { | |
1768 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); | |
acf1b6dd | 1769 | |
ae4de14c AK |
1770 | if (tcet && tcet->nb_table) { |
1771 | spapr_tce_table_disable(tcet); | |
1772 | } | |
acf1b6dd AK |
1773 | } |
1774 | ||
1775 | /* Register default 32bit DMA window */ | |
ae4de14c | 1776 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); |
acf1b6dd AK |
1777 | spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, |
1778 | sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); | |
b3162f22 AK |
1779 | } |
1780 | ||
1781 | static void spapr_phb_reset(DeviceState *qdev) | |
1782 | { | |
1783 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); | |
1784 | ||
1785 | spapr_phb_dma_reset(sphb); | |
acf1b6dd | 1786 | |
eddeed26 | 1787 | /* Reset the IOMMU state */ |
e28c16f6 | 1788 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
fbb4e983 DG |
1789 | |
1790 | if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { | |
1791 | spapr_phb_vfio_reset(qdev); | |
1792 | } | |
eddeed26 DG |
1793 | } |
1794 | ||
298a9710 | 1795 | static Property spapr_phb_properties[] = { |
3e4ac968 | 1796 | DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), |
c7bcc85d | 1797 | DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, |
357d1e3b | 1798 | SPAPR_PCI_MEM32_WIN_SIZE), |
357d1e3b DG |
1799 | DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size, |
1800 | SPAPR_PCI_MEM64_WIN_SIZE), | |
c7bcc85d PB |
1801 | DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, |
1802 | SPAPR_PCI_IO_WIN_SIZE), | |
7619c7b0 MR |
1803 | DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, |
1804 | true), | |
f93caaac DG |
1805 | /* Default DMA window is 0..1GB */ |
1806 | DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0), | |
1807 | DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000), | |
ae4de14c AK |
1808 | DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr, |
1809 | 0x800000000000000ULL), | |
1810 | DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true), | |
1811 | DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask, | |
1812 | (1ULL << 12) | (1ULL << 16)), | |
4814401f | 1813 | DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1), |
5c4537bd DG |
1814 | DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState, |
1815 | pre_2_8_migration, false), | |
82516263 DG |
1816 | DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState, |
1817 | pcie_ecs, true), | |
298a9710 DG |
1818 | DEFINE_PROP_END_OF_LIST(), |
1819 | }; | |
1820 | ||
1112cf94 DG |
1821 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
1822 | .name = "spapr_pci/lsi", | |
1823 | .version_id = 1, | |
1824 | .minimum_version_id = 1, | |
3aff6c2f | 1825 | .fields = (VMStateField[]) { |
d2164ad3 | 1826 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL), |
1112cf94 DG |
1827 | |
1828 | VMSTATE_END_OF_LIST() | |
1829 | }, | |
1830 | }; | |
1831 | ||
1832 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 1833 | .name = "spapr_pci/msi", |
1112cf94 DG |
1834 | .version_id = 1, |
1835 | .minimum_version_id = 1, | |
9a321e92 AK |
1836 | .fields = (VMStateField []) { |
1837 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
1838 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
1839 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
1840 | VMSTATE_END_OF_LIST() |
1841 | }, | |
1842 | }; | |
1843 | ||
44b1ff31 | 1844 | static int spapr_pci_pre_save(void *opaque) |
9a321e92 AK |
1845 | { |
1846 | sPAPRPHBState *sphb = opaque; | |
708414f0 MA |
1847 | GHashTableIter iter; |
1848 | gpointer key, value; | |
1849 | int i; | |
9a321e92 | 1850 | |
5c4537bd DG |
1851 | if (sphb->pre_2_8_migration) { |
1852 | sphb->mig_liobn = sphb->dma_liobn[0]; | |
1853 | sphb->mig_mem_win_addr = sphb->mem_win_addr; | |
1854 | sphb->mig_mem_win_size = sphb->mem_win_size; | |
1855 | sphb->mig_io_win_addr = sphb->io_win_addr; | |
1856 | sphb->mig_io_win_size = sphb->io_win_size; | |
1857 | ||
1858 | if ((sphb->mem64_win_size != 0) | |
1859 | && (sphb->mem64_win_addr | |
1860 | == (sphb->mem_win_addr + sphb->mem_win_size))) { | |
1861 | sphb->mig_mem_win_size += sphb->mem64_win_size; | |
1862 | } | |
1863 | } | |
e806b4db LV |
1864 | |
1865 | g_free(sphb->msi_devs); | |
1866 | sphb->msi_devs = NULL; | |
1867 | sphb->msi_devs_num = g_hash_table_size(sphb->msi); | |
1868 | if (!sphb->msi_devs_num) { | |
44b1ff31 | 1869 | return 0; |
e806b4db LV |
1870 | } |
1871 | sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); | |
1872 | ||
1873 | g_hash_table_iter_init(&iter, sphb->msi); | |
1874 | for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { | |
1875 | sphb->msi_devs[i].key = *(uint32_t *) key; | |
1876 | sphb->msi_devs[i].value = *(spapr_pci_msi *) value; | |
1877 | } | |
44b1ff31 DDAG |
1878 | |
1879 | return 0; | |
9a321e92 AK |
1880 | } |
1881 | ||
1882 | static int spapr_pci_post_load(void *opaque, int version_id) | |
1883 | { | |
1884 | sPAPRPHBState *sphb = opaque; | |
1885 | gpointer key, value; | |
1886 | int i; | |
1887 | ||
1888 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
1889 | key = g_memdup(&sphb->msi_devs[i].key, | |
1890 | sizeof(sphb->msi_devs[i].key)); | |
1891 | value = g_memdup(&sphb->msi_devs[i].value, | |
1892 | sizeof(sphb->msi_devs[i].value)); | |
1893 | g_hash_table_insert(sphb->msi, key, value); | |
1894 | } | |
012aef07 MA |
1895 | g_free(sphb->msi_devs); |
1896 | sphb->msi_devs = NULL; | |
9a321e92 AK |
1897 | sphb->msi_devs_num = 0; |
1898 | ||
1899 | return 0; | |
1900 | } | |
1901 | ||
5c4537bd DG |
1902 | static bool pre_2_8_migration(void *opaque, int version_id) |
1903 | { | |
1904 | sPAPRPHBState *sphb = opaque; | |
1905 | ||
1906 | return sphb->pre_2_8_migration; | |
1907 | } | |
1908 | ||
1112cf94 DG |
1909 | static const VMStateDescription vmstate_spapr_pci = { |
1910 | .name = "spapr_pci", | |
5a78b821 | 1911 | .version_id = 2, |
9a321e92 AK |
1912 | .minimum_version_id = 2, |
1913 | .pre_save = spapr_pci_pre_save, | |
1914 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 1915 | .fields = (VMStateField[]) { |
d2164ad3 | 1916 | VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState, NULL), |
5c4537bd DG |
1917 | VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration), |
1918 | VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration), | |
1919 | VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration), | |
1920 | VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration), | |
1921 | VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration), | |
1112cf94 DG |
1922 | VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, |
1923 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), | |
9a321e92 AK |
1924 | VMSTATE_INT32(msi_devs_num, sPAPRPHBState), |
1925 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, | |
1926 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), | |
1112cf94 DG |
1927 | VMSTATE_END_OF_LIST() |
1928 | }, | |
1929 | }; | |
1930 | ||
568f0690 DG |
1931 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
1932 | PCIBus *rootbus) | |
1933 | { | |
1934 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
1935 | ||
1936 | return sphb->dtbusname; | |
1937 | } | |
1938 | ||
298a9710 DG |
1939 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
1940 | { | |
568f0690 | 1941 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 1942 | DeviceClass *dc = DEVICE_CLASS(klass); |
7454c7af | 1943 | HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); |
298a9710 | 1944 | |
568f0690 | 1945 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 1946 | dc->realize = spapr_phb_realize; |
298a9710 | 1947 | dc->props = spapr_phb_properties; |
eddeed26 | 1948 | dc->reset = spapr_phb_reset; |
1112cf94 | 1949 | dc->vmsd = &vmstate_spapr_pci; |
e4f4fb1e EH |
1950 | /* Supported by TYPE_SPAPR_MACHINE */ |
1951 | dc->user_creatable = true; | |
09aa9a52 | 1952 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
3340e5c4 DG |
1953 | hp->plug = spapr_pci_plug; |
1954 | hp->unplug_request = spapr_pci_unplug_request; | |
298a9710 | 1955 | } |
3384f95c | 1956 | |
4240abff | 1957 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 1958 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 1959 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
1960 | .instance_size = sizeof(sPAPRPHBState), |
1961 | .class_init = spapr_phb_class_init, | |
7454c7af MR |
1962 | .interfaces = (InterfaceInfo[]) { |
1963 | { TYPE_HOTPLUG_HANDLER }, | |
1964 | { } | |
1965 | } | |
298a9710 DG |
1966 | }; |
1967 | ||
28e02042 | 1968 | PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) |
298a9710 DG |
1969 | { |
1970 | DeviceState *dev; | |
1971 | ||
8c9f64df | 1972 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 1973 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 1974 | qdev_init_nofail(dev); |
caae58cb DG |
1975 | |
1976 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
1977 | } |
1978 | ||
1d2d9742 ND |
1979 | typedef struct sPAPRFDT { |
1980 | void *fdt; | |
1981 | int node_off; | |
1982 | sPAPRPHBState *sphb; | |
1983 | } sPAPRFDT; | |
1984 | ||
1985 | static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, | |
1986 | void *opaque) | |
1987 | { | |
1988 | PCIBus *sec_bus; | |
1989 | sPAPRFDT *p = opaque; | |
1990 | int offset; | |
1991 | sPAPRFDT s_fdt; | |
1d2d9742 | 1992 | |
e634b89c | 1993 | offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); |
1d2d9742 ND |
1994 | if (!offset) { |
1995 | error_report("Failed to create pci child device tree node"); | |
1996 | return; | |
1997 | } | |
1998 | ||
1999 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
2000 | PCI_HEADER_TYPE_BRIDGE)) { | |
2001 | return; | |
2002 | } | |
2003 | ||
2004 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
2005 | if (!sec_bus) { | |
2006 | return; | |
2007 | } | |
2008 | ||
2009 | s_fdt.fdt = p->fdt; | |
2010 | s_fdt.node_off = offset; | |
2011 | s_fdt.sphb = p->sphb; | |
a8eeafda GK |
2012 | pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus), |
2013 | spapr_populate_pci_devices_dt, | |
2014 | &s_fdt); | |
1d2d9742 ND |
2015 | } |
2016 | ||
2017 | static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, | |
2018 | void *opaque) | |
2019 | { | |
2020 | unsigned int *bus_no = opaque; | |
2021 | unsigned int primary = *bus_no; | |
2022 | unsigned int subordinate = 0xff; | |
2023 | PCIBus *sec_bus = NULL; | |
2024 | ||
2025 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
2026 | PCI_HEADER_TYPE_BRIDGE)) { | |
2027 | return; | |
2028 | } | |
2029 | ||
2030 | (*bus_no)++; | |
2031 | pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); | |
2032 | pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); | |
2033 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2034 | ||
2035 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
2036 | if (!sec_bus) { | |
2037 | return; | |
2038 | } | |
2039 | ||
2040 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); | |
2041 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
2042 | spapr_phb_pci_enumerate_bridge, bus_no); | |
2043 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2044 | } | |
2045 | ||
2046 | static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) | |
2047 | { | |
2048 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; | |
2049 | unsigned int bus_no = 0; | |
2050 | ||
2051 | pci_for_each_device(bus, pci_bus_num(bus), | |
2052 | spapr_phb_pci_enumerate_bridge, | |
2053 | &bus_no); | |
2054 | ||
2055 | } | |
2056 | ||
e0fdbd7c AK |
2057 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
2058 | uint32_t xics_phandle, | |
2059 | void *fdt) | |
3384f95c | 2060 | { |
62083979 | 2061 | int bus_off, i, j, ret; |
549ce59e | 2062 | gchar *nodename; |
3384f95c DG |
2063 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
2064 | struct { | |
2065 | uint32_t hi; | |
2066 | uint64_t child; | |
2067 | uint64_t parent; | |
2068 | uint64_t size; | |
c4889f54 | 2069 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
2070 | { |
2071 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
2072 | cpu_to_be64(phb->io_win_addr), | |
2073 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
2074 | }, | |
2075 | { | |
2076 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
2077 | cpu_to_be64(phb->mem_win_addr), | |
daa23699 | 2078 | cpu_to_be64(phb->mem_win_size), |
b194df47 AK |
2079 | }, |
2080 | { | |
daa23699 DG |
2081 | cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), |
2082 | cpu_to_be64(phb->mem64_win_addr), | |
2083 | cpu_to_be64(phb->mem64_win_size), | |
3384f95c DG |
2084 | }, |
2085 | }; | |
daa23699 DG |
2086 | const unsigned sizeof_ranges = |
2087 | (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); | |
3384f95c DG |
2088 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
2089 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
2090 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
2091 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
ae4de14c AK |
2092 | uint32_t ddw_applicable[] = { |
2093 | cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), | |
2094 | cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), | |
2095 | cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) | |
2096 | }; | |
2097 | uint32_t ddw_extensions[] = { | |
2098 | cpu_to_be32(1), | |
2099 | cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) | |
2100 | }; | |
4814401f AK |
2101 | uint32_t associativity[] = {cpu_to_be32(0x4), |
2102 | cpu_to_be32(0x0), | |
2103 | cpu_to_be32(0x0), | |
2104 | cpu_to_be32(0x0), | |
2105 | cpu_to_be32(phb->numa_node)}; | |
ccf9ff85 | 2106 | sPAPRTCETable *tcet; |
1d2d9742 ND |
2107 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; |
2108 | sPAPRFDT s_fdt; | |
3384f95c DG |
2109 | |
2110 | /* Start populating the FDT */ | |
549ce59e | 2111 | nodename = g_strdup_printf("pci@%" PRIx64, phb->buid); |
9ba25536 | 2112 | _FDT(bus_off = fdt_add_subnode(fdt, 0, nodename)); |
549ce59e | 2113 | g_free(nodename); |
3384f95c | 2114 | |
3384f95c DG |
2115 | /* Write PHB properties */ |
2116 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
2117 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
2118 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
2119 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
2120 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
2121 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
2122 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 2123 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 2124 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 2125 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
161deaf2 | 2126 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR)); |
3384f95c | 2127 | |
ae4de14c AK |
2128 | /* Dynamic DMA window */ |
2129 | if (phb->ddw_enabled) { | |
2130 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, | |
2131 | sizeof(ddw_applicable))); | |
2132 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", | |
2133 | &ddw_extensions, sizeof(ddw_extensions))); | |
2134 | } | |
2135 | ||
4814401f | 2136 | /* Advertise NUMA via ibm,associativity */ |
4bcfa56c | 2137 | if (phb->numa_node != -1) { |
4814401f AK |
2138 | _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, |
2139 | sizeof(associativity))); | |
2140 | } | |
2141 | ||
4d8d5467 BH |
2142 | /* Build the interrupt-map, this must matches what is done |
2143 | * in pci_spapr_map_irq | |
2144 | */ | |
2145 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
2146 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
2147 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
2148 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
2149 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
2150 | int lsi_num = pci_spapr_swizzle(i, j); | |
2151 | ||
2152 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
2153 | irqmap[1] = 0; | |
2154 | irqmap[2] = 0; | |
2155 | irqmap[3] = cpu_to_be32(j+1); | |
2156 | irqmap[4] = cpu_to_be32(xics_phandle); | |
bb2d8ab6 | 2157 | spapr_dt_xics_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); |
7fb0bd34 | 2158 | } |
3384f95c | 2159 | } |
3384f95c DG |
2160 | /* Write interrupt map */ |
2161 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 2162 | sizeof(interrupt_map))); |
3384f95c | 2163 | |
ae4de14c | 2164 | tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); |
da34fed7 TH |
2165 | if (!tcet) { |
2166 | return -1; | |
2167 | } | |
ccf9ff85 AK |
2168 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", |
2169 | tcet->liobn, tcet->bus_offset, | |
2170 | tcet->nb_table << tcet->page_shift); | |
edded454 | 2171 | |
1d2d9742 ND |
2172 | /* Walk the bridges and program the bus numbers*/ |
2173 | spapr_phb_pci_enumerate(phb); | |
2174 | _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); | |
2175 | ||
2176 | /* Populate tree nodes with PCI devices attached */ | |
2177 | s_fdt.fdt = fdt; | |
2178 | s_fdt.node_off = bus_off; | |
2179 | s_fdt.sphb = phb; | |
a8eeafda GK |
2180 | pci_for_each_device_reverse(bus, pci_bus_num(bus), |
2181 | spapr_populate_pci_devices_dt, | |
2182 | &s_fdt); | |
1d2d9742 | 2183 | |
62083979 MR |
2184 | ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), |
2185 | SPAPR_DR_CONNECTOR_TYPE_PCI); | |
2186 | if (ret) { | |
2187 | return ret; | |
2188 | } | |
2189 | ||
3384f95c DG |
2190 | return 0; |
2191 | } | |
298a9710 | 2192 | |
fa28f71b AK |
2193 | void spapr_pci_rtas_init(void) |
2194 | { | |
3a3b8502 AK |
2195 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
2196 | rtas_read_pci_config); | |
2197 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
2198 | rtas_write_pci_config); | |
2199 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
2200 | rtas_ibm_read_pci_config); | |
2201 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
2202 | rtas_ibm_write_pci_config); | |
226419d6 | 2203 | if (msi_nonbroken) { |
3a3b8502 AK |
2204 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
2205 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 2206 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
2207 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
2208 | rtas_ibm_change_msi); | |
0ee2c058 | 2209 | } |
ee954280 GS |
2210 | |
2211 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
2212 | "ibm,set-eeh-option", | |
2213 | rtas_ibm_set_eeh_option); | |
2214 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
2215 | "ibm,get-config-addr-info2", | |
2216 | rtas_ibm_get_config_addr_info2); | |
2217 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
2218 | "ibm,read-slot-reset-state2", | |
2219 | rtas_ibm_read_slot_reset_state2); | |
2220 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
2221 | "ibm,set-slot-reset", | |
2222 | rtas_ibm_set_slot_reset); | |
2223 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
2224 | "ibm,configure-pe", | |
2225 | rtas_ibm_configure_pe); | |
2226 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
2227 | "ibm,slot-error-detail", | |
2228 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
2229 | } |
2230 | ||
8c9f64df | 2231 | static void spapr_pci_register_types(void) |
298a9710 DG |
2232 | { |
2233 | type_register_static(&spapr_phb_info); | |
2234 | } | |
8c9f64df AF |
2235 | |
2236 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
2237 | |
2238 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
2239 | { | |
2240 | bool be = *(bool *)opaque; | |
2241 | ||
2242 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
2243 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
2244 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
2245 | &error_abort); | |
2246 | } | |
2247 | return 0; | |
2248 | } | |
2249 | ||
2250 | void spapr_pci_switch_vga(bool big_endian) | |
2251 | { | |
28e02042 | 2252 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
eefaccc0 DG |
2253 | sPAPRPHBState *sphb; |
2254 | ||
2255 | /* | |
2256 | * For backward compatibility with existing guests, we switch | |
2257 | * the endianness of the VGA controller when changing the guest | |
2258 | * interrupt mode | |
2259 | */ | |
2260 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
2261 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
2262 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
2263 | &big_endian); | |
2264 | } | |
2265 | } |