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CommitLineData
3384f95c
DG
1/*
2 * QEMU sPAPR PCI host originated from Uninorth PCI host
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
0b8fa32f 25
0d75590d 26#include "qemu/osdep.h"
da34e65c 27#include "qapi/error.h"
4771d756 28#include "cpu.h"
64552b6b 29#include "hw/irq.h"
1d2d9742 30#include "hw/sysbus.h"
d6454270 31#include "migration/vmstate.h"
83c9f4ca
PB
32#include "hw/pci/pci.h"
33#include "hw/pci/msi.h"
34#include "hw/pci/msix.h"
35#include "hw/pci/pci_host.h"
0d09e41a
PB
36#include "hw/ppc/spapr.h"
37#include "hw/pci-host/spapr.h"
022c62cb 38#include "exec/address-spaces.h"
ae4de14c 39#include "exec/ram_addr.h"
3384f95c 40#include <libfdt.h>
a2950fb6 41#include "trace.h"
295d51aa 42#include "qemu/error-report.h"
0b8fa32f 43#include "qemu/module.h"
7454c7af 44#include "qapi/qmp/qerror.h"
99372e78 45#include "hw/ppc/fdt.h"
1d2d9742 46#include "hw/pci/pci_bridge.h"
06aac7bd 47#include "hw/pci/pci_bus.h"
2530a1a5 48#include "hw/pci/pci_ids.h"
62083979 49#include "hw/ppc/spapr_drc.h"
a27bd6c7 50#include "hw/qdev-properties.h"
7454c7af 51#include "sysemu/device_tree.h"
77ac58dd 52#include "sysemu/kvm.h"
ae4de14c 53#include "sysemu/hostmem.h"
4814401f 54#include "sysemu/numa.h"
3384f95c 55
0ee2c058
AK
56/* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
57#define RTAS_QUERY_FN 0
58#define RTAS_CHANGE_FN 1
59#define RTAS_RESET_FN 2
60#define RTAS_CHANGE_MSI_FN 3
61#define RTAS_CHANGE_MSIX_FN 4
62
63/* Interrupt types to return on RTAS_CHANGE_* */
64#define RTAS_TYPE_MSI 1
65#define RTAS_TYPE_MSIX 2
66
ce2918cb 67SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid)
3384f95c 68{
ce2918cb 69 SpaprPhbState *sphb;
3384f95c 70
8c9f64df
AF
71 QLIST_FOREACH(sphb, &spapr->phbs, list) {
72 if (sphb->buid != buid) {
3384f95c
DG
73 continue;
74 }
8c9f64df 75 return sphb;
9894c5d4
AK
76 }
77
78 return NULL;
79}
80
ce2918cb 81PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
46c5874e 82 uint32_t config_addr)
9894c5d4 83{
ce2918cb 84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid);
8558d942 85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
5dac82ce 86 int bus_num = (config_addr >> 16) & 0xFF;
9894c5d4
AK
87 int devfn = (config_addr >> 8) & 0xFF;
88
89 if (!phb) {
90 return NULL;
91 }
3384f95c 92
5dac82ce 93 return pci_find_device(phb->bus, bus_num, devfn);
3384f95c
DG
94}
95
3f7565c9
BH
96static uint32_t rtas_pci_cfgaddr(uint32_t arg)
97{
92615a5a 98 /* This handles the encoding of extended config space addresses */
3f7565c9
BH
99 return ((arg >> 20) & 0xf00) | (arg & 0xff);
100}
101
ce2918cb 102static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid,
92615a5a
DG
103 uint32_t addr, uint32_t size,
104 target_ulong rets)
88045ac5 105{
92615a5a
DG
106 PCIDevice *pci_dev;
107 uint32_t val;
108
109 if ((size != 1) && (size != 2) && (size != 4)) {
110 /* access must be 1, 2 or 4 bytes */
a64d325d 111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
92615a5a 112 return;
88045ac5 113 }
88045ac5 114
46c5874e 115 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
92615a5a
DG
116 addr = rtas_pci_cfgaddr(addr);
117
118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
119 /* Access must be to a valid device, within bounds and
120 * naturally aligned */
a64d325d 121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
92615a5a 122 return;
88045ac5 123 }
92615a5a
DG
124
125 val = pci_host_config_read_common(pci_dev, addr,
126 pci_config_size(pci_dev), size);
127
a64d325d 128 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
92615a5a 129 rtas_st(rets, 1, val);
88045ac5
AG
130}
131
ce2918cb 132static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
3384f95c
DG
133 uint32_t token, uint32_t nargs,
134 target_ulong args,
135 uint32_t nret, target_ulong rets)
136{
92615a5a
DG
137 uint64_t buid;
138 uint32_t size, addr;
3384f95c 139
92615a5a 140 if ((nargs != 4) || (nret != 2)) {
a64d325d 141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
3384f95c
DG
142 return;
143 }
92615a5a 144
a14aa92b 145 buid = rtas_ldq(args, 1);
3384f95c 146 size = rtas_ld(args, 3);
92615a5a
DG
147 addr = rtas_ld(args, 0);
148
149 finish_read_pci_config(spapr, buid, addr, size, rets);
3384f95c
DG
150}
151
ce2918cb 152static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
3384f95c
DG
153 uint32_t token, uint32_t nargs,
154 target_ulong args,
155 uint32_t nret, target_ulong rets)
156{
92615a5a 157 uint32_t size, addr;
3384f95c 158
92615a5a 159 if ((nargs != 2) || (nret != 2)) {
a64d325d 160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
3384f95c
DG
161 return;
162 }
92615a5a 163
3384f95c 164 size = rtas_ld(args, 1);
92615a5a
DG
165 addr = rtas_ld(args, 0);
166
167 finish_read_pci_config(spapr, 0, addr, size, rets);
168}
169
ce2918cb 170static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid,
92615a5a
DG
171 uint32_t addr, uint32_t size,
172 uint32_t val, target_ulong rets)
173{
174 PCIDevice *pci_dev;
175
176 if ((size != 1) && (size != 2) && (size != 4)) {
177 /* access must be 1, 2 or 4 bytes */
a64d325d 178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
92615a5a
DG
179 return;
180 }
181
46c5874e 182 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
92615a5a
DG
183 addr = rtas_pci_cfgaddr(addr);
184
185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
186 /* Access must be to a valid device, within bounds and
187 * naturally aligned */
a64d325d 188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
92615a5a
DG
189 return;
190 }
191
192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
193 val, size);
194
a64d325d 195 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
3384f95c
DG
196}
197
ce2918cb 198static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
3384f95c
DG
199 uint32_t token, uint32_t nargs,
200 target_ulong args,
201 uint32_t nret, target_ulong rets)
202{
92615a5a 203 uint64_t buid;
3384f95c 204 uint32_t val, size, addr;
3384f95c 205
92615a5a 206 if ((nargs != 5) || (nret != 1)) {
a64d325d 207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
3384f95c
DG
208 return;
209 }
92615a5a 210
a14aa92b 211 buid = rtas_ldq(args, 1);
3384f95c
DG
212 val = rtas_ld(args, 4);
213 size = rtas_ld(args, 3);
92615a5a
DG
214 addr = rtas_ld(args, 0);
215
216 finish_write_pci_config(spapr, buid, addr, size, val, rets);
3384f95c
DG
217}
218
ce2918cb 219static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
3384f95c
DG
220 uint32_t token, uint32_t nargs,
221 target_ulong args,
222 uint32_t nret, target_ulong rets)
223{
224 uint32_t val, size, addr;
3384f95c 225
92615a5a 226 if ((nargs != 3) || (nret != 1)) {
a64d325d 227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
3384f95c
DG
228 return;
229 }
92615a5a
DG
230
231
3384f95c
DG
232 val = rtas_ld(args, 2);
233 size = rtas_ld(args, 1);
92615a5a
DG
234 addr = rtas_ld(args, 0);
235
236 finish_write_pci_config(spapr, 0, addr, size, val, rets);
3384f95c
DG
237}
238
0ee2c058
AK
239/*
240 * Set MSI/MSIX message data.
241 * This is required for msi_notify()/msix_notify() which
242 * will write at the addresses via spapr_msi_write().
9a321e92
AK
243 *
244 * If hwaddr == 0, all entries will have .data == first_irq i.e.
245 * table will be reset.
0ee2c058 246 */
f1c2dc7c
AK
247static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
248 unsigned first_irq, unsigned req_num)
0ee2c058
AK
249{
250 unsigned i;
f1c2dc7c 251 MSIMessage msg = { .address = addr, .data = first_irq };
0ee2c058
AK
252
253 if (!msix) {
254 msi_set_message(pdev, msg);
255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
256 return;
257 }
258
9a321e92 259 for (i = 0; i < req_num; ++i) {
0ee2c058
AK
260 msix_set_message(pdev, i, msg);
261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
9a321e92
AK
262 if (addr) {
263 ++msg.data;
264 }
0ee2c058
AK
265 }
266}
267
ce2918cb 268static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
0ee2c058
AK
269 uint32_t token, uint32_t nargs,
270 target_ulong args, uint32_t nret,
271 target_ulong rets)
272{
ce2918cb 273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
0ee2c058 274 uint32_t config_addr = rtas_ld(args, 0);
a14aa92b 275 uint64_t buid = rtas_ldq(args, 1);
0ee2c058
AK
276 unsigned int func = rtas_ld(args, 3);
277 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
278 unsigned int seq_num = rtas_ld(args, 5);
279 unsigned int ret_intr_type;
d4a63ac8 280 unsigned int irq, max_irqs = 0;
ce2918cb 281 SpaprPhbState *phb = NULL;
0ee2c058 282 PCIDevice *pdev = NULL;
9a321e92
AK
283 spapr_pci_msi *msi;
284 int *config_addr_key;
a005b3ef 285 Error *err = NULL;
4fe75a8c 286 int i;
0ee2c058 287
ce2918cb 288 /* Fins SpaprPhbState */
9cbe305b
GK
289 phb = spapr_pci_find_phb(spapr, buid);
290 if (phb) {
291 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
292 }
293 if (!phb || !pdev) {
294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
295 return;
296 }
297
0ee2c058 298 switch (func) {
0ee2c058 299 case RTAS_CHANGE_FN:
9cbe305b
GK
300 if (msi_present(pdev)) {
301 ret_intr_type = RTAS_TYPE_MSI;
302 } else if (msix_present(pdev)) {
303 ret_intr_type = RTAS_TYPE_MSIX;
304 } else {
305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
306 return;
307 }
308 break;
309 case RTAS_CHANGE_MSI_FN:
310 if (msi_present(pdev)) {
311 ret_intr_type = RTAS_TYPE_MSI;
312 } else {
313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
314 return;
315 }
0ee2c058
AK
316 break;
317 case RTAS_CHANGE_MSIX_FN:
9cbe305b
GK
318 if (msix_present(pdev)) {
319 ret_intr_type = RTAS_TYPE_MSIX;
320 } else {
321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
322 return;
323 }
0ee2c058
AK
324 break;
325 default:
295d51aa 326 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
a64d325d 327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
0ee2c058
AK
328 return;
329 }
330
ce266b75
GK
331 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
332
0ee2c058
AK
333 /* Releasing MSIs */
334 if (!req_num) {
9a321e92
AK
335 if (!msi) {
336 trace_spapr_pci_msi("Releasing wrong config", config_addr);
a64d325d 337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
0ee2c058
AK
338 return;
339 }
9a321e92 340
32420522 341 if (msi_present(pdev)) {
d4a63ac8 342 spapr_msi_setmsg(pdev, 0, false, 0, 0);
32420522
AK
343 }
344 if (msix_present(pdev)) {
d4a63ac8 345 spapr_msi_setmsg(pdev, 0, true, 0, 0);
32420522 346 }
9a321e92
AK
347 g_hash_table_remove(phb->msi, &config_addr);
348
349 trace_spapr_pci_msi("Released MSIs", config_addr);
a64d325d 350 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
0ee2c058
AK
351 rtas_st(rets, 1, 0);
352 return;
353 }
354
355 /* Enabling MSI */
356
28668b5f
AK
357 /* Check if the device supports as many IRQs as requested */
358 if (ret_intr_type == RTAS_TYPE_MSI) {
359 max_irqs = msi_nr_vectors_allocated(pdev);
360 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
361 max_irqs = pdev->msix_entries_nr;
362 }
363 if (!max_irqs) {
9a321e92
AK
364 error_report("Requested interrupt type %d is not enabled for device %x",
365 ret_intr_type, config_addr);
28668b5f
AK
366 rtas_st(rets, 0, -1); /* Hardware error */
367 return;
368 }
369 /* Correct the number if the guest asked for too many */
370 if (req_num > max_irqs) {
9a321e92 371 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
28668b5f 372 req_num = max_irqs;
9a321e92
AK
373 irq = 0; /* to avoid misleading trace */
374 goto out;
28668b5f
AK
375 }
376
9a321e92 377 /* Allocate MSIs */
2c88b098 378 if (smc->legacy_irq_allocation) {
82cffa2e
CLG
379 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI,
380 &err);
381 } else {
382 irq = spapr_irq_msi_alloc(spapr, req_num,
383 ret_intr_type == RTAS_TYPE_MSI, &err);
384 }
a005b3ef
GK
385 if (err) {
386 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
387 config_addr);
a64d325d 388 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
0ee2c058
AK
389 return;
390 }
391
4fe75a8c
CLG
392 for (i = 0; i < req_num; i++) {
393 spapr_irq_claim(spapr, irq + i, false, &err);
394 if (err) {
925969c3
GK
395 if (i) {
396 spapr_irq_free(spapr, irq, i);
397 }
398 if (!smc->legacy_irq_allocation) {
399 spapr_irq_msi_free(spapr, irq, req_num);
400 }
4fe75a8c
CLG
401 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
402 config_addr);
403 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
404 return;
405 }
406 }
407
ce266b75
GK
408 /* Release previous MSIs */
409 if (msi) {
ce266b75
GK
410 g_hash_table_remove(phb->msi, &config_addr);
411 }
412
0ee2c058 413 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
8c46f7ec 414 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
9a321e92 415 irq, req_num);
0ee2c058 416
9a321e92
AK
417 /* Add MSI device to cache */
418 msi = g_new(spapr_pci_msi, 1);
419 msi->first_irq = irq;
420 msi->num = req_num;
421 config_addr_key = g_new(int, 1);
422 *config_addr_key = config_addr;
423 g_hash_table_insert(phb->msi, config_addr_key, msi);
424
425out:
a64d325d 426 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
0ee2c058
AK
427 rtas_st(rets, 1, req_num);
428 rtas_st(rets, 2, ++seq_num);
b359bd6a
SB
429 if (nret > 3) {
430 rtas_st(rets, 3, ret_intr_type);
431 }
0ee2c058 432
9a321e92 433 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
0ee2c058
AK
434}
435
210b580b 436static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
ce2918cb 437 SpaprMachineState *spapr,
0ee2c058
AK
438 uint32_t token,
439 uint32_t nargs,
440 target_ulong args,
441 uint32_t nret,
442 target_ulong rets)
443{
444 uint32_t config_addr = rtas_ld(args, 0);
a14aa92b 445 uint64_t buid = rtas_ldq(args, 1);
0ee2c058 446 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
ce2918cb 447 SpaprPhbState *phb = NULL;
9a321e92
AK
448 PCIDevice *pdev = NULL;
449 spapr_pci_msi *msi;
0ee2c058 450
ce2918cb 451 /* Find SpaprPhbState */
46c5874e 452 phb = spapr_pci_find_phb(spapr, buid);
9a321e92 453 if (phb) {
46c5874e 454 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
9a321e92
AK
455 }
456 if (!phb || !pdev) {
a64d325d 457 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
0ee2c058
AK
458 return;
459 }
460
461 /* Find device descriptor and start IRQ */
9a321e92
AK
462 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
463 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
464 trace_spapr_pci_msi("Failed to return vector", config_addr);
a64d325d 465 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
0ee2c058
AK
466 return;
467 }
9a321e92 468 intr_src_num = msi->first_irq + ioa_intr_num;
0ee2c058
AK
469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
470 intr_src_num);
471
a64d325d 472 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
0ee2c058
AK
473 rtas_st(rets, 1, intr_src_num);
474 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
475}
476
ee954280 477static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
ce2918cb 478 SpaprMachineState *spapr,
ee954280
GS
479 uint32_t token, uint32_t nargs,
480 target_ulong args, uint32_t nret,
481 target_ulong rets)
482{
ce2918cb 483 SpaprPhbState *sphb;
ee954280
GS
484 uint32_t addr, option;
485 uint64_t buid;
486 int ret;
487
488 if ((nargs != 4) || (nret != 1)) {
489 goto param_error_exit;
490 }
491
a14aa92b 492 buid = rtas_ldq(args, 1);
ee954280
GS
493 addr = rtas_ld(args, 0);
494 option = rtas_ld(args, 3);
495
46c5874e 496 sphb = spapr_pci_find_phb(spapr, buid);
ee954280
GS
497 if (!sphb) {
498 goto param_error_exit;
499 }
500
fbb4e983 501 if (!spapr_phb_eeh_available(sphb)) {
ee954280
GS
502 goto param_error_exit;
503 }
504
fbb4e983 505 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
ee954280
GS
506 rtas_st(rets, 0, ret);
507 return;
508
509param_error_exit:
510 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
511}
512
513static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
ce2918cb 514 SpaprMachineState *spapr,
ee954280
GS
515 uint32_t token, uint32_t nargs,
516 target_ulong args, uint32_t nret,
517 target_ulong rets)
518{
ce2918cb 519 SpaprPhbState *sphb;
ee954280
GS
520 PCIDevice *pdev;
521 uint32_t addr, option;
522 uint64_t buid;
523
524 if ((nargs != 4) || (nret != 2)) {
525 goto param_error_exit;
526 }
527
a14aa92b 528 buid = rtas_ldq(args, 1);
46c5874e 529 sphb = spapr_pci_find_phb(spapr, buid);
ee954280
GS
530 if (!sphb) {
531 goto param_error_exit;
532 }
533
fbb4e983 534 if (!spapr_phb_eeh_available(sphb)) {
ee954280
GS
535 goto param_error_exit;
536 }
537
538 /*
539 * We always have PE address of form "00BB0001". "BB"
540 * represents the bus number of PE's primary bus.
541 */
542 option = rtas_ld(args, 3);
543 switch (option) {
544 case RTAS_GET_PE_ADDR:
545 addr = rtas_ld(args, 0);
46c5874e 546 pdev = spapr_pci_find_dev(spapr, buid, addr);
ee954280
GS
547 if (!pdev) {
548 goto param_error_exit;
549 }
550
fd56e061 551 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1);
ee954280
GS
552 break;
553 case RTAS_GET_PE_MODE:
554 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
555 break;
556 default:
557 goto param_error_exit;
558 }
559
560 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
561 return;
562
563param_error_exit:
564 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
565}
566
567static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
ce2918cb 568 SpaprMachineState *spapr,
ee954280
GS
569 uint32_t token, uint32_t nargs,
570 target_ulong args, uint32_t nret,
571 target_ulong rets)
572{
ce2918cb 573 SpaprPhbState *sphb;
ee954280
GS
574 uint64_t buid;
575 int state, ret;
576
577 if ((nargs != 3) || (nret != 4 && nret != 5)) {
578 goto param_error_exit;
579 }
580
a14aa92b 581 buid = rtas_ldq(args, 1);
46c5874e 582 sphb = spapr_pci_find_phb(spapr, buid);
ee954280
GS
583 if (!sphb) {
584 goto param_error_exit;
585 }
586
fbb4e983 587 if (!spapr_phb_eeh_available(sphb)) {
ee954280
GS
588 goto param_error_exit;
589 }
590
fbb4e983 591 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
ee954280
GS
592 rtas_st(rets, 0, ret);
593 if (ret != RTAS_OUT_SUCCESS) {
594 return;
595 }
596
597 rtas_st(rets, 1, state);
598 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
599 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
600 if (nret >= 5) {
601 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
602 }
603 return;
604
605param_error_exit:
606 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
607}
608
609static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
ce2918cb 610 SpaprMachineState *spapr,
ee954280
GS
611 uint32_t token, uint32_t nargs,
612 target_ulong args, uint32_t nret,
613 target_ulong rets)
614{
ce2918cb 615 SpaprPhbState *sphb;
ee954280
GS
616 uint32_t option;
617 uint64_t buid;
618 int ret;
619
620 if ((nargs != 4) || (nret != 1)) {
621 goto param_error_exit;
622 }
623
a14aa92b 624 buid = rtas_ldq(args, 1);
ee954280 625 option = rtas_ld(args, 3);
46c5874e 626 sphb = spapr_pci_find_phb(spapr, buid);
ee954280
GS
627 if (!sphb) {
628 goto param_error_exit;
629 }
630
fbb4e983 631 if (!spapr_phb_eeh_available(sphb)) {
ee954280
GS
632 goto param_error_exit;
633 }
634
fbb4e983 635 ret = spapr_phb_vfio_eeh_reset(sphb, option);
ee954280
GS
636 rtas_st(rets, 0, ret);
637 return;
638
639param_error_exit:
640 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
641}
642
643static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
ce2918cb 644 SpaprMachineState *spapr,
ee954280
GS
645 uint32_t token, uint32_t nargs,
646 target_ulong args, uint32_t nret,
647 target_ulong rets)
648{
ce2918cb 649 SpaprPhbState *sphb;
ee954280
GS
650 uint64_t buid;
651 int ret;
652
653 if ((nargs != 3) || (nret != 1)) {
654 goto param_error_exit;
655 }
656
a14aa92b 657 buid = rtas_ldq(args, 1);
46c5874e 658 sphb = spapr_pci_find_phb(spapr, buid);
ee954280
GS
659 if (!sphb) {
660 goto param_error_exit;
661 }
662
fbb4e983 663 if (!spapr_phb_eeh_available(sphb)) {
ee954280
GS
664 goto param_error_exit;
665 }
666
fbb4e983 667 ret = spapr_phb_vfio_eeh_configure(sphb);
ee954280
GS
668 rtas_st(rets, 0, ret);
669 return;
670
671param_error_exit:
672 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
673}
674
675/* To support it later */
676static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
ce2918cb 677 SpaprMachineState *spapr,
ee954280
GS
678 uint32_t token, uint32_t nargs,
679 target_ulong args, uint32_t nret,
680 target_ulong rets)
681{
ce2918cb 682 SpaprPhbState *sphb;
ee954280
GS
683 int option;
684 uint64_t buid;
685
686 if ((nargs != 8) || (nret != 1)) {
687 goto param_error_exit;
688 }
689
a14aa92b 690 buid = rtas_ldq(args, 1);
46c5874e 691 sphb = spapr_pci_find_phb(spapr, buid);
ee954280
GS
692 if (!sphb) {
693 goto param_error_exit;
694 }
695
fbb4e983 696 if (!spapr_phb_eeh_available(sphb)) {
ee954280
GS
697 goto param_error_exit;
698 }
699
700 option = rtas_ld(args, 7);
701 switch (option) {
702 case RTAS_SLOT_TEMP_ERR_LOG:
703 case RTAS_SLOT_PERM_ERR_LOG:
704 break;
705 default:
706 goto param_error_exit;
707 }
708
709 /* We don't have error log yet */
710 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
711 return;
712
713param_error_exit:
714 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
715}
716
3384f95c
DG
717static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
718{
719 /*
e8ec4adf 720 * Here we use the number returned by pci_swizzle_map_irq_fn to find a
3384f95c
DG
721 * corresponding qemu_irq.
722 */
ce2918cb 723 SpaprPhbState *phb = opaque;
3384f95c 724
caae58cb 725 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
a307d594 726 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
3384f95c
DG
727}
728
5cc7a967
AK
729static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
730{
ce2918cb 731 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
5cc7a967
AK
732 PCIINTxRoute route;
733
734 route.mode = PCI_INTX_ENABLED;
735 route.irq = sphb->lsi_table[pin].irq;
736
737 return route;
738}
739
0ee2c058
AK
740/*
741 * MSI/MSIX memory region implementation.
742 * The handler handles both MSI and MSIX.
18f2330e 743 * The vector number is encoded in least bits in data.
0ee2c058 744 */
a8170e5e 745static void spapr_msi_write(void *opaque, hwaddr addr,
0ee2c058
AK
746 uint64_t data, unsigned size)
747{
ce2918cb 748 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
f1c2dc7c 749 uint32_t irq = data;
0ee2c058
AK
750
751 trace_spapr_pci_msi_write(addr, data, irq);
752
77183755 753 qemu_irq_pulse(spapr_qirq(spapr, irq));
0ee2c058
AK
754}
755
756static const MemoryRegionOps spapr_msi_ops = {
757 /* There is no .read as the read result is undefined by PCI spec */
758 .read = NULL,
759 .write = spapr_msi_write,
760 .endianness = DEVICE_LITTLE_ENDIAN
761};
762
298a9710
DG
763/*
764 * PHB PCI device
765 */
e00387d5 766static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
edded454 767{
ce2918cb 768 SpaprPhbState *phb = opaque;
edded454 769
e00387d5 770 return &phb->iommu_as;
edded454
DG
771}
772
ce2918cb 773static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
16b0ea1d
ND
774{
775 char *path = NULL, *buf = NULL, *host = NULL;
776
777 /* Get the PCI VFIO host id */
778 host = object_property_get_str(OBJECT(pdev), "host", NULL);
779 if (!host) {
780 goto err_out;
781 }
782
783 /* Construct the path of the file that will give us the DT location */
784 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
785 g_free(host);
8f687605 786 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
16b0ea1d
ND
787 goto err_out;
788 }
789 g_free(path);
790
791 /* Construct and read from host device tree the loc-code */
792 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
793 g_free(buf);
8f687605 794 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
16b0ea1d
ND
795 goto err_out;
796 }
797 return buf;
798
799err_out:
800 g_free(path);
801 return NULL;
802}
803
ce2918cb 804static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
16b0ea1d
ND
805{
806 char *buf;
807 const char *devtype = "qemu";
808 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
809
810 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
811 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
812 if (buf) {
813 return buf;
814 }
815 devtype = "vfio";
816 }
817 /*
818 * For emulated devices and VFIO-failure case, make up
819 * the loc-code.
820 */
821 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
822 devtype, pdev->name, sphb->index, busnr,
823 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
824 return buf;
825}
826
7454c7af
MR
827/* Macros to operate with address in OF binding to PCI */
828#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
829#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
830#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
831#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
832#define b_ss(x) b_x((x), 24, 2) /* the space code */
833#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
834#define b_ddddd(x) b_x((x), 11, 5) /* device number */
835#define b_fff(x) b_x((x), 8, 3) /* function number */
836#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
837
838/* for 'reg'/'assigned-addresses' OF properties */
839#define RESOURCE_CELLS_SIZE 2
840#define RESOURCE_CELLS_ADDRESS 3
841
842typedef struct ResourceFields {
843 uint32_t phys_hi;
844 uint32_t phys_mid;
845 uint32_t phys_lo;
846 uint32_t size_hi;
847 uint32_t size_lo;
848} QEMU_PACKED ResourceFields;
849
850typedef struct ResourceProps {
851 ResourceFields reg[8];
852 ResourceFields assigned[7];
853 uint32_t reg_len;
854 uint32_t assigned_len;
855} ResourceProps;
856
857/* fill in the 'reg'/'assigned-resources' OF properties for
858 * a PCI device. 'reg' describes resource requirements for a
859 * device's IO/MEM regions, 'assigned-addresses' describes the
860 * actual resource assignments.
861 *
862 * the properties are arrays of ('phys-addr', 'size') pairs describing
863 * the addressable regions of the PCI device, where 'phys-addr' is a
864 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
865 * (phys.hi, phys.mid, phys.lo), and 'size' is a
866 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
867 *
868 * phys.hi = 0xYYXXXXZZ, where:
869 * 0xYY = npt000ss
870 * ||| |
72187935
ND
871 * ||| +-- space code
872 * ||| |
873 * ||| + 00 if configuration space
874 * ||| + 01 if IO region,
875 * ||| + 10 if 32-bit MEM region
876 * ||| + 11 if 64-bit MEM region
877 * |||
7454c7af
MR
878 * ||+------ for non-relocatable IO: 1 if aliased
879 * || for relocatable IO: 1 if below 64KB
880 * || for MEM: 1 if below 1MB
881 * |+------- 1 if region is prefetchable
882 * +-------- 1 if region is non-relocatable
883 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
884 * bits respectively
885 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
886 * to the region
887 *
888 * phys.mid and phys.lo correspond respectively to the hi/lo portions
889 * of the actual address of the region.
890 *
891 * how the phys-addr/size values are used differ slightly between
892 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
893 * an additional description for the config space region of the
894 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
895 * to describe the region as relocatable, with an address-mapping
896 * that corresponds directly to the PHB's address space for the
897 * resource. 'assigned-addresses' always has n=1 set with an absolute
898 * address assigned for the resource. in general, 'assigned-addresses'
899 * won't be populated, since addresses for PCI devices are generally
900 * unmapped initially and left to the guest to assign.
901 *
902 * note also that addresses defined in these properties are, at least
903 * for PAPR guests, relative to the PHBs IO/MEM windows, and
904 * correspond directly to the addresses in the BARs.
905 *
906 * in accordance with PCI Bus Binding to Open Firmware,
907 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
908 * Appendix C.
909 */
910static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
911{
912 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
913 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
914 b_ddddd(PCI_SLOT(d->devfn)) |
915 b_fff(PCI_FUNC(d->devfn)));
916 ResourceFields *reg, *assigned;
917 int i, reg_idx = 0, assigned_idx = 0;
918
919 /* config space region */
920 reg = &rp->reg[reg_idx++];
921 reg->phys_hi = cpu_to_be32(dev_id);
922 reg->phys_mid = 0;
923 reg->phys_lo = 0;
924 reg->size_hi = 0;
925 reg->size_lo = 0;
926
927 for (i = 0; i < PCI_NUM_REGIONS; i++) {
928 if (!d->io_regions[i].size) {
929 continue;
930 }
931
932 reg = &rp->reg[reg_idx++];
933
934 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
935 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
936 reg->phys_hi |= cpu_to_be32(b_ss(1));
72187935
ND
937 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
938 reg->phys_hi |= cpu_to_be32(b_ss(3));
7454c7af
MR
939 } else {
940 reg->phys_hi |= cpu_to_be32(b_ss(2));
941 }
942 reg->phys_mid = 0;
943 reg->phys_lo = 0;
944 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
945 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
946
947 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) {
948 continue;
949 }
950
951 assigned = &rp->assigned[assigned_idx++];
382b6f22 952 assigned->phys_hi = cpu_to_be32(be32_to_cpu(reg->phys_hi) | b_n(1));
7454c7af
MR
953 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32);
954 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr);
955 assigned->size_hi = reg->size_hi;
956 assigned->size_lo = reg->size_lo;
957 }
958
959 rp->reg_len = reg_idx * sizeof(ResourceFields);
960 rp->assigned_len = assigned_idx * sizeof(ResourceFields);
961}
962
2530a1a5
LV
963typedef struct PCIClass PCIClass;
964typedef struct PCISubClass PCISubClass;
965typedef struct PCIIFace PCIIFace;
966
967struct PCIIFace {
968 int iface;
969 const char *name;
970};
971
972struct PCISubClass {
973 int subclass;
974 const char *name;
975 const PCIIFace *iface;
976};
977
978struct PCIClass {
979 const char *name;
980 const PCISubClass *subc;
981};
982
983static const PCISubClass undef_subclass[] = {
984 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
985 { 0xFF, NULL, NULL },
986};
987
988static const PCISubClass mass_subclass[] = {
989 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
990 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
991 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
992 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
993 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
994 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
995 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
996 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
997 { 0xFF, NULL, NULL },
998};
999
1000static const PCISubClass net_subclass[] = {
1001 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
1002 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
1003 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
1004 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
1005 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
1006 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
1007 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
1008 { 0xFF, NULL, NULL },
1009};
1010
1011static const PCISubClass displ_subclass[] = {
1012 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
1013 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
1014 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
1015 { 0xFF, NULL, NULL },
1016};
1017
1018static const PCISubClass media_subclass[] = {
1019 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1020 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1021 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1022 { 0xFF, NULL, NULL },
1023};
1024
1025static const PCISubClass mem_subclass[] = {
1026 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1027 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1028 { 0xFF, NULL, NULL },
1029};
1030
1031static const PCISubClass bridg_subclass[] = {
1032 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1033 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1034 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1035 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1036 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1037 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1038 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1039 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1040 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1041 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1042 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1043 { 0xFF, NULL, NULL },
1044};
1045
1046static const PCISubClass comm_subclass[] = {
1047 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1048 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1049 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1050 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1051 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1052 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1053 { 0xFF, NULL, NULL, },
1054};
1055
1056static const PCIIFace pic_iface[] = {
1057 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1058 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1059 { 0xFF, NULL },
1060};
1061
1062static const PCISubClass sys_subclass[] = {
1063 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1064 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1065 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1066 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1067 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1068 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1069 { 0xFF, NULL, NULL },
1070};
1071
1072static const PCISubClass inp_subclass[] = {
1073 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1074 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1075 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1076 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1077 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1078 { 0xFF, NULL, NULL },
1079};
1080
1081static const PCISubClass dock_subclass[] = {
1082 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1083 { 0xFF, NULL, NULL },
1084};
1085
1086static const PCISubClass cpu_subclass[] = {
1087 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1088 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1089 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1090 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1091 { 0xFF, NULL, NULL },
1092};
1093
1094static const PCIIFace usb_iface[] = {
1095 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1096 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1097 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1098 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1099 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1100 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1101 { 0xFF, NULL },
1102};
1103
1104static const PCISubClass ser_subclass[] = {
1105 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1106 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1107 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1108 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1109 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1110 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1111 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1112 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1113 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1114 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1115 { 0xFF, NULL, NULL },
1116};
1117
1118static const PCISubClass wrl_subclass[] = {
1119 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1120 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1121 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1122 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1123 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1124 { 0xFF, NULL, NULL },
1125};
1126
1127static const PCISubClass sat_subclass[] = {
1128 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1129 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1130 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1131 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1132 { 0xFF, NULL, NULL },
1133};
1134
1135static const PCISubClass crypt_subclass[] = {
1136 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1137 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1138 "entertainment-encryption", NULL },
1139 { 0xFF, NULL, NULL },
1140};
1141
1142static const PCISubClass spc_subclass[] = {
1143 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1144 { PCI_CLASS_SP_PERF, "counter", NULL },
1145 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1146 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1147 { 0xFF, NULL, NULL },
1148};
1149
1150static const PCIClass pci_classes[] = {
1151 { "legacy-device", undef_subclass },
1152 { "mass-storage", mass_subclass },
1153 { "network", net_subclass },
1154 { "display", displ_subclass, },
1155 { "multimedia-device", media_subclass },
1156 { "memory-controller", mem_subclass },
1157 { "unknown-bridge", bridg_subclass },
1158 { "communication-controller", comm_subclass},
1159 { "system-peripheral", sys_subclass },
1160 { "input-controller", inp_subclass },
1161 { "docking-station", dock_subclass },
1162 { "cpu", cpu_subclass },
1163 { "serial-bus", ser_subclass },
1164 { "wireless-controller", wrl_subclass },
1165 { "intelligent-io", NULL },
1166 { "satellite-device", sat_subclass },
1167 { "encryption", crypt_subclass },
1168 { "data-processing-controller", spc_subclass },
1169};
1170
4782a8bb
DG
1171static const char *dt_name_from_class(uint8_t class, uint8_t subclass,
1172 uint8_t iface)
2530a1a5
LV
1173{
1174 const PCIClass *pclass;
1175 const PCISubClass *psubclass;
1176 const PCIIFace *piface;
1177 const char *name;
1178
1179 if (class >= ARRAY_SIZE(pci_classes)) {
1180 return "pci";
1181 }
1182
1183 pclass = pci_classes + class;
1184 name = pclass->name;
1185
1186 if (pclass->subc == NULL) {
1187 return name;
1188 }
1189
1190 psubclass = pclass->subc;
1191 while ((psubclass->subclass & 0xff) != 0xff) {
1192 if ((psubclass->subclass & 0xff) == subclass) {
1193 name = psubclass->name;
1194 break;
1195 }
1196 psubclass++;
1197 }
1198
1199 piface = psubclass->iface;
1200 if (piface == NULL) {
1201 return name;
1202 }
1203 while ((piface->iface & 0xff) != 0xff) {
1204 if ((piface->iface & 0xff) == iface) {
1205 name = piface->name;
1206 break;
1207 }
1208 piface++;
1209 }
1210
1211 return name;
1212}
1213
a1ec25b2
DG
1214/*
1215 * DRC helper functions
1216 */
1217
1218static uint32_t drc_id_from_devfn(SpaprPhbState *phb,
05929a6c 1219 uint8_t chassis, int32_t devfn)
2530a1a5 1220{
05929a6c 1221 return (phb->index << 16) | (chassis << 8) | devfn;
a1ec25b2 1222}
2530a1a5 1223
a1ec25b2 1224static SpaprDrc *drc_from_devfn(SpaprPhbState *phb,
05929a6c 1225 uint8_t chassis, int32_t devfn)
a1ec25b2
DG
1226{
1227 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
05929a6c
DG
1228 drc_id_from_devfn(phb, chassis, devfn));
1229}
2530a1a5 1230
05929a6c
DG
1231static uint8_t chassis_from_bus(PCIBus *bus, Error **errp)
1232{
1233 if (pci_bus_is_root(bus)) {
1234 return 0;
1235 } else {
1236 PCIDevice *bridge = pci_bridge_get_device(bus);
1237
1238 return object_property_get_uint(OBJECT(bridge), "chassis_nr", errp);
1239 }
a1ec25b2
DG
1240}
1241
1242static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev)
1243{
05929a6c
DG
1244 Error *local_err = NULL;
1245 uint8_t chassis = chassis_from_bus(pci_get_bus(dev), &local_err);
1246
1247 if (local_err) {
1248 error_report_err(local_err);
1249 return NULL;
1250 }
1251
1252 return drc_from_devfn(phb, chassis, dev->devfn);
a1ec25b2
DG
1253}
1254
14e71490 1255static void add_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp)
a1ec25b2 1256{
14e71490 1257 Object *owner;
a1ec25b2 1258 int i;
14e71490
DG
1259 uint8_t chassis;
1260 Error *local_err = NULL;
a1ec25b2
DG
1261
1262 if (!phb->dr_enabled) {
1263 return;
1264 }
1265
14e71490
DG
1266 chassis = chassis_from_bus(bus, &local_err);
1267 if (local_err) {
1268 error_propagate(errp, local_err);
1269 return;
1270 }
1271
1272 if (pci_bus_is_root(bus)) {
1273 owner = OBJECT(phb);
2530a1a5 1274 } else {
14e71490
DG
1275 owner = OBJECT(pci_bridge_get_device(bus));
1276 }
1277
a1ec25b2 1278 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) {
14e71490
DG
1279 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI,
1280 drc_id_from_devfn(phb, chassis, i));
a1ec25b2
DG
1281 }
1282}
1283
14e71490 1284static void remove_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp)
a1ec25b2
DG
1285{
1286 int i;
14e71490
DG
1287 uint8_t chassis;
1288 Error *local_err = NULL;
a1ec25b2
DG
1289
1290 if (!phb->dr_enabled) {
1291 return;
1292 }
1293
14e71490
DG
1294 chassis = chassis_from_bus(bus, &local_err);
1295 if (local_err) {
1296 error_propagate(errp, local_err);
1297 return;
1298 }
1299
a1ec25b2 1300 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) {
14e71490 1301 SpaprDrc *drc = drc_from_devfn(phb, chassis, i);
a1ec25b2
DG
1302
1303 if (drc) {
1304 object_unparent(OBJECT(drc));
1305 }
2530a1a5
LV
1306 }
1307}
1308
466e8831
DG
1309typedef struct PciWalkFdt {
1310 void *fdt;
1311 int offset;
1312 SpaprPhbState *sphb;
1313 int err;
1314} PciWalkFdt;
1315
1316static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1317 void *fdt, int parent_offset);
1318
1319static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev,
1320 void *opaque)
1321{
1322 PciWalkFdt *p = opaque;
1323 int err;
1324
1325 if (p->err) {
1326 /* Something's already broken, don't keep going */
1327 return;
1328 }
1329
1330 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset);
1331 if (err < 0) {
1332 p->err = err;
1333 }
1334}
1335
1336/* Augment PCI device node with bridge specific information */
1337static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus,
1338 void *fdt, int offset)
1339{
7e10b57d 1340 Object *owner;
466e8831
DG
1341 PciWalkFdt cbinfo = {
1342 .fdt = fdt,
1343 .offset = offset,
1344 .sphb = sphb,
1345 .err = 0,
1346 };
14e71490 1347 int ret;
466e8831
DG
1348
1349 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1350 RESOURCE_CELLS_ADDRESS));
1351 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1352 RESOURCE_CELLS_SIZE));
1353
740a1931
PMD
1354 assert(bus);
1355 pci_for_each_device_reverse(bus, pci_bus_num(bus),
1356 spapr_dt_pci_device_cb, &cbinfo);
1357 if (cbinfo.err) {
1358 return cbinfo.err;
466e8831
DG
1359 }
1360
7e10b57d
GK
1361 if (pci_bus_is_root(bus)) {
1362 owner = OBJECT(sphb);
1363 } else {
1364 owner = OBJECT(pci_bridge_get_device(bus));
1365 }
1366
1367 ret = spapr_dt_drc(fdt, offset, owner,
14e71490
DG
1368 SPAPR_DR_CONNECTOR_TYPE_PCI);
1369 if (ret) {
1370 return ret;
1371 }
1372
466e8831
DG
1373 return offset;
1374}
e634b89c 1375
9d2134d8
DG
1376/* create OF node for pci device and required OF DT properties */
1377static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1378 void *fdt, int parent_offset)
7454c7af 1379{
9d2134d8
DG
1380 int offset;
1381 const gchar *basename;
1382 gchar *nodename;
1383 int slot = PCI_SLOT(dev->devfn);
1384 int func = PCI_FUNC(dev->devfn);
466e8831 1385 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
7454c7af 1386 ResourceProps rp;
a1ec25b2 1387 SpaprDrc *drc = drc_from_dev(sphb, dev);
9d2134d8
DG
1388 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2);
1389 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2);
1390 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1);
2530a1a5 1391 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
9d2134d8
DG
1392 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1);
1393 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2);
1394 uint32_t subsystem_vendor_id =
1395 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
1396 uint32_t cache_line_size =
1397 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1);
1398 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1399 gchar *loc_code;
7454c7af 1400
9d2134d8
DG
1401 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1402 ccode & 0xff);
7454c7af 1403
9d2134d8
DG
1404 if (func != 0) {
1405 nodename = g_strdup_printf("%s@%x,%x", basename, slot, func);
1406 } else {
1407 nodename = g_strdup_printf("%s@%x", basename, slot);
7454c7af
MR
1408 }
1409
9d2134d8
DG
1410 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename));
1411
1412 g_free(nodename);
1413
7454c7af 1414 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
9d2134d8
DG
1415 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id));
1416 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id));
1417 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id));
7454c7af 1418
2530a1a5 1419 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
9d2134d8
DG
1420 if (irq_pin) {
1421 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin));
7454c7af
MR
1422 }
1423
9d2134d8
DG
1424 if (subsystem_id) {
1425 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id));
7454c7af
MR
1426 }
1427
9d2134d8 1428 if (subsystem_vendor_id) {
7454c7af 1429 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
9d2134d8 1430 subsystem_vendor_id));
7454c7af
MR
1431 }
1432
9d2134d8
DG
1433 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size));
1434
7454c7af
MR
1435
1436 /* the following fdt cells are masked off the pci status register */
7454c7af
MR
1437 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1438 PCI_STATUS_DEVSEL_MASK & pci_status));
1439
1440 if (pci_status & PCI_STATUS_FAST_BACK) {
1441 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1442 }
1443 if (pci_status & PCI_STATUS_66MHZ) {
1444 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1445 }
1446 if (pci_status & PCI_STATUS_UDF) {
1447 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1448 }
1449
9d2134d8
DG
1450 loc_code = spapr_phb_get_loc_code(sphb, dev);
1451 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code));
1452 g_free(loc_code);
16b0ea1d 1453
a1ec25b2
DG
1454 if (drc) {
1455 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index",
1456 spapr_drc_index(drc)));
e634b89c 1457 }
7454c7af 1458
9cbe305b 1459 if (msi_present(dev)) {
9d2134d8 1460 uint32_t max_msi = msi_nr_vectors_allocated(dev);
9cbe305b
GK
1461 if (max_msi) {
1462 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1463 }
a8ad731a 1464 }
9cbe305b 1465 if (msix_present(dev)) {
9d2134d8 1466 uint32_t max_msix = dev->msix_entries_nr;
9cbe305b
GK
1467 if (max_msix) {
1468 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1469 }
a8ad731a 1470 }
7454c7af
MR
1471
1472 populate_resource_props(dev, &rp);
1473 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1474 _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
1475 (uint8_t *)rp.assigned, rp.assigned_len));
1476
82516263 1477 if (sphb->pcie_ecs && pci_is_express(dev)) {
bb998645
DG
1478 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1479 }
ec132efa
AK
1480
1481 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb);
7454c7af 1482
466e8831
DG
1483 if (!pc->is_bridge) {
1484 /* Properties only for non-bridges */
1485 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1);
1486 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1);
1487 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant));
1488 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency));
1489 return offset;
1490 } else {
1491 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
e634b89c 1492
466e8831
DG
1493 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset);
1494 }
7454c7af
MR
1495}
1496
31834723
DHB
1497/* Callback to be called during DRC release. */
1498void spapr_phb_remove_pci_device_cb(DeviceState *dev)
7454c7af 1499{
27c1da51
DH
1500 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
1501
1502 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
07578b0a 1503 object_unparent(OBJECT(dev));
7454c7af
MR
1504}
1505
ce2918cb 1506int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
46fd0299
GK
1507 void *fdt, int *fdt_start_offset, Error **errp)
1508{
1509 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev);
ce2918cb 1510 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler);
46fd0299
GK
1511 PCIDevice *pdev = PCI_DEVICE(drc->dev);
1512
9d2134d8 1513 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0);
46fd0299
GK
1514 return 0;
1515}
1516
14e71490
DG
1517static void spapr_pci_bridge_plug(SpaprPhbState *phb,
1518 PCIBridge *bridge,
1519 Error **errp)
1520{
1521 Error *local_err = NULL;
1522 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1523
1524 add_drcs(phb, bus, &local_err);
1525 if (local_err) {
1526 error_propagate(errp, local_err);
1527 return;
1528 }
1529}
1530
3340e5c4
DG
1531static void spapr_pci_plug(HotplugHandler *plug_handler,
1532 DeviceState *plugged_dev, Error **errp)
7454c7af 1533{
ce2918cb 1534 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
7454c7af 1535 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
14e71490 1536 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
a1ec25b2 1537 SpaprDrc *drc = drc_from_dev(phb, pdev);
7454c7af 1538 Error *local_err = NULL;
788d2599
MR
1539 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1540 uint32_t slotnr = PCI_SLOT(pdev->devfn);
7454c7af
MR
1541
1542 /* if DR is disabled we don't need to do anything in the case of
1543 * hotplug or coldplug callbacks
1544 */
1545 if (!phb->dr_enabled) {
1546 /* if this is a hotplug operation initiated by the user
1547 * we need to let them know it's not enabled
1548 */
1549 if (plugged_dev->hotplugged) {
6304fd27 1550 error_setg(&local_err, QERR_BUS_NO_HOTPLUG,
c6bd8c70 1551 object_get_typename(OBJECT(phb)));
7454c7af 1552 }
6304fd27 1553 goto out;
7454c7af
MR
1554 }
1555
1556 g_assert(drc);
1557
14e71490
DG
1558 if (pc->is_bridge) {
1559 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev), &local_err);
1560 if (local_err) {
1561 error_propagate(errp, local_err);
1562 return;
1563 }
1564 }
1565
788d2599
MR
1566 /* Following the QEMU convention used for PCIe multifunction
1567 * hotplug, we do not allow functions to be hotplugged to a
1568 * slot that already has function 0 present
1569 */
1570 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1571 PCI_FUNC(pdev->devfn) != 0) {
6304fd27 1572 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s,"
788d2599
MR
1573 " additional functions can no longer be exposed to guest.",
1574 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
6304fd27
DG
1575 goto out;
1576 }
1577
09d876ce 1578 spapr_drc_attach(drc, DEVICE(pdev), &local_err);
7454c7af 1579 if (local_err) {
6304fd27 1580 goto out;
7454c7af 1581 }
788d2599
MR
1582
1583 /* If this is function 0, signal hotplug for all the device functions.
1584 * Otherwise defer sending the hotplug event.
1585 */
94fd9cba
LV
1586 if (!spapr_drc_hotplugged(plugged_dev)) {
1587 spapr_drc_reset(drc);
1588 } else if (PCI_FUNC(pdev->devfn) == 0) {
788d2599 1589 int i;
05929a6c
DG
1590 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err);
1591
1592 if (local_err) {
1593 error_propagate(errp, local_err);
1594 return;
1595 }
788d2599
MR
1596
1597 for (i = 0; i < 8; i++) {
ce2918cb
DG
1598 SpaprDrc *func_drc;
1599 SpaprDrcClass *func_drck;
1600 SpaprDREntitySense state;
788d2599 1601
05929a6c 1602 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
788d2599 1603 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
f224d35b 1604 state = func_drck->dr_entity_sense(func_drc);
788d2599
MR
1605
1606 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1607 spapr_hotplug_req_add_by_index(func_drc);
1608 }
1609 }
c5bc152b 1610 }
6304fd27
DG
1611
1612out:
e366d181 1613 error_propagate(errp, local_err);
7454c7af
MR
1614}
1615
14e71490
DG
1616static void spapr_pci_bridge_unplug(SpaprPhbState *phb,
1617 PCIBridge *bridge,
1618 Error **errp)
1619{
1620 Error *local_err = NULL;
1621 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1622
1623 remove_drcs(phb, bus, &local_err);
1624 if (local_err) {
1625 error_propagate(errp, local_err);
1626 return;
1627 }
1628}
1629
27c1da51
DH
1630static void spapr_pci_unplug(HotplugHandler *plug_handler,
1631 DeviceState *plugged_dev, Error **errp)
1632{
14e71490
DG
1633 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1634 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1635
27c1da51
DH
1636 /* some version guests do not wait for completion of a device
1637 * cleanup (generally done asynchronously by the kernel) before
1638 * signaling to QEMU that the device is safe, but instead sleep
1639 * for some 'safe' period of time. unfortunately on a busy host
1640 * this sleep isn't guaranteed to be long enough, resulting in
1641 * bad things like IRQ lines being left asserted during final
1642 * device removal. to deal with this we call reset just prior
1643 * to finalizing the device, which will put the device back into
1644 * an 'idle' state, as the device cleanup code expects.
1645 */
1646 pci_device_reset(PCI_DEVICE(plugged_dev));
14e71490
DG
1647
1648 if (pc->is_bridge) {
1649 Error *local_err = NULL;
1650 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev), &local_err);
1651 if (local_err) {
1652 error_propagate(errp, local_err);
1653 }
1654 return;
1655 }
1656
07578b0a 1657 object_property_set_bool(OBJECT(plugged_dev), false, "realized", NULL);
27c1da51
DH
1658}
1659
3340e5c4
DG
1660static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1661 DeviceState *plugged_dev, Error **errp)
7454c7af 1662{
ce2918cb 1663 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
7454c7af 1664 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
a1ec25b2 1665 SpaprDrc *drc = drc_from_dev(phb, pdev);
7454c7af
MR
1666
1667 if (!phb->dr_enabled) {
c6bd8c70
MA
1668 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1669 object_get_typename(OBJECT(phb)));
7454c7af
MR
1670 return;
1671 }
1672
1673 g_assert(drc);
3340e5c4 1674 g_assert(drc->dev == plugged_dev);
7454c7af 1675
f1c52354 1676 if (!spapr_drc_unplug_requested(drc)) {
14e71490 1677 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
788d2599 1678 uint32_t slotnr = PCI_SLOT(pdev->devfn);
ce2918cb
DG
1679 SpaprDrc *func_drc;
1680 SpaprDrcClass *func_drck;
1681 SpaprDREntitySense state;
788d2599 1682 int i;
05929a6c
DG
1683 Error *local_err = NULL;
1684 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err);
1685
1686 if (local_err) {
1687 error_propagate(errp, local_err);
1688 return;
1689 }
788d2599 1690
14e71490
DG
1691 if (pc->is_bridge) {
1692 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported");
1693 }
788d2599
MR
1694
1695 /* ensure any other present functions are pending unplug */
1696 if (PCI_FUNC(pdev->devfn) == 0) {
1697 for (i = 1; i < 8; i++) {
05929a6c 1698 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
788d2599 1699 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
f224d35b 1700 state = func_drck->dr_entity_sense(func_drc);
788d2599 1701 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
f1c52354 1702 && !spapr_drc_unplug_requested(func_drc)) {
788d2599
MR
1703 error_setg(errp,
1704 "PCI: slot %d, function %d still present. "
1705 "Must unplug all non-0 functions first.",
1706 slotnr, i);
1707 return;
1708 }
1709 }
1710 }
1711
a8dc47fd 1712 spapr_drc_detach(drc);
788d2599
MR
1713
1714 /* if this isn't func 0, defer unplug event. otherwise signal removal
1715 * for all present functions
1716 */
1717 if (PCI_FUNC(pdev->devfn) == 0) {
1718 for (i = 7; i >= 0; i--) {
05929a6c 1719 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
788d2599 1720 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
f224d35b 1721 state = func_drck->dr_entity_sense(func_drc);
788d2599
MR
1722 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1723 spapr_hotplug_req_remove_by_index(func_drc);
1724 }
1725 }
1726 }
7454c7af
MR
1727 }
1728}
1729
ef28b98d
GK
1730static void spapr_phb_finalizefn(Object *obj)
1731{
ce2918cb 1732 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj);
ef28b98d
GK
1733
1734 g_free(sphb->dtbusname);
1735 sphb->dtbusname = NULL;
1736}
1737
1738static void spapr_phb_unrealize(DeviceState *dev, Error **errp)
1739{
ce2918cb 1740 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
ef28b98d
GK
1741 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1742 PCIHostState *phb = PCI_HOST_BRIDGE(s);
ce2918cb
DG
1743 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb);
1744 SpaprTceTable *tcet;
ef28b98d
GK
1745 int i;
1746 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
14e71490 1747 Error *local_err = NULL;
ef28b98d 1748
ec132efa
AK
1749 spapr_phb_nvgpu_free(sphb);
1750
ef28b98d
GK
1751 if (sphb->msi) {
1752 g_hash_table_unref(sphb->msi);
1753 sphb->msi = NULL;
1754 }
1755
1756 /*
1757 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1758 * via PHB's unrealize->object_finalize
1759 */
1760 for (i = windows_supported - 1; i >= 0; i--) {
1761 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1762 if (tcet) {
1763 memory_region_del_subregion(&sphb->iommu_root,
1764 spapr_tce_get_iommu(tcet));
1765 }
1766 }
1767
14e71490
DG
1768 remove_drcs(sphb, phb->bus, &local_err);
1769 if (local_err) {
1770 error_propagate(errp, local_err);
1771 return;
ef28b98d
GK
1772 }
1773
1774 for (i = PCI_NUM_PINS - 1; i >= 0; i--) {
1775 if (sphb->lsi_table[i].irq) {
1776 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1);
1777 sphb->lsi_table[i].irq = 0;
1778 }
1779 }
1780
1781 QLIST_REMOVE(sphb, list);
1782
1783 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow);
1784
a2166410
GK
1785 /*
1786 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have
1787 * unmapped all sections. Remove the listeners now, before destroying the
1788 * address space.
1789 */
1790 address_space_remove_listeners(&sphb->iommu_as);
ef28b98d
GK
1791 address_space_destroy(&sphb->iommu_as);
1792
1793 qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort);
1794 pci_unregister_root_bus(phb->bus);
1795
1796 memory_region_del_subregion(get_system_memory(), &sphb->iowindow);
1797 if (sphb->mem64_win_pciaddr != (hwaddr)-1) {
1798 memory_region_del_subregion(get_system_memory(), &sphb->mem64window);
1799 }
1800 memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
1801}
1802
078eb6b0
GK
1803static void spapr_phb_destroy_msi(gpointer opaque)
1804{
1805 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1806 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1807 spapr_pci_msi *msi = opaque;
1808
1809 if (!smc->legacy_irq_allocation) {
1810 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
1811 }
1812 spapr_irq_free(spapr, msi->first_irq, msi->num);
1813 g_free(msi);
1814}
1815
c6ba42f6 1816static void spapr_phb_realize(DeviceState *dev, Error **errp)
3384f95c 1817{
f7d6bfcd
GK
1818 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1819 * tries to add a sPAPR PHB to a non-pseries machine.
1820 */
ce2918cb
DG
1821 SpaprMachineState *spapr =
1822 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
f7d6bfcd 1823 TYPE_SPAPR_MACHINE);
ce2918cb 1824 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL;
c6ba42f6 1825 SysBusDevice *s = SYS_BUS_DEVICE(dev);
ce2918cb 1826 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
8558d942 1827 PCIHostState *phb = PCI_HOST_BRIDGE(s);
298a9710
DG
1828 char *namebuf;
1829 int i;
3384f95c 1830 PCIBus *bus;
8c46f7ec 1831 uint64_t msi_window_size = 4096;
ce2918cb 1832 SpaprTceTable *tcet;
ef28b98d 1833 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
14e71490 1834 Error *local_err = NULL;
3384f95c 1835
f7d6bfcd
GK
1836 if (!spapr) {
1837 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1838 return;
1839 }
1840
bb2bdd81 1841 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
caae58cb 1842
daa23699 1843 if (sphb->mem64_win_size != 0) {
daa23699
DG
1844 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1845 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1846 " (max 2 GiB)", sphb->mem_win_size);
1847 return;
1848 }
1849
30b3bc5a
GK
1850 /* 64-bit window defaults to identity mapping */
1851 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
daa23699
DG
1852 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1853 /*
1854 * For compatibility with old configuration, if no 64-bit MMIO
1855 * window is specified, but the ordinary (32-bit) memory
1856 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1857 * window, with a 64-bit MMIO window following on immediately
1858 * afterwards
1859 */
1860 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1861 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1862 sphb->mem64_win_pciaddr =
1863 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1864 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1865 }
1866
46c5874e 1867 if (spapr_pci_find_phb(spapr, sphb->buid)) {
70282930
GK
1868 SpaprPhbState *s;
1869
1870 error_setg(errp, "PCI host bridges must have unique indexes");
1871 error_append_hint(errp, "The following indexes are already in use:");
1872 QLIST_FOREACH(s, &spapr->phbs, list) {
1873 error_append_hint(errp, " %d", s->index);
1874 }
1875 error_append_hint(errp, "\nTry another value for the index property\n");
c6ba42f6 1876 return;
caae58cb
DG
1877 }
1878
4bcfa56c
MR
1879 if (sphb->numa_node != -1 &&
1880 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
1881 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1882 return;
1883 }
1884
8c9f64df 1885 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
caae58cb 1886
298a9710 1887 /* Initialize memory regions */
1d36da76 1888 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
92b8e39c 1889 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1d36da76 1890 g_free(namebuf);
3384f95c 1891
1d36da76 1892 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
daa23699 1893 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
40c5dce9 1894 namebuf, &sphb->memspace,
8c9f64df 1895 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1d36da76 1896 g_free(namebuf);
8c9f64df 1897 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
daa23699
DG
1898 &sphb->mem32window);
1899
30b3bc5a 1900 if (sphb->mem64_win_size != 0) {
96dbc9af
GK
1901 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1902 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1903 namebuf, &sphb->memspace,
1904 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1905 g_free(namebuf);
1906
30b3bc5a
GK
1907 memory_region_add_subregion(get_system_memory(),
1908 sphb->mem64_win_addr,
1909 &sphb->mem64window);
96dbc9af 1910 }
3384f95c 1911
fabe9ee1 1912 /* Initialize IO regions */
1d36da76 1913 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
40c5dce9
PB
1914 memory_region_init(&sphb->iospace, OBJECT(sphb),
1915 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1d36da76 1916 g_free(namebuf);
3384f95c 1917
1d36da76 1918 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
66aab867 1919 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
fabe9ee1 1920 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1d36da76 1921 g_free(namebuf);
8c9f64df 1922 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
a3cfa18e 1923 &sphb->iowindow);
1b8601b0 1924
4560116e 1925 bus = pci_register_root_bus(dev, NULL,
e8ec4adf 1926 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb,
1115ff6d 1927 &sphb->memspace, &sphb->iospace,
5cf0d326 1928 PCI_DEVFN(0, 0), PCI_NUM_PINS,
2f57db8a
DG
1929 TYPE_PCI_BUS);
1930
1931 /*
1932 * Despite resembling a vanilla PCI bus in most ways, the PAPR
1933 * para-virtualized PCI bus *does* permit PCI-E extended config
1934 * space access
1935 */
1936 if (sphb->pcie_ecs) {
1937 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1938 }
8c9f64df 1939 phb->bus = bus;
94d1cc5f 1940 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL);
298a9710 1941
cca7fad5
AK
1942 /*
1943 * Initialize PHB address space.
1944 * By default there will be at least one subregion for default
1945 * 32bit DMA window.
1946 * Later the guest might want to create another DMA window
1947 * which will become another memory subregion.
1948 */
1d36da76 1949 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
cca7fad5
AK
1950 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1951 namebuf, UINT64_MAX);
1d36da76 1952 g_free(namebuf);
cca7fad5
AK
1953 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1954 sphb->dtbusname);
1955
8c46f7ec
GK
1956 /*
1957 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1958 * we need to allocate some memory to catch those writes coming
1959 * from msi_notify()/msix_notify().
1960 * As MSIMessage:addr is going to be the same and MSIMessage:data
1961 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1962 * be used.
1963 *
1964 * For KVM we want to ensure that this memory is a full page so that
1965 * our memory slot is of page size granularity.
1966 */
8c46f7ec
GK
1967 if (kvm_enabled()) {
1968 msi_window_size = getpagesize();
1969 }
8c46f7ec 1970
dba95ebb 1971 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
8c46f7ec
GK
1972 "msi", msi_window_size);
1973 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1974 &sphb->msiwindow);
1975
e00387d5 1976 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
edded454 1977
5cc7a967
AK
1978 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1979
8c9f64df 1980 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
298a9710
DG
1981
1982 /* Initialize the LSI table */
7fb0bd34 1983 for (i = 0; i < PCI_NUM_PINS; i++) {
82cffa2e 1984 uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
298a9710 1985
2c88b098 1986 if (smc->legacy_irq_allocation) {
82cffa2e
CLG
1987 irq = spapr_irq_findone(spapr, &local_err);
1988 if (local_err) {
4b576648
MA
1989 error_propagate_prepend(errp, local_err,
1990 "can't allocate LSIs: ");
ef28b98d
GK
1991 /*
1992 * Older machines will never support PHB hotplug, ie, this is an
1993 * init only path and QEMU will terminate. No need to rollback.
1994 */
82cffa2e
CLG
1995 return;
1996 }
4fe75a8c
CLG
1997 }
1998
1999 spapr_irq_claim(spapr, irq, true, &local_err);
a005b3ef 2000 if (local_err) {
4b576648 2001 error_propagate_prepend(errp, local_err, "can't allocate LSIs: ");
ef28b98d 2002 goto unrealize;
298a9710
DG
2003 }
2004
8c9f64df 2005 sphb->lsi_table[i].irq = irq;
298a9710 2006 }
da6ccee4 2007
62083979 2008 /* allocate connectors for child PCI devices */
14e71490
DG
2009 add_drcs(sphb, phb->bus, &local_err);
2010 if (local_err) {
2011 error_propagate(errp, local_err);
2012 goto unrealize;
62083979
MR
2013 }
2014
ae4de14c
AK
2015 /* DMA setup */
2016 for (i = 0; i < windows_supported; ++i) {
2017 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
2018 if (!tcet) {
2019 error_setg(errp, "Creating window#%d failed for %s",
2020 i, sphb->dtbusname);
ef28b98d 2021 goto unrealize;
ae4de14c 2022 }
5c3d70e9
GK
2023 memory_region_add_subregion(&sphb->iommu_root, 0,
2024 spapr_tce_get_iommu(tcet));
da6ccee4 2025 }
cca7fad5 2026
078eb6b0
GK
2027 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free,
2028 spapr_phb_destroy_msi);
ef28b98d
GK
2029 return;
2030
2031unrealize:
2032 spapr_phb_unrealize(dev, NULL);
298a9710
DG
2033}
2034
e28c16f6 2035static int spapr_phb_children_reset(Object *child, void *opaque)
eddeed26 2036{
e28c16f6
AK
2037 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
2038
2039 if (dev) {
2040 device_reset(dev);
2041 }
eddeed26 2042
e28c16f6
AK
2043 return 0;
2044}
2045
ce2918cb 2046void spapr_phb_dma_reset(SpaprPhbState *sphb)
e28c16f6 2047{
ae4de14c 2048 int i;
ce2918cb 2049 SpaprTceTable *tcet;
ae4de14c
AK
2050
2051 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
2052 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
acf1b6dd 2053
ae4de14c
AK
2054 if (tcet && tcet->nb_table) {
2055 spapr_tce_table_disable(tcet);
2056 }
acf1b6dd
AK
2057 }
2058
2059 /* Register default 32bit DMA window */
ae4de14c 2060 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
acf1b6dd
AK
2061 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
2062 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
b3162f22
AK
2063}
2064
2065static void spapr_phb_reset(DeviceState *qdev)
2066{
ce2918cb 2067 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
ec132efa 2068 Error *errp = NULL;
b3162f22
AK
2069
2070 spapr_phb_dma_reset(sphb);
ec132efa
AK
2071 spapr_phb_nvgpu_free(sphb);
2072 spapr_phb_nvgpu_setup(sphb, &errp);
2073 if (errp) {
2074 error_report_err(errp);
2075 }
acf1b6dd 2076
eddeed26 2077 /* Reset the IOMMU state */
e28c16f6 2078 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
fbb4e983
DG
2079
2080 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
2081 spapr_phb_vfio_reset(qdev);
2082 }
ea52074d
GK
2083
2084 g_hash_table_remove_all(sphb->msi);
eddeed26
DG
2085}
2086
298a9710 2087static Property spapr_phb_properties[] = {
ce2918cb
DG
2088 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1),
2089 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size,
357d1e3b 2090 SPAPR_PCI_MEM32_WIN_SIZE),
ce2918cb 2091 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size,
357d1e3b 2092 SPAPR_PCI_MEM64_WIN_SIZE),
ce2918cb 2093 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size,
c7bcc85d 2094 SPAPR_PCI_IO_WIN_SIZE),
ce2918cb 2095 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled,
7619c7b0 2096 true),
f93caaac 2097 /* Default DMA window is 0..1GB */
ce2918cb
DG
2098 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0),
2099 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000),
2100 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr,
ae4de14c 2101 0x800000000000000ULL),
ce2918cb
DG
2102 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true),
2103 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask,
d15d4ad6
DG
2104 (1ULL << 12) | (1ULL << 16)
2105 | (1ULL << 21) | (1ULL << 24)),
ce2918cb
DG
2106 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1),
2107 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState,
5c4537bd 2108 pre_2_8_migration, false),
ce2918cb 2109 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState,
82516263 2110 pcie_ecs, true),
ec132efa
AK
2111 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0),
2112 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0),
298a9710
DG
2113 DEFINE_PROP_END_OF_LIST(),
2114};
2115
1112cf94
DG
2116static const VMStateDescription vmstate_spapr_pci_lsi = {
2117 .name = "spapr_pci/lsi",
2118 .version_id = 1,
2119 .minimum_version_id = 1,
3aff6c2f 2120 .fields = (VMStateField[]) {
d2164ad3 2121 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL),
1112cf94
DG
2122
2123 VMSTATE_END_OF_LIST()
2124 },
2125};
2126
2127static const VMStateDescription vmstate_spapr_pci_msi = {
9a321e92 2128 .name = "spapr_pci/msi",
1112cf94
DG
2129 .version_id = 1,
2130 .minimum_version_id = 1,
9a321e92
AK
2131 .fields = (VMStateField []) {
2132 VMSTATE_UINT32(key, spapr_pci_msi_mig),
2133 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
2134 VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
1112cf94
DG
2135 VMSTATE_END_OF_LIST()
2136 },
2137};
2138
44b1ff31 2139static int spapr_pci_pre_save(void *opaque)
9a321e92 2140{
ce2918cb 2141 SpaprPhbState *sphb = opaque;
708414f0
MA
2142 GHashTableIter iter;
2143 gpointer key, value;
2144 int i;
9a321e92 2145
5c4537bd
DG
2146 if (sphb->pre_2_8_migration) {
2147 sphb->mig_liobn = sphb->dma_liobn[0];
2148 sphb->mig_mem_win_addr = sphb->mem_win_addr;
2149 sphb->mig_mem_win_size = sphb->mem_win_size;
2150 sphb->mig_io_win_addr = sphb->io_win_addr;
2151 sphb->mig_io_win_size = sphb->io_win_size;
2152
2153 if ((sphb->mem64_win_size != 0)
2154 && (sphb->mem64_win_addr
2155 == (sphb->mem_win_addr + sphb->mem_win_size))) {
2156 sphb->mig_mem_win_size += sphb->mem64_win_size;
2157 }
2158 }
e806b4db
LV
2159
2160 g_free(sphb->msi_devs);
2161 sphb->msi_devs = NULL;
2162 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
2163 if (!sphb->msi_devs_num) {
44b1ff31 2164 return 0;
e806b4db 2165 }
4fc4c6a5 2166 sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num);
e806b4db
LV
2167
2168 g_hash_table_iter_init(&iter, sphb->msi);
2169 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
2170 sphb->msi_devs[i].key = *(uint32_t *) key;
2171 sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
2172 }
44b1ff31
DDAG
2173
2174 return 0;
9a321e92
AK
2175}
2176
2177static int spapr_pci_post_load(void *opaque, int version_id)
2178{
ce2918cb 2179 SpaprPhbState *sphb = opaque;
9a321e92
AK
2180 gpointer key, value;
2181 int i;
2182
2183 for (i = 0; i < sphb->msi_devs_num; ++i) {
2184 key = g_memdup(&sphb->msi_devs[i].key,
2185 sizeof(sphb->msi_devs[i].key));
2186 value = g_memdup(&sphb->msi_devs[i].value,
2187 sizeof(sphb->msi_devs[i].value));
2188 g_hash_table_insert(sphb->msi, key, value);
2189 }
012aef07
MA
2190 g_free(sphb->msi_devs);
2191 sphb->msi_devs = NULL;
9a321e92
AK
2192 sphb->msi_devs_num = 0;
2193
2194 return 0;
2195}
2196
5c4537bd
DG
2197static bool pre_2_8_migration(void *opaque, int version_id)
2198{
ce2918cb 2199 SpaprPhbState *sphb = opaque;
5c4537bd
DG
2200
2201 return sphb->pre_2_8_migration;
2202}
2203
1112cf94
DG
2204static const VMStateDescription vmstate_spapr_pci = {
2205 .name = "spapr_pci",
5a78b821 2206 .version_id = 2,
9a321e92
AK
2207 .minimum_version_id = 2,
2208 .pre_save = spapr_pci_pre_save,
2209 .post_load = spapr_pci_post_load,
3aff6c2f 2210 .fields = (VMStateField[]) {
ce2918cb
DG
2211 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL),
2212 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration),
2213 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration),
2214 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration),
2215 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration),
2216 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration),
2217 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
1112cf94 2218 vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
ce2918cb
DG
2219 VMSTATE_INT32(msi_devs_num, SpaprPhbState),
2220 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0,
9a321e92 2221 vmstate_spapr_pci_msi, spapr_pci_msi_mig),
1112cf94
DG
2222 VMSTATE_END_OF_LIST()
2223 },
2224};
2225
568f0690
DG
2226static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
2227 PCIBus *rootbus)
2228{
ce2918cb 2229 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
568f0690
DG
2230
2231 return sphb->dtbusname;
2232}
2233
298a9710
DG
2234static void spapr_phb_class_init(ObjectClass *klass, void *data)
2235{
568f0690 2236 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
298a9710 2237 DeviceClass *dc = DEVICE_CLASS(klass);
7454c7af 2238 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
298a9710 2239
568f0690 2240 hc->root_bus_path = spapr_phb_root_bus_path;
c6ba42f6 2241 dc->realize = spapr_phb_realize;
ef28b98d 2242 dc->unrealize = spapr_phb_unrealize;
298a9710 2243 dc->props = spapr_phb_properties;
eddeed26 2244 dc->reset = spapr_phb_reset;
1112cf94 2245 dc->vmsd = &vmstate_spapr_pci;
e4f4fb1e
EH
2246 /* Supported by TYPE_SPAPR_MACHINE */
2247 dc->user_creatable = true;
09aa9a52 2248 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
3340e5c4 2249 hp->plug = spapr_pci_plug;
27c1da51 2250 hp->unplug = spapr_pci_unplug;
3340e5c4 2251 hp->unplug_request = spapr_pci_unplug_request;
298a9710 2252}
3384f95c 2253
4240abff 2254static const TypeInfo spapr_phb_info = {
8c9f64df 2255 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
8558d942 2256 .parent = TYPE_PCI_HOST_BRIDGE,
ce2918cb 2257 .instance_size = sizeof(SpaprPhbState),
ef28b98d 2258 .instance_finalize = spapr_phb_finalizefn,
298a9710 2259 .class_init = spapr_phb_class_init,
7454c7af
MR
2260 .interfaces = (InterfaceInfo[]) {
2261 { TYPE_HOTPLUG_HANDLER },
2262 { }
2263 }
298a9710
DG
2264};
2265
1d2d9742
ND
2266static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2267 void *opaque)
2268{
2269 unsigned int *bus_no = opaque;
1d2d9742
ND
2270 PCIBus *sec_bus = NULL;
2271
2272 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2273 PCI_HEADER_TYPE_BRIDGE)) {
2274 return;
2275 }
2276
2277 (*bus_no)++;
d8e81d6e 2278 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
1d2d9742
ND
2279 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2280 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2281
2282 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2283 if (!sec_bus) {
2284 return;
2285 }
2286
1d2d9742
ND
2287 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2288 spapr_phb_pci_enumerate_bridge, bus_no);
2289 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2290}
2291
ce2918cb 2292static void spapr_phb_pci_enumerate(SpaprPhbState *phb)
1d2d9742
ND
2293{
2294 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2295 unsigned int bus_no = 0;
2296
2297 pci_for_each_device(bus, pci_bus_num(bus),
2298 spapr_phb_pci_enumerate_bridge,
2299 &bus_no);
2300
2301}
2302
466e8831
DG
2303int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt,
2304 uint32_t nr_msis, int *node_offset)
3384f95c 2305{
62083979 2306 int bus_off, i, j, ret;
3384f95c
DG
2307 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2308 struct {
2309 uint32_t hi;
2310 uint64_t child;
2311 uint64_t parent;
2312 uint64_t size;
c4889f54 2313 } QEMU_PACKED ranges[] = {
3384f95c
DG
2314 {
2315 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2316 cpu_to_be64(phb->io_win_addr),
2317 cpu_to_be64(memory_region_size(&phb->iospace)),
2318 },
2319 {
2320 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2321 cpu_to_be64(phb->mem_win_addr),
daa23699 2322 cpu_to_be64(phb->mem_win_size),
b194df47
AK
2323 },
2324 {
daa23699
DG
2325 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2326 cpu_to_be64(phb->mem64_win_addr),
2327 cpu_to_be64(phb->mem64_win_size),
3384f95c
DG
2328 },
2329 };
daa23699
DG
2330 const unsigned sizeof_ranges =
2331 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
3384f95c
DG
2332 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2333 uint32_t interrupt_map_mask[] = {
7fb0bd34
DG
2334 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2335 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
ae4de14c
AK
2336 uint32_t ddw_applicable[] = {
2337 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2338 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2339 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2340 };
2341 uint32_t ddw_extensions[] = {
2342 cpu_to_be32(1),
2343 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2344 };
4814401f
AK
2345 uint32_t associativity[] = {cpu_to_be32(0x4),
2346 cpu_to_be32(0x0),
2347 cpu_to_be32(0x0),
2348 cpu_to_be32(0x0),
2349 cpu_to_be32(phb->numa_node)};
ce2918cb 2350 SpaprTceTable *tcet;
ce2918cb 2351 SpaprDrc *drc;
ec132efa 2352 Error *errp = NULL;
3384f95c
DG
2353
2354 /* Start populating the FDT */
c413605b 2355 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname));
0a0a66cd
MR
2356 if (node_offset) {
2357 *node_offset = bus_off;
2358 }
3384f95c 2359
3384f95c
DG
2360 /* Write PHB properties */
2361 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2362 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
3384f95c
DG
2363 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2364 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2365 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
b194df47 2366 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
3384f95c 2367 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
3f7565c9 2368 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
0976efd5 2369 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis));
3384f95c 2370
ae4de14c
AK
2371 /* Dynamic DMA window */
2372 if (phb->ddw_enabled) {
2373 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2374 sizeof(ddw_applicable)));
2375 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2376 &ddw_extensions, sizeof(ddw_extensions)));
2377 }
2378
4814401f 2379 /* Advertise NUMA via ibm,associativity */
4bcfa56c 2380 if (phb->numa_node != -1) {
4814401f
AK
2381 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
2382 sizeof(associativity)));
2383 }
2384
4d8d5467 2385 /* Build the interrupt-map, this must matches what is done
e8ec4adf 2386 * in pci_swizzle_map_irq_fn
4d8d5467
BH
2387 */
2388 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2389 &interrupt_map_mask, sizeof(interrupt_map_mask)));
7fb0bd34
DG
2390 for (i = 0; i < PCI_SLOT_MAX; i++) {
2391 for (j = 0; j < PCI_NUM_PINS; j++) {
2392 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
e8ec4adf 2393 int lsi_num = pci_swizzle(i, j);
7fb0bd34
DG
2394
2395 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2396 irqmap[1] = 0;
2397 irqmap[2] = 0;
2398 irqmap[3] = cpu_to_be32(j+1);
5c7adcf4
GK
2399 irqmap[4] = cpu_to_be32(intc_phandle);
2400 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
7fb0bd34 2401 }
3384f95c 2402 }
3384f95c
DG
2403 /* Write interrupt map */
2404 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
7fb0bd34 2405 sizeof(interrupt_map)));
3384f95c 2406
ae4de14c 2407 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
da34fed7
TH
2408 if (!tcet) {
2409 return -1;
2410 }
ccf9ff85
AK
2411 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2412 tcet->liobn, tcet->bus_offset,
2413 tcet->nb_table << tcet->page_shift);
edded454 2414
f130928d
MR
2415 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index);
2416 if (drc) {
2417 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc));
2418
2419 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index,
2420 sizeof(drc_index)));
2421 }
2422
1d2d9742
ND
2423 /* Walk the bridges and program the bus numbers*/
2424 spapr_phb_pci_enumerate(phb);
2425 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2426
466e8831
DG
2427 /* Walk the bridge and subordinate buses */
2428 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off);
2429 if (ret < 0) {
62083979
MR
2430 return ret;
2431 }
2432
ec132efa
AK
2433 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &errp);
2434 if (errp) {
2435 error_report_err(errp);
2436 }
2437 spapr_phb_nvgpu_ram_populate_dt(phb, fdt);
2438
3384f95c
DG
2439 return 0;
2440}
298a9710 2441
fa28f71b
AK
2442void spapr_pci_rtas_init(void)
2443{
3a3b8502
AK
2444 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2445 rtas_read_pci_config);
2446 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2447 rtas_write_pci_config);
2448 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2449 rtas_ibm_read_pci_config);
2450 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2451 rtas_ibm_write_pci_config);
226419d6 2452 if (msi_nonbroken) {
3a3b8502
AK
2453 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2454 "ibm,query-interrupt-source-number",
0ee2c058 2455 rtas_ibm_query_interrupt_source_number);
3a3b8502
AK
2456 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2457 rtas_ibm_change_msi);
0ee2c058 2458 }
ee954280
GS
2459
2460 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2461 "ibm,set-eeh-option",
2462 rtas_ibm_set_eeh_option);
2463 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2464 "ibm,get-config-addr-info2",
2465 rtas_ibm_get_config_addr_info2);
2466 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2467 "ibm,read-slot-reset-state2",
2468 rtas_ibm_read_slot_reset_state2);
2469 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2470 "ibm,set-slot-reset",
2471 rtas_ibm_set_slot_reset);
2472 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2473 "ibm,configure-pe",
2474 rtas_ibm_configure_pe);
2475 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2476 "ibm,slot-error-detail",
2477 rtas_ibm_slot_error_detail);
fa28f71b
AK
2478}
2479
8c9f64df 2480static void spapr_pci_register_types(void)
298a9710
DG
2481{
2482 type_register_static(&spapr_phb_info);
2483}
8c9f64df
AF
2484
2485type_init(spapr_pci_register_types)
eefaccc0
DG
2486
2487static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2488{
2489 bool be = *(bool *)opaque;
2490
2491 if (object_dynamic_cast(OBJECT(dev), "VGA")
2492 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
2493 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
2494 &error_abort);
2495 }
2496 return 0;
2497}
2498
2499void spapr_pci_switch_vga(bool big_endian)
2500{
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2501 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
2502 SpaprPhbState *sphb;
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DG
2503
2504 /*
2505 * For backward compatibility with existing guests, we switch
2506 * the endianness of the VGA controller when changing the guest
2507 * interrupt mode
2508 */
2509 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2510 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2511 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2512 &big_endian);
2513 }
2514}