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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/pci/pci.h" | |
27 | #include "hw/pci/msi.h" | |
28 | #include "hw/pci/msix.h" | |
29 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
30 | #include "hw/ppc/spapr.h" |
31 | #include "hw/pci-host/spapr.h" | |
022c62cb | 32 | #include "exec/address-spaces.h" |
3384f95c | 33 | #include <libfdt.h> |
a2950fb6 | 34 | #include "trace.h" |
295d51aa | 35 | #include "qemu/error-report.h" |
3384f95c | 36 | |
06aac7bd | 37 | #include "hw/pci/pci_bus.h" |
3384f95c | 38 | |
0ee2c058 AK |
39 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
40 | #define RTAS_QUERY_FN 0 | |
41 | #define RTAS_CHANGE_FN 1 | |
42 | #define RTAS_RESET_FN 2 | |
43 | #define RTAS_CHANGE_MSI_FN 3 | |
44 | #define RTAS_CHANGE_MSIX_FN 4 | |
45 | ||
46 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
47 | #define RTAS_TYPE_MSI 1 | |
48 | #define RTAS_TYPE_MSIX 2 | |
49 | ||
46c5874e | 50 | sPAPRPHBState *spapr_pci_find_phb(sPAPREnvironment *spapr, uint64_t buid) |
3384f95c | 51 | { |
8c9f64df | 52 | sPAPRPHBState *sphb; |
3384f95c | 53 | |
8c9f64df AF |
54 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
55 | if (sphb->buid != buid) { | |
3384f95c DG |
56 | continue; |
57 | } | |
8c9f64df | 58 | return sphb; |
9894c5d4 AK |
59 | } |
60 | ||
61 | return NULL; | |
62 | } | |
63 | ||
46c5874e AK |
64 | PCIDevice *spapr_pci_find_dev(sPAPREnvironment *spapr, uint64_t buid, |
65 | uint32_t config_addr) | |
9894c5d4 | 66 | { |
46c5874e | 67 | sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 68 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 69 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
70 | int devfn = (config_addr >> 8) & 0xFF; |
71 | ||
72 | if (!phb) { | |
73 | return NULL; | |
74 | } | |
3384f95c | 75 | |
5dac82ce | 76 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
77 | } |
78 | ||
3f7565c9 BH |
79 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
80 | { | |
92615a5a | 81 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
82 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
83 | } | |
84 | ||
92615a5a DG |
85 | static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, |
86 | uint32_t addr, uint32_t size, | |
87 | target_ulong rets) | |
88045ac5 | 88 | { |
92615a5a DG |
89 | PCIDevice *pci_dev; |
90 | uint32_t val; | |
91 | ||
92 | if ((size != 1) && (size != 2) && (size != 4)) { | |
93 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 94 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 95 | return; |
88045ac5 | 96 | } |
88045ac5 | 97 | |
46c5874e | 98 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
99 | addr = rtas_pci_cfgaddr(addr); |
100 | ||
101 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
102 | /* Access must be to a valid device, within bounds and | |
103 | * naturally aligned */ | |
a64d325d | 104 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 105 | return; |
88045ac5 | 106 | } |
92615a5a DG |
107 | |
108 | val = pci_host_config_read_common(pci_dev, addr, | |
109 | pci_config_size(pci_dev), size); | |
110 | ||
a64d325d | 111 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 112 | rtas_st(rets, 1, val); |
88045ac5 AG |
113 | } |
114 | ||
210b580b | 115 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
116 | uint32_t token, uint32_t nargs, |
117 | target_ulong args, | |
118 | uint32_t nret, target_ulong rets) | |
119 | { | |
92615a5a DG |
120 | uint64_t buid; |
121 | uint32_t size, addr; | |
3384f95c | 122 | |
92615a5a | 123 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 124 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
125 | return; |
126 | } | |
92615a5a DG |
127 | |
128 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c | 129 | size = rtas_ld(args, 3); |
92615a5a DG |
130 | addr = rtas_ld(args, 0); |
131 | ||
132 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
133 | } |
134 | ||
210b580b | 135 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
136 | uint32_t token, uint32_t nargs, |
137 | target_ulong args, | |
138 | uint32_t nret, target_ulong rets) | |
139 | { | |
92615a5a | 140 | uint32_t size, addr; |
3384f95c | 141 | |
92615a5a | 142 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 143 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
144 | return; |
145 | } | |
92615a5a | 146 | |
3384f95c | 147 | size = rtas_ld(args, 1); |
92615a5a DG |
148 | addr = rtas_ld(args, 0); |
149 | ||
150 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
151 | } | |
152 | ||
153 | static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, | |
154 | uint32_t addr, uint32_t size, | |
155 | uint32_t val, target_ulong rets) | |
156 | { | |
157 | PCIDevice *pci_dev; | |
158 | ||
159 | if ((size != 1) && (size != 2) && (size != 4)) { | |
160 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 161 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
162 | return; |
163 | } | |
164 | ||
46c5874e | 165 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
166 | addr = rtas_pci_cfgaddr(addr); |
167 | ||
168 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
169 | /* Access must be to a valid device, within bounds and | |
170 | * naturally aligned */ | |
a64d325d | 171 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
172 | return; |
173 | } | |
174 | ||
175 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
176 | val, size); | |
177 | ||
a64d325d | 178 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
179 | } |
180 | ||
210b580b | 181 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
182 | uint32_t token, uint32_t nargs, |
183 | target_ulong args, | |
184 | uint32_t nret, target_ulong rets) | |
185 | { | |
92615a5a | 186 | uint64_t buid; |
3384f95c | 187 | uint32_t val, size, addr; |
3384f95c | 188 | |
92615a5a | 189 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 190 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
191 | return; |
192 | } | |
92615a5a DG |
193 | |
194 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c DG |
195 | val = rtas_ld(args, 4); |
196 | size = rtas_ld(args, 3); | |
92615a5a DG |
197 | addr = rtas_ld(args, 0); |
198 | ||
199 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
200 | } |
201 | ||
210b580b | 202 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
3384f95c DG |
203 | uint32_t token, uint32_t nargs, |
204 | target_ulong args, | |
205 | uint32_t nret, target_ulong rets) | |
206 | { | |
207 | uint32_t val, size, addr; | |
3384f95c | 208 | |
92615a5a | 209 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 210 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
211 | return; |
212 | } | |
92615a5a DG |
213 | |
214 | ||
3384f95c DG |
215 | val = rtas_ld(args, 2); |
216 | size = rtas_ld(args, 1); | |
92615a5a DG |
217 | addr = rtas_ld(args, 0); |
218 | ||
219 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
220 | } |
221 | ||
0ee2c058 AK |
222 | /* |
223 | * Set MSI/MSIX message data. | |
224 | * This is required for msi_notify()/msix_notify() which | |
225 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
226 | * |
227 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
228 | * table will be reset. | |
0ee2c058 | 229 | */ |
f1c2dc7c AK |
230 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
231 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
232 | { |
233 | unsigned i; | |
f1c2dc7c | 234 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
235 | |
236 | if (!msix) { | |
237 | msi_set_message(pdev, msg); | |
238 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
239 | return; | |
240 | } | |
241 | ||
9a321e92 | 242 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
243 | msix_set_message(pdev, i, msg); |
244 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
245 | if (addr) { |
246 | ++msg.data; | |
247 | } | |
0ee2c058 AK |
248 | } |
249 | } | |
250 | ||
210b580b | 251 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
0ee2c058 AK |
252 | uint32_t token, uint32_t nargs, |
253 | target_ulong args, uint32_t nret, | |
254 | target_ulong rets) | |
255 | { | |
256 | uint32_t config_addr = rtas_ld(args, 0); | |
257 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
258 | unsigned int func = rtas_ld(args, 3); | |
259 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
260 | unsigned int seq_num = rtas_ld(args, 5); | |
261 | unsigned int ret_intr_type; | |
9a321e92 | 262 | unsigned int irq, max_irqs = 0, num = 0; |
0ee2c058 AK |
263 | sPAPRPHBState *phb = NULL; |
264 | PCIDevice *pdev = NULL; | |
9a321e92 AK |
265 | spapr_pci_msi *msi; |
266 | int *config_addr_key; | |
0ee2c058 AK |
267 | |
268 | switch (func) { | |
269 | case RTAS_CHANGE_MSI_FN: | |
270 | case RTAS_CHANGE_FN: | |
271 | ret_intr_type = RTAS_TYPE_MSI; | |
272 | break; | |
273 | case RTAS_CHANGE_MSIX_FN: | |
274 | ret_intr_type = RTAS_TYPE_MSIX; | |
275 | break; | |
276 | default: | |
295d51aa | 277 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 278 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
279 | return; |
280 | } | |
281 | ||
282 | /* Fins sPAPRPHBState */ | |
46c5874e | 283 | phb = spapr_pci_find_phb(spapr, buid); |
0ee2c058 | 284 | if (phb) { |
46c5874e | 285 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
0ee2c058 AK |
286 | } |
287 | if (!phb || !pdev) { | |
a64d325d | 288 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
289 | return; |
290 | } | |
291 | ||
292 | /* Releasing MSIs */ | |
293 | if (!req_num) { | |
9a321e92 AK |
294 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
295 | if (!msi) { | |
296 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 297 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
298 | return; |
299 | } | |
9a321e92 AK |
300 | |
301 | xics_free(spapr->icp, msi->first_irq, msi->num); | |
32420522 AK |
302 | if (msi_present(pdev)) { |
303 | spapr_msi_setmsg(pdev, 0, false, 0, num); | |
304 | } | |
305 | if (msix_present(pdev)) { | |
306 | spapr_msi_setmsg(pdev, 0, true, 0, num); | |
307 | } | |
9a321e92 AK |
308 | g_hash_table_remove(phb->msi, &config_addr); |
309 | ||
310 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 311 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
312 | rtas_st(rets, 1, 0); |
313 | return; | |
314 | } | |
315 | ||
316 | /* Enabling MSI */ | |
317 | ||
28668b5f AK |
318 | /* Check if the device supports as many IRQs as requested */ |
319 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
320 | max_irqs = msi_nr_vectors_allocated(pdev); | |
321 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
322 | max_irqs = pdev->msix_entries_nr; | |
323 | } | |
324 | if (!max_irqs) { | |
9a321e92 AK |
325 | error_report("Requested interrupt type %d is not enabled for device %x", |
326 | ret_intr_type, config_addr); | |
28668b5f AK |
327 | rtas_st(rets, 0, -1); /* Hardware error */ |
328 | return; | |
329 | } | |
330 | /* Correct the number if the guest asked for too many */ | |
331 | if (req_num > max_irqs) { | |
9a321e92 | 332 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 333 | req_num = max_irqs; |
9a321e92 AK |
334 | irq = 0; /* to avoid misleading trace */ |
335 | goto out; | |
28668b5f AK |
336 | } |
337 | ||
9a321e92 AK |
338 | /* Allocate MSIs */ |
339 | irq = xics_alloc_block(spapr->icp, 0, req_num, false, | |
340 | ret_intr_type == RTAS_TYPE_MSI); | |
341 | if (!irq) { | |
342 | error_report("Cannot allocate MSIs for device %x", config_addr); | |
a64d325d | 343 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
344 | return; |
345 | } | |
346 | ||
0ee2c058 | 347 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 348 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 349 | irq, req_num); |
0ee2c058 | 350 | |
9a321e92 AK |
351 | /* Add MSI device to cache */ |
352 | msi = g_new(spapr_pci_msi, 1); | |
353 | msi->first_irq = irq; | |
354 | msi->num = req_num; | |
355 | config_addr_key = g_new(int, 1); | |
356 | *config_addr_key = config_addr; | |
357 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
358 | ||
359 | out: | |
a64d325d | 360 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
361 | rtas_st(rets, 1, req_num); |
362 | rtas_st(rets, 2, ++seq_num); | |
363 | rtas_st(rets, 3, ret_intr_type); | |
364 | ||
9a321e92 | 365 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
366 | } |
367 | ||
210b580b AL |
368 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
369 | sPAPREnvironment *spapr, | |
0ee2c058 AK |
370 | uint32_t token, |
371 | uint32_t nargs, | |
372 | target_ulong args, | |
373 | uint32_t nret, | |
374 | target_ulong rets) | |
375 | { | |
376 | uint32_t config_addr = rtas_ld(args, 0); | |
377 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
378 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); | |
0ee2c058 | 379 | sPAPRPHBState *phb = NULL; |
9a321e92 AK |
380 | PCIDevice *pdev = NULL; |
381 | spapr_pci_msi *msi; | |
0ee2c058 | 382 | |
9a321e92 | 383 | /* Find sPAPRPHBState */ |
46c5874e | 384 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 385 | if (phb) { |
46c5874e | 386 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
387 | } |
388 | if (!phb || !pdev) { | |
a64d325d | 389 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
390 | return; |
391 | } | |
392 | ||
393 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
394 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
395 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
396 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 397 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
398 | return; |
399 | } | |
9a321e92 | 400 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
401 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
402 | intr_src_num); | |
403 | ||
a64d325d | 404 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
405 | rtas_st(rets, 1, intr_src_num); |
406 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
407 | } | |
408 | ||
ee954280 GS |
409 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
410 | sPAPREnvironment *spapr, | |
411 | uint32_t token, uint32_t nargs, | |
412 | target_ulong args, uint32_t nret, | |
413 | target_ulong rets) | |
414 | { | |
415 | sPAPRPHBState *sphb; | |
416 | sPAPRPHBClass *spc; | |
417 | uint32_t addr, option; | |
418 | uint64_t buid; | |
419 | int ret; | |
420 | ||
421 | if ((nargs != 4) || (nret != 1)) { | |
422 | goto param_error_exit; | |
423 | } | |
424 | ||
425 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
426 | addr = rtas_ld(args, 0); | |
427 | option = rtas_ld(args, 3); | |
428 | ||
46c5874e | 429 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
430 | if (!sphb) { |
431 | goto param_error_exit; | |
432 | } | |
433 | ||
434 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
435 | if (!spc->eeh_set_option) { | |
436 | goto param_error_exit; | |
437 | } | |
438 | ||
439 | ret = spc->eeh_set_option(sphb, addr, option); | |
440 | rtas_st(rets, 0, ret); | |
441 | return; | |
442 | ||
443 | param_error_exit: | |
444 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
445 | } | |
446 | ||
447 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
448 | sPAPREnvironment *spapr, | |
449 | uint32_t token, uint32_t nargs, | |
450 | target_ulong args, uint32_t nret, | |
451 | target_ulong rets) | |
452 | { | |
453 | sPAPRPHBState *sphb; | |
454 | sPAPRPHBClass *spc; | |
455 | PCIDevice *pdev; | |
456 | uint32_t addr, option; | |
457 | uint64_t buid; | |
458 | ||
459 | if ((nargs != 4) || (nret != 2)) { | |
460 | goto param_error_exit; | |
461 | } | |
462 | ||
463 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 464 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
465 | if (!sphb) { |
466 | goto param_error_exit; | |
467 | } | |
468 | ||
469 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
470 | if (!spc->eeh_set_option) { | |
471 | goto param_error_exit; | |
472 | } | |
473 | ||
474 | /* | |
475 | * We always have PE address of form "00BB0001". "BB" | |
476 | * represents the bus number of PE's primary bus. | |
477 | */ | |
478 | option = rtas_ld(args, 3); | |
479 | switch (option) { | |
480 | case RTAS_GET_PE_ADDR: | |
481 | addr = rtas_ld(args, 0); | |
46c5874e | 482 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
483 | if (!pdev) { |
484 | goto param_error_exit; | |
485 | } | |
486 | ||
487 | rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); | |
488 | break; | |
489 | case RTAS_GET_PE_MODE: | |
490 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
491 | break; | |
492 | default: | |
493 | goto param_error_exit; | |
494 | } | |
495 | ||
496 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
497 | return; | |
498 | ||
499 | param_error_exit: | |
500 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
501 | } | |
502 | ||
503 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
504 | sPAPREnvironment *spapr, | |
505 | uint32_t token, uint32_t nargs, | |
506 | target_ulong args, uint32_t nret, | |
507 | target_ulong rets) | |
508 | { | |
509 | sPAPRPHBState *sphb; | |
510 | sPAPRPHBClass *spc; | |
511 | uint64_t buid; | |
512 | int state, ret; | |
513 | ||
514 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
515 | goto param_error_exit; | |
516 | } | |
517 | ||
518 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 519 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
520 | if (!sphb) { |
521 | goto param_error_exit; | |
522 | } | |
523 | ||
524 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
525 | if (!spc->eeh_get_state) { | |
526 | goto param_error_exit; | |
527 | } | |
528 | ||
529 | ret = spc->eeh_get_state(sphb, &state); | |
530 | rtas_st(rets, 0, ret); | |
531 | if (ret != RTAS_OUT_SUCCESS) { | |
532 | return; | |
533 | } | |
534 | ||
535 | rtas_st(rets, 1, state); | |
536 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
537 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
538 | if (nret >= 5) { | |
539 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
540 | } | |
541 | return; | |
542 | ||
543 | param_error_exit: | |
544 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
545 | } | |
546 | ||
547 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
548 | sPAPREnvironment *spapr, | |
549 | uint32_t token, uint32_t nargs, | |
550 | target_ulong args, uint32_t nret, | |
551 | target_ulong rets) | |
552 | { | |
553 | sPAPRPHBState *sphb; | |
554 | sPAPRPHBClass *spc; | |
555 | uint32_t option; | |
556 | uint64_t buid; | |
557 | int ret; | |
558 | ||
559 | if ((nargs != 4) || (nret != 1)) { | |
560 | goto param_error_exit; | |
561 | } | |
562 | ||
563 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
564 | option = rtas_ld(args, 3); | |
46c5874e | 565 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
566 | if (!sphb) { |
567 | goto param_error_exit; | |
568 | } | |
569 | ||
570 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
571 | if (!spc->eeh_reset) { | |
572 | goto param_error_exit; | |
573 | } | |
574 | ||
575 | ret = spc->eeh_reset(sphb, option); | |
576 | rtas_st(rets, 0, ret); | |
577 | return; | |
578 | ||
579 | param_error_exit: | |
580 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
581 | } | |
582 | ||
583 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
584 | sPAPREnvironment *spapr, | |
585 | uint32_t token, uint32_t nargs, | |
586 | target_ulong args, uint32_t nret, | |
587 | target_ulong rets) | |
588 | { | |
589 | sPAPRPHBState *sphb; | |
590 | sPAPRPHBClass *spc; | |
591 | uint64_t buid; | |
592 | int ret; | |
593 | ||
594 | if ((nargs != 3) || (nret != 1)) { | |
595 | goto param_error_exit; | |
596 | } | |
597 | ||
598 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 599 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
600 | if (!sphb) { |
601 | goto param_error_exit; | |
602 | } | |
603 | ||
604 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
605 | if (!spc->eeh_configure) { | |
606 | goto param_error_exit; | |
607 | } | |
608 | ||
609 | ret = spc->eeh_configure(sphb); | |
610 | rtas_st(rets, 0, ret); | |
611 | return; | |
612 | ||
613 | param_error_exit: | |
614 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
615 | } | |
616 | ||
617 | /* To support it later */ | |
618 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
619 | sPAPREnvironment *spapr, | |
620 | uint32_t token, uint32_t nargs, | |
621 | target_ulong args, uint32_t nret, | |
622 | target_ulong rets) | |
623 | { | |
624 | sPAPRPHBState *sphb; | |
625 | sPAPRPHBClass *spc; | |
626 | int option; | |
627 | uint64_t buid; | |
628 | ||
629 | if ((nargs != 8) || (nret != 1)) { | |
630 | goto param_error_exit; | |
631 | } | |
632 | ||
633 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
46c5874e | 634 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
635 | if (!sphb) { |
636 | goto param_error_exit; | |
637 | } | |
638 | ||
639 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
640 | if (!spc->eeh_set_option) { | |
641 | goto param_error_exit; | |
642 | } | |
643 | ||
644 | option = rtas_ld(args, 7); | |
645 | switch (option) { | |
646 | case RTAS_SLOT_TEMP_ERR_LOG: | |
647 | case RTAS_SLOT_PERM_ERR_LOG: | |
648 | break; | |
649 | default: | |
650 | goto param_error_exit; | |
651 | } | |
652 | ||
653 | /* We don't have error log yet */ | |
654 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
655 | return; | |
656 | ||
657 | param_error_exit: | |
658 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
659 | } | |
660 | ||
7fb0bd34 DG |
661 | static int pci_spapr_swizzle(int slot, int pin) |
662 | { | |
663 | return (slot + pin) % PCI_NUM_PINS; | |
664 | } | |
665 | ||
3384f95c DG |
666 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
667 | { | |
668 | /* | |
669 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
670 | * which is less than number of IRQs on the specific bus (4). We |
671 | * use standard PCI swizzling, that is (slot number + pin number) | |
672 | * % 4. | |
3384f95c | 673 | */ |
7fb0bd34 | 674 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
675 | } |
676 | ||
677 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
678 | { | |
679 | /* | |
680 | * Here we use the number returned by pci_spapr_map_irq to find a | |
681 | * corresponding qemu_irq. | |
682 | */ | |
683 | sPAPRPHBState *phb = opaque; | |
684 | ||
caae58cb | 685 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 686 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
687 | } |
688 | ||
5cc7a967 AK |
689 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
690 | { | |
691 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); | |
692 | PCIINTxRoute route; | |
693 | ||
694 | route.mode = PCI_INTX_ENABLED; | |
695 | route.irq = sphb->lsi_table[pin].irq; | |
696 | ||
697 | return route; | |
698 | } | |
699 | ||
0ee2c058 AK |
700 | /* |
701 | * MSI/MSIX memory region implementation. | |
702 | * The handler handles both MSI and MSIX. | |
703 | * For MSI-X, the vector number is encoded as a part of the address, | |
704 | * data is set to 0. | |
705 | * For MSI, the vector number is encoded in least bits in data. | |
706 | */ | |
a8170e5e | 707 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
708 | uint64_t data, unsigned size) |
709 | { | |
f1c2dc7c | 710 | uint32_t irq = data; |
0ee2c058 AK |
711 | |
712 | trace_spapr_pci_msi_write(addr, data, irq); | |
713 | ||
714 | qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); | |
715 | } | |
716 | ||
717 | static const MemoryRegionOps spapr_msi_ops = { | |
718 | /* There is no .read as the read result is undefined by PCI spec */ | |
719 | .read = NULL, | |
720 | .write = spapr_msi_write, | |
721 | .endianness = DEVICE_LITTLE_ENDIAN | |
722 | }; | |
723 | ||
298a9710 DG |
724 | /* |
725 | * PHB PCI device | |
726 | */ | |
e00387d5 | 727 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
728 | { |
729 | sPAPRPHBState *phb = opaque; | |
730 | ||
e00387d5 | 731 | return &phb->iommu_as; |
edded454 DG |
732 | } |
733 | ||
c6ba42f6 | 734 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 735 | { |
c6ba42f6 | 736 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
8c9f64df | 737 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 738 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
da6ccee4 | 739 | sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); |
298a9710 DG |
740 | char *namebuf; |
741 | int i; | |
3384f95c | 742 | PCIBus *bus; |
8c46f7ec | 743 | uint64_t msi_window_size = 4096; |
3384f95c | 744 | |
421b1b27 | 745 | if (sphb->index != (uint32_t)-1) { |
caae58cb DG |
746 | hwaddr windows_base; |
747 | ||
421b1b27 DG |
748 | if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) |
749 | || (sphb->mem_win_addr != (hwaddr)-1) | |
750 | || (sphb->io_win_addr != (hwaddr)-1)) { | |
c6ba42f6 AK |
751 | error_setg(errp, "Either \"index\" or other parameters must" |
752 | " be specified for PAPR PHB, not both"); | |
753 | return; | |
caae58cb DG |
754 | } |
755 | ||
3e4ac968 DG |
756 | if (sphb->index > SPAPR_PCI_MAX_INDEX) { |
757 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
758 | SPAPR_PCI_MAX_INDEX); | |
759 | return; | |
760 | } | |
761 | ||
caae58cb | 762 | sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; |
c8545818 | 763 | sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); |
caae58cb DG |
764 | |
765 | windows_base = SPAPR_PCI_WINDOW_BASE | |
766 | + sphb->index * SPAPR_PCI_WINDOW_SPACING; | |
767 | sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; | |
768 | sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; | |
caae58cb DG |
769 | } |
770 | ||
421b1b27 | 771 | if (sphb->buid == (uint64_t)-1) { |
c6ba42f6 AK |
772 | error_setg(errp, "BUID not specified for PHB"); |
773 | return; | |
caae58cb DG |
774 | } |
775 | ||
421b1b27 | 776 | if (sphb->dma_liobn == (uint32_t)-1) { |
c6ba42f6 AK |
777 | error_setg(errp, "LIOBN not specified for PHB"); |
778 | return; | |
caae58cb DG |
779 | } |
780 | ||
421b1b27 | 781 | if (sphb->mem_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
782 | error_setg(errp, "Memory window address not specified for PHB"); |
783 | return; | |
caae58cb DG |
784 | } |
785 | ||
421b1b27 | 786 | if (sphb->io_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
787 | error_setg(errp, "IO window address not specified for PHB"); |
788 | return; | |
caae58cb DG |
789 | } |
790 | ||
46c5874e | 791 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
c6ba42f6 AK |
792 | error_setg(errp, "PCI host bridges must have unique BUIDs"); |
793 | return; | |
caae58cb DG |
794 | } |
795 | ||
8c9f64df | 796 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 797 | |
8c9f64df | 798 | namebuf = alloca(strlen(sphb->dtbusname) + 32); |
3384f95c | 799 | |
298a9710 | 800 | /* Initialize memory regions */ |
8c9f64df | 801 | sprintf(namebuf, "%s.mmio", sphb->dtbusname); |
92b8e39c | 802 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
3384f95c | 803 | |
8c9f64df | 804 | sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); |
40c5dce9 PB |
805 | memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), |
806 | namebuf, &sphb->memspace, | |
8c9f64df AF |
807 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
808 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, | |
809 | &sphb->memwindow); | |
3384f95c | 810 | |
fabe9ee1 | 811 | /* Initialize IO regions */ |
8c9f64df | 812 | sprintf(namebuf, "%s.io", sphb->dtbusname); |
40c5dce9 PB |
813 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
814 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
3384f95c | 815 | |
a3cfa18e | 816 | sprintf(namebuf, "%s.io-alias", sphb->dtbusname); |
66aab867 | 817 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 818 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
8c9f64df | 819 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 820 | &sphb->iowindow); |
1b8601b0 AK |
821 | |
822 | bus = pci_register_bus(dev, NULL, | |
8c9f64df AF |
823 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, |
824 | &sphb->memspace, &sphb->iospace, | |
60a0e443 | 825 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); |
8c9f64df | 826 | phb->bus = bus; |
298a9710 | 827 | |
cca7fad5 AK |
828 | /* |
829 | * Initialize PHB address space. | |
830 | * By default there will be at least one subregion for default | |
831 | * 32bit DMA window. | |
832 | * Later the guest might want to create another DMA window | |
833 | * which will become another memory subregion. | |
834 | */ | |
835 | sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); | |
836 | ||
837 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), | |
838 | namebuf, UINT64_MAX); | |
839 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, | |
840 | sphb->dtbusname); | |
841 | ||
8c46f7ec GK |
842 | /* |
843 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
844 | * we need to allocate some memory to catch those writes coming | |
845 | * from msi_notify()/msix_notify(). | |
846 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
847 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
848 | * be used. | |
849 | * | |
850 | * For KVM we want to ensure that this memory is a full page so that | |
851 | * our memory slot is of page size granularity. | |
852 | */ | |
853 | #ifdef CONFIG_KVM | |
854 | if (kvm_enabled()) { | |
855 | msi_window_size = getpagesize(); | |
856 | } | |
857 | #endif | |
858 | ||
859 | memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, | |
860 | "msi", msi_window_size); | |
861 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
862 | &sphb->msiwindow); | |
863 | ||
e00387d5 | 864 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 865 | |
5cc7a967 AK |
866 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
867 | ||
8c9f64df | 868 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
869 | |
870 | /* Initialize the LSI table */ | |
7fb0bd34 | 871 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 872 | uint32_t irq; |
298a9710 | 873 | |
bee763db | 874 | irq = xics_alloc_block(spapr->icp, 0, 1, true, false); |
a307d594 | 875 | if (!irq) { |
c6ba42f6 AK |
876 | error_setg(errp, "spapr_allocate_lsi failed"); |
877 | return; | |
298a9710 DG |
878 | } |
879 | ||
8c9f64df | 880 | sphb->lsi_table[i].irq = irq; |
298a9710 | 881 | } |
da6ccee4 AK |
882 | |
883 | if (!info->finish_realize) { | |
884 | error_setg(errp, "finish_realize not defined"); | |
885 | return; | |
886 | } | |
887 | ||
888 | info->finish_realize(sphb, errp); | |
9a321e92 AK |
889 | |
890 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); | |
da6ccee4 AK |
891 | } |
892 | ||
893 | static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) | |
894 | { | |
e28c16f6 | 895 | sPAPRTCETable *tcet; |
3e1a01cb | 896 | uint32_t nb_table; |
e28c16f6 | 897 | |
3e1a01cb | 898 | nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; |
e28c16f6 | 899 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, |
3e1a01cb | 900 | 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); |
e28c16f6 | 901 | if (!tcet) { |
da6ccee4 AK |
902 | error_setg(errp, "Unable to create TCE table for %s", |
903 | sphb->dtbusname); | |
904 | return ; | |
905 | } | |
cca7fad5 AK |
906 | |
907 | /* Register default 32bit DMA window */ | |
908 | memory_region_add_subregion(&sphb->iommu_root, 0, | |
e28c16f6 | 909 | spapr_tce_get_iommu(tcet)); |
298a9710 DG |
910 | } |
911 | ||
e28c16f6 | 912 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 913 | { |
e28c16f6 AK |
914 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
915 | ||
916 | if (dev) { | |
917 | device_reset(dev); | |
918 | } | |
eddeed26 | 919 | |
e28c16f6 AK |
920 | return 0; |
921 | } | |
922 | ||
923 | static void spapr_phb_reset(DeviceState *qdev) | |
924 | { | |
eddeed26 | 925 | /* Reset the IOMMU state */ |
e28c16f6 | 926 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
eddeed26 DG |
927 | } |
928 | ||
298a9710 | 929 | static Property spapr_phb_properties[] = { |
3e4ac968 | 930 | DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), |
c7bcc85d PB |
931 | DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), |
932 | DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), | |
933 | DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), | |
934 | DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, | |
935 | SPAPR_PCI_MMIO_WIN_SIZE), | |
936 | DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), | |
937 | DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, | |
938 | SPAPR_PCI_IO_WIN_SIZE), | |
298a9710 DG |
939 | DEFINE_PROP_END_OF_LIST(), |
940 | }; | |
941 | ||
1112cf94 DG |
942 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
943 | .name = "spapr_pci/lsi", | |
944 | .version_id = 1, | |
945 | .minimum_version_id = 1, | |
3aff6c2f | 946 | .fields = (VMStateField[]) { |
1112cf94 DG |
947 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), |
948 | ||
949 | VMSTATE_END_OF_LIST() | |
950 | }, | |
951 | }; | |
952 | ||
953 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 954 | .name = "spapr_pci/msi", |
1112cf94 DG |
955 | .version_id = 1, |
956 | .minimum_version_id = 1, | |
9a321e92 AK |
957 | .fields = (VMStateField []) { |
958 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
959 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
960 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
961 | VMSTATE_END_OF_LIST() |
962 | }, | |
963 | }; | |
964 | ||
f8833a37 PM |
965 | static void spapr_pci_fill_msi_devs(gpointer key, gpointer value, |
966 | gpointer opaque) | |
967 | { | |
968 | sPAPRPHBState *sphb = opaque; | |
969 | ||
970 | sphb->msi_devs[sphb->msi_devs_num].key = *(uint32_t *)key; | |
971 | sphb->msi_devs[sphb->msi_devs_num].value = *(spapr_pci_msi *)value; | |
972 | sphb->msi_devs_num++; | |
973 | } | |
974 | ||
9a321e92 AK |
975 | static void spapr_pci_pre_save(void *opaque) |
976 | { | |
977 | sPAPRPHBState *sphb = opaque; | |
f8833a37 | 978 | int msi_devs_num; |
9a321e92 AK |
979 | |
980 | if (sphb->msi_devs) { | |
981 | g_free(sphb->msi_devs); | |
982 | sphb->msi_devs = NULL; | |
983 | } | |
f8833a37 PM |
984 | sphb->msi_devs_num = 0; |
985 | msi_devs_num = g_hash_table_size(sphb->msi); | |
986 | if (!msi_devs_num) { | |
9a321e92 AK |
987 | return; |
988 | } | |
f8833a37 | 989 | sphb->msi_devs = g_malloc(msi_devs_num * sizeof(spapr_pci_msi_mig)); |
9a321e92 | 990 | |
f8833a37 PM |
991 | g_hash_table_foreach(sphb->msi, spapr_pci_fill_msi_devs, sphb); |
992 | assert(sphb->msi_devs_num == msi_devs_num); | |
9a321e92 AK |
993 | } |
994 | ||
995 | static int spapr_pci_post_load(void *opaque, int version_id) | |
996 | { | |
997 | sPAPRPHBState *sphb = opaque; | |
998 | gpointer key, value; | |
999 | int i; | |
1000 | ||
1001 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
1002 | key = g_memdup(&sphb->msi_devs[i].key, | |
1003 | sizeof(sphb->msi_devs[i].key)); | |
1004 | value = g_memdup(&sphb->msi_devs[i].value, | |
1005 | sizeof(sphb->msi_devs[i].value)); | |
1006 | g_hash_table_insert(sphb->msi, key, value); | |
1007 | } | |
1008 | if (sphb->msi_devs) { | |
1009 | g_free(sphb->msi_devs); | |
1010 | sphb->msi_devs = NULL; | |
1011 | } | |
1012 | sphb->msi_devs_num = 0; | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
1112cf94 DG |
1017 | static const VMStateDescription vmstate_spapr_pci = { |
1018 | .name = "spapr_pci", | |
9a321e92 AK |
1019 | .version_id = 2, |
1020 | .minimum_version_id = 2, | |
1021 | .pre_save = spapr_pci_pre_save, | |
1022 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 1023 | .fields = (VMStateField[]) { |
1112cf94 DG |
1024 | VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), |
1025 | VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), | |
1026 | VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), | |
1027 | VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), | |
1028 | VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), | |
1029 | VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), | |
1112cf94 DG |
1030 | VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, |
1031 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), | |
9a321e92 AK |
1032 | VMSTATE_INT32(msi_devs_num, sPAPRPHBState), |
1033 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, | |
1034 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), | |
1112cf94 DG |
1035 | VMSTATE_END_OF_LIST() |
1036 | }, | |
1037 | }; | |
1038 | ||
568f0690 DG |
1039 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
1040 | PCIBus *rootbus) | |
1041 | { | |
1042 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
1043 | ||
1044 | return sphb->dtbusname; | |
1045 | } | |
1046 | ||
298a9710 DG |
1047 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
1048 | { | |
568f0690 | 1049 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 1050 | DeviceClass *dc = DEVICE_CLASS(klass); |
da6ccee4 | 1051 | sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 1052 | |
568f0690 | 1053 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 1054 | dc->realize = spapr_phb_realize; |
298a9710 | 1055 | dc->props = spapr_phb_properties; |
eddeed26 | 1056 | dc->reset = spapr_phb_reset; |
1112cf94 | 1057 | dc->vmsd = &vmstate_spapr_pci; |
09aa9a52 AK |
1058 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
1059 | dc->cannot_instantiate_with_device_add_yet = false; | |
da6ccee4 | 1060 | spc->finish_realize = spapr_phb_finish_realize; |
298a9710 | 1061 | } |
3384f95c | 1062 | |
4240abff | 1063 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 1064 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 1065 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
1066 | .instance_size = sizeof(sPAPRPHBState), |
1067 | .class_init = spapr_phb_class_init, | |
da6ccee4 | 1068 | .class_size = sizeof(sPAPRPHBClass), |
298a9710 DG |
1069 | }; |
1070 | ||
89dfd6e1 | 1071 | PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index) |
298a9710 DG |
1072 | { |
1073 | DeviceState *dev; | |
1074 | ||
8c9f64df | 1075 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 1076 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 1077 | qdev_init_nofail(dev); |
caae58cb DG |
1078 | |
1079 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
1080 | } |
1081 | ||
1082 | /* Macros to operate with address in OF binding to PCI */ | |
1083 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
1084 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
1085 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
1086 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
1087 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
1088 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
1089 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
1090 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
1091 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
1092 | ||
e28c16f6 AK |
1093 | typedef struct sPAPRTCEDT { |
1094 | void *fdt; | |
1095 | int node_off; | |
1096 | } sPAPRTCEDT; | |
1097 | ||
1098 | static int spapr_phb_children_dt(Object *child, void *opaque) | |
1099 | { | |
1100 | sPAPRTCEDT *p = opaque; | |
1101 | sPAPRTCETable *tcet; | |
1102 | ||
1103 | tcet = (sPAPRTCETable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE); | |
c8545818 | 1104 | if (!tcet || SPAPR_PCI_DMA_WINDOW_NUM(tcet->liobn)) { |
e28c16f6 AK |
1105 | return 0; |
1106 | } | |
1107 | ||
1108 | spapr_dma_dt(p->fdt, p->node_off, "ibm,dma-window", | |
1b8eceee AK |
1109 | tcet->liobn, tcet->bus_offset, |
1110 | tcet->nb_table << tcet->page_shift); | |
e28c16f6 AK |
1111 | /* Stop after the first window */ |
1112 | ||
1113 | return 1; | |
1114 | } | |
1115 | ||
e0fdbd7c AK |
1116 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
1117 | uint32_t xics_phandle, | |
1118 | void *fdt) | |
3384f95c | 1119 | { |
7fb0bd34 | 1120 | int bus_off, i, j; |
3384f95c | 1121 | char nodename[256]; |
3384f95c | 1122 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
b194df47 AK |
1123 | const uint64_t mmiosize = memory_region_size(&phb->memwindow); |
1124 | const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; | |
1125 | const uint64_t w32size = MIN(w32max, mmiosize); | |
1126 | const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; | |
3384f95c DG |
1127 | struct { |
1128 | uint32_t hi; | |
1129 | uint64_t child; | |
1130 | uint64_t parent; | |
1131 | uint64_t size; | |
c4889f54 | 1132 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
1133 | { |
1134 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
1135 | cpu_to_be64(phb->io_win_addr), | |
1136 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
1137 | }, | |
1138 | { | |
1139 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
1140 | cpu_to_be64(phb->mem_win_addr), | |
b194df47 AK |
1141 | cpu_to_be64(w32size), |
1142 | }, | |
1143 | { | |
1144 | cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), | |
1145 | cpu_to_be64(phb->mem_win_addr + w32size), | |
1146 | cpu_to_be64(w64size) | |
3384f95c DG |
1147 | }, |
1148 | }; | |
b194df47 | 1149 | const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); |
3384f95c DG |
1150 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
1151 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
1152 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
1153 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
3384f95c DG |
1154 | |
1155 | /* Start populating the FDT */ | |
1156 | sprintf(nodename, "pci@%" PRIx64, phb->buid); | |
1157 | bus_off = fdt_add_subnode(fdt, 0, nodename); | |
1158 | if (bus_off < 0) { | |
1159 | return bus_off; | |
1160 | } | |
1161 | ||
1162 | #define _FDT(exp) \ | |
1163 | do { \ | |
1164 | int ret = (exp); \ | |
1165 | if (ret < 0) { \ | |
1166 | return ret; \ | |
1167 | } \ | |
1168 | } while (0) | |
1169 | ||
1170 | /* Write PHB properties */ | |
1171 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
1172 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
1173 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
1174 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
1175 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
1176 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
1177 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 1178 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 1179 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 1180 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
9dbae977 | 1181 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); |
3384f95c | 1182 | |
4d8d5467 BH |
1183 | /* Build the interrupt-map, this must matches what is done |
1184 | * in pci_spapr_map_irq | |
1185 | */ | |
1186 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
1187 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
1188 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
1189 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
1190 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
1191 | int lsi_num = pci_spapr_swizzle(i, j); | |
1192 | ||
1193 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
1194 | irqmap[1] = 0; | |
1195 | irqmap[2] = 0; | |
1196 | irqmap[3] = cpu_to_be32(j+1); | |
1197 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 1198 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
1199 | irqmap[6] = cpu_to_be32(0x8); |
1200 | } | |
3384f95c | 1201 | } |
3384f95c DG |
1202 | /* Write interrupt map */ |
1203 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 1204 | sizeof(interrupt_map))); |
3384f95c | 1205 | |
e28c16f6 AK |
1206 | object_child_foreach(OBJECT(phb), spapr_phb_children_dt, |
1207 | &((sPAPRTCEDT){ .fdt = fdt, .node_off = bus_off })); | |
edded454 | 1208 | |
3384f95c DG |
1209 | return 0; |
1210 | } | |
298a9710 | 1211 | |
fa28f71b AK |
1212 | void spapr_pci_rtas_init(void) |
1213 | { | |
3a3b8502 AK |
1214 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
1215 | rtas_read_pci_config); | |
1216 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
1217 | rtas_write_pci_config); | |
1218 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
1219 | rtas_ibm_read_pci_config); | |
1220 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
1221 | rtas_ibm_write_pci_config); | |
0ee2c058 | 1222 | if (msi_supported) { |
3a3b8502 AK |
1223 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
1224 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 1225 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
1226 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
1227 | rtas_ibm_change_msi); | |
0ee2c058 | 1228 | } |
ee954280 GS |
1229 | |
1230 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
1231 | "ibm,set-eeh-option", | |
1232 | rtas_ibm_set_eeh_option); | |
1233 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
1234 | "ibm,get-config-addr-info2", | |
1235 | rtas_ibm_get_config_addr_info2); | |
1236 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
1237 | "ibm,read-slot-reset-state2", | |
1238 | rtas_ibm_read_slot_reset_state2); | |
1239 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
1240 | "ibm,set-slot-reset", | |
1241 | rtas_ibm_set_slot_reset); | |
1242 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
1243 | "ibm,configure-pe", | |
1244 | rtas_ibm_configure_pe); | |
1245 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
1246 | "ibm,slot-error-detail", | |
1247 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
1248 | } |
1249 | ||
8c9f64df | 1250 | static void spapr_pci_register_types(void) |
298a9710 DG |
1251 | { |
1252 | type_register_static(&spapr_phb_info); | |
1253 | } | |
8c9f64df AF |
1254 | |
1255 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
1256 | |
1257 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
1258 | { | |
1259 | bool be = *(bool *)opaque; | |
1260 | ||
1261 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
1262 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
1263 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
1264 | &error_abort); | |
1265 | } | |
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | void spapr_pci_switch_vga(bool big_endian) | |
1270 | { | |
1271 | sPAPRPHBState *sphb; | |
1272 | ||
1273 | /* | |
1274 | * For backward compatibility with existing guests, we switch | |
1275 | * the endianness of the VGA controller when changing the guest | |
1276 | * interrupt mode | |
1277 | */ | |
1278 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
1279 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
1280 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
1281 | &big_endian); | |
1282 | } | |
1283 | } |