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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
83c9f4ca | 25 | #include "hw/hw.h" |
1d2d9742 | 26 | #include "hw/sysbus.h" |
83c9f4ca PB |
27 | #include "hw/pci/pci.h" |
28 | #include "hw/pci/msi.h" | |
29 | #include "hw/pci/msix.h" | |
30 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
31 | #include "hw/ppc/spapr.h" |
32 | #include "hw/pci-host/spapr.h" | |
022c62cb | 33 | #include "exec/address-spaces.h" |
3384f95c | 34 | #include <libfdt.h> |
a2950fb6 | 35 | #include "trace.h" |
295d51aa | 36 | #include "qemu/error-report.h" |
7454c7af | 37 | #include "qapi/qmp/qerror.h" |
3384f95c | 38 | |
1d2d9742 | 39 | #include "hw/pci/pci_bridge.h" |
06aac7bd | 40 | #include "hw/pci/pci_bus.h" |
62083979 | 41 | #include "hw/ppc/spapr_drc.h" |
7454c7af | 42 | #include "sysemu/device_tree.h" |
3384f95c | 43 | |
0ee2c058 AK |
44 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
45 | #define RTAS_QUERY_FN 0 | |
46 | #define RTAS_CHANGE_FN 1 | |
47 | #define RTAS_RESET_FN 2 | |
48 | #define RTAS_CHANGE_MSI_FN 3 | |
49 | #define RTAS_CHANGE_MSIX_FN 4 | |
50 | ||
51 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
52 | #define RTAS_TYPE_MSI 1 | |
53 | #define RTAS_TYPE_MSIX 2 | |
54 | ||
9b7d9284 ND |
55 | #define FDT_NAME_MAX 128 |
56 | ||
7454c7af MR |
57 | #define _FDT(exp) \ |
58 | do { \ | |
59 | int ret = (exp); \ | |
60 | if (ret < 0) { \ | |
61 | return ret; \ | |
62 | } \ | |
63 | } while (0) | |
64 | ||
28e02042 | 65 | sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) |
3384f95c | 66 | { |
8c9f64df | 67 | sPAPRPHBState *sphb; |
3384f95c | 68 | |
8c9f64df AF |
69 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
70 | if (sphb->buid != buid) { | |
3384f95c DG |
71 | continue; |
72 | } | |
8c9f64df | 73 | return sphb; |
9894c5d4 AK |
74 | } |
75 | ||
76 | return NULL; | |
77 | } | |
78 | ||
28e02042 | 79 | PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, |
46c5874e | 80 | uint32_t config_addr) |
9894c5d4 | 81 | { |
46c5874e | 82 | sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 83 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 84 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
85 | int devfn = (config_addr >> 8) & 0xFF; |
86 | ||
87 | if (!phb) { | |
88 | return NULL; | |
89 | } | |
3384f95c | 90 | |
5dac82ce | 91 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
92 | } |
93 | ||
3f7565c9 BH |
94 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
95 | { | |
92615a5a | 96 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
97 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
98 | } | |
99 | ||
28e02042 | 100 | static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
101 | uint32_t addr, uint32_t size, |
102 | target_ulong rets) | |
88045ac5 | 103 | { |
92615a5a DG |
104 | PCIDevice *pci_dev; |
105 | uint32_t val; | |
106 | ||
107 | if ((size != 1) && (size != 2) && (size != 4)) { | |
108 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 109 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 110 | return; |
88045ac5 | 111 | } |
88045ac5 | 112 | |
46c5874e | 113 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
114 | addr = rtas_pci_cfgaddr(addr); |
115 | ||
116 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
117 | /* Access must be to a valid device, within bounds and | |
118 | * naturally aligned */ | |
a64d325d | 119 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 120 | return; |
88045ac5 | 121 | } |
92615a5a DG |
122 | |
123 | val = pci_host_config_read_common(pci_dev, addr, | |
124 | pci_config_size(pci_dev), size); | |
125 | ||
a64d325d | 126 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 127 | rtas_st(rets, 1, val); |
88045ac5 AG |
128 | } |
129 | ||
28e02042 | 130 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
131 | uint32_t token, uint32_t nargs, |
132 | target_ulong args, | |
133 | uint32_t nret, target_ulong rets) | |
134 | { | |
92615a5a DG |
135 | uint64_t buid; |
136 | uint32_t size, addr; | |
3384f95c | 137 | |
92615a5a | 138 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 139 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
140 | return; |
141 | } | |
92615a5a | 142 | |
a14aa92b | 143 | buid = rtas_ldq(args, 1); |
3384f95c | 144 | size = rtas_ld(args, 3); |
92615a5a DG |
145 | addr = rtas_ld(args, 0); |
146 | ||
147 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
148 | } |
149 | ||
28e02042 | 150 | static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
151 | uint32_t token, uint32_t nargs, |
152 | target_ulong args, | |
153 | uint32_t nret, target_ulong rets) | |
154 | { | |
92615a5a | 155 | uint32_t size, addr; |
3384f95c | 156 | |
92615a5a | 157 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 158 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
159 | return; |
160 | } | |
92615a5a | 161 | |
3384f95c | 162 | size = rtas_ld(args, 1); |
92615a5a DG |
163 | addr = rtas_ld(args, 0); |
164 | ||
165 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
166 | } | |
167 | ||
28e02042 | 168 | static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, |
92615a5a DG |
169 | uint32_t addr, uint32_t size, |
170 | uint32_t val, target_ulong rets) | |
171 | { | |
172 | PCIDevice *pci_dev; | |
173 | ||
174 | if ((size != 1) && (size != 2) && (size != 4)) { | |
175 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 176 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
177 | return; |
178 | } | |
179 | ||
46c5874e | 180 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
181 | addr = rtas_pci_cfgaddr(addr); |
182 | ||
183 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
184 | /* Access must be to a valid device, within bounds and | |
185 | * naturally aligned */ | |
a64d325d | 186 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
187 | return; |
188 | } | |
189 | ||
190 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
191 | val, size); | |
192 | ||
a64d325d | 193 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
194 | } |
195 | ||
28e02042 | 196 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
197 | uint32_t token, uint32_t nargs, |
198 | target_ulong args, | |
199 | uint32_t nret, target_ulong rets) | |
200 | { | |
92615a5a | 201 | uint64_t buid; |
3384f95c | 202 | uint32_t val, size, addr; |
3384f95c | 203 | |
92615a5a | 204 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 205 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
206 | return; |
207 | } | |
92615a5a | 208 | |
a14aa92b | 209 | buid = rtas_ldq(args, 1); |
3384f95c DG |
210 | val = rtas_ld(args, 4); |
211 | size = rtas_ld(args, 3); | |
92615a5a DG |
212 | addr = rtas_ld(args, 0); |
213 | ||
214 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
215 | } |
216 | ||
28e02042 | 217 | static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
3384f95c DG |
218 | uint32_t token, uint32_t nargs, |
219 | target_ulong args, | |
220 | uint32_t nret, target_ulong rets) | |
221 | { | |
222 | uint32_t val, size, addr; | |
3384f95c | 223 | |
92615a5a | 224 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 225 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
226 | return; |
227 | } | |
92615a5a DG |
228 | |
229 | ||
3384f95c DG |
230 | val = rtas_ld(args, 2); |
231 | size = rtas_ld(args, 1); | |
92615a5a DG |
232 | addr = rtas_ld(args, 0); |
233 | ||
234 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
235 | } |
236 | ||
0ee2c058 AK |
237 | /* |
238 | * Set MSI/MSIX message data. | |
239 | * This is required for msi_notify()/msix_notify() which | |
240 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
241 | * |
242 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
243 | * table will be reset. | |
0ee2c058 | 244 | */ |
f1c2dc7c AK |
245 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
246 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
247 | { |
248 | unsigned i; | |
f1c2dc7c | 249 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
250 | |
251 | if (!msix) { | |
252 | msi_set_message(pdev, msg); | |
253 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
254 | return; | |
255 | } | |
256 | ||
9a321e92 | 257 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
258 | msix_set_message(pdev, i, msg); |
259 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
260 | if (addr) { |
261 | ++msg.data; | |
262 | } | |
0ee2c058 AK |
263 | } |
264 | } | |
265 | ||
28e02042 | 266 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
0ee2c058 AK |
267 | uint32_t token, uint32_t nargs, |
268 | target_ulong args, uint32_t nret, | |
269 | target_ulong rets) | |
270 | { | |
271 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 272 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 AK |
273 | unsigned int func = rtas_ld(args, 3); |
274 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
275 | unsigned int seq_num = rtas_ld(args, 5); | |
276 | unsigned int ret_intr_type; | |
9a321e92 | 277 | unsigned int irq, max_irqs = 0, num = 0; |
0ee2c058 AK |
278 | sPAPRPHBState *phb = NULL; |
279 | PCIDevice *pdev = NULL; | |
9a321e92 AK |
280 | spapr_pci_msi *msi; |
281 | int *config_addr_key; | |
0ee2c058 AK |
282 | |
283 | switch (func) { | |
284 | case RTAS_CHANGE_MSI_FN: | |
285 | case RTAS_CHANGE_FN: | |
286 | ret_intr_type = RTAS_TYPE_MSI; | |
287 | break; | |
288 | case RTAS_CHANGE_MSIX_FN: | |
289 | ret_intr_type = RTAS_TYPE_MSIX; | |
290 | break; | |
291 | default: | |
295d51aa | 292 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 293 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
294 | return; |
295 | } | |
296 | ||
297 | /* Fins sPAPRPHBState */ | |
46c5874e | 298 | phb = spapr_pci_find_phb(spapr, buid); |
0ee2c058 | 299 | if (phb) { |
46c5874e | 300 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
0ee2c058 AK |
301 | } |
302 | if (!phb || !pdev) { | |
a64d325d | 303 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
304 | return; |
305 | } | |
306 | ||
307 | /* Releasing MSIs */ | |
308 | if (!req_num) { | |
9a321e92 AK |
309 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
310 | if (!msi) { | |
311 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 312 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
313 | return; |
314 | } | |
9a321e92 AK |
315 | |
316 | xics_free(spapr->icp, msi->first_irq, msi->num); | |
32420522 AK |
317 | if (msi_present(pdev)) { |
318 | spapr_msi_setmsg(pdev, 0, false, 0, num); | |
319 | } | |
320 | if (msix_present(pdev)) { | |
321 | spapr_msi_setmsg(pdev, 0, true, 0, num); | |
322 | } | |
9a321e92 AK |
323 | g_hash_table_remove(phb->msi, &config_addr); |
324 | ||
325 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 326 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
327 | rtas_st(rets, 1, 0); |
328 | return; | |
329 | } | |
330 | ||
331 | /* Enabling MSI */ | |
332 | ||
28668b5f AK |
333 | /* Check if the device supports as many IRQs as requested */ |
334 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
335 | max_irqs = msi_nr_vectors_allocated(pdev); | |
336 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
337 | max_irqs = pdev->msix_entries_nr; | |
338 | } | |
339 | if (!max_irqs) { | |
9a321e92 AK |
340 | error_report("Requested interrupt type %d is not enabled for device %x", |
341 | ret_intr_type, config_addr); | |
28668b5f AK |
342 | rtas_st(rets, 0, -1); /* Hardware error */ |
343 | return; | |
344 | } | |
345 | /* Correct the number if the guest asked for too many */ | |
346 | if (req_num > max_irqs) { | |
9a321e92 | 347 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 348 | req_num = max_irqs; |
9a321e92 AK |
349 | irq = 0; /* to avoid misleading trace */ |
350 | goto out; | |
28668b5f AK |
351 | } |
352 | ||
9a321e92 AK |
353 | /* Allocate MSIs */ |
354 | irq = xics_alloc_block(spapr->icp, 0, req_num, false, | |
355 | ret_intr_type == RTAS_TYPE_MSI); | |
356 | if (!irq) { | |
357 | error_report("Cannot allocate MSIs for device %x", config_addr); | |
a64d325d | 358 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
359 | return; |
360 | } | |
361 | ||
0ee2c058 | 362 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 363 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 364 | irq, req_num); |
0ee2c058 | 365 | |
9a321e92 AK |
366 | /* Add MSI device to cache */ |
367 | msi = g_new(spapr_pci_msi, 1); | |
368 | msi->first_irq = irq; | |
369 | msi->num = req_num; | |
370 | config_addr_key = g_new(int, 1); | |
371 | *config_addr_key = config_addr; | |
372 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
373 | ||
374 | out: | |
a64d325d | 375 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
376 | rtas_st(rets, 1, req_num); |
377 | rtas_st(rets, 2, ++seq_num); | |
b359bd6a SB |
378 | if (nret > 3) { |
379 | rtas_st(rets, 3, ret_intr_type); | |
380 | } | |
0ee2c058 | 381 | |
9a321e92 | 382 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
383 | } |
384 | ||
210b580b | 385 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
28e02042 | 386 | sPAPRMachineState *spapr, |
0ee2c058 AK |
387 | uint32_t token, |
388 | uint32_t nargs, | |
389 | target_ulong args, | |
390 | uint32_t nret, | |
391 | target_ulong rets) | |
392 | { | |
393 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 394 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 | 395 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); |
0ee2c058 | 396 | sPAPRPHBState *phb = NULL; |
9a321e92 AK |
397 | PCIDevice *pdev = NULL; |
398 | spapr_pci_msi *msi; | |
0ee2c058 | 399 | |
9a321e92 | 400 | /* Find sPAPRPHBState */ |
46c5874e | 401 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 402 | if (phb) { |
46c5874e | 403 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
404 | } |
405 | if (!phb || !pdev) { | |
a64d325d | 406 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
407 | return; |
408 | } | |
409 | ||
410 | /* Find device descriptor and start IRQ */ | |
9a321e92 AK |
411 | msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); |
412 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { | |
413 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 414 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
415 | return; |
416 | } | |
9a321e92 | 417 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
418 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
419 | intr_src_num); | |
420 | ||
a64d325d | 421 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
422 | rtas_st(rets, 1, intr_src_num); |
423 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
424 | } | |
425 | ||
ee954280 | 426 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
28e02042 | 427 | sPAPRMachineState *spapr, |
ee954280 GS |
428 | uint32_t token, uint32_t nargs, |
429 | target_ulong args, uint32_t nret, | |
430 | target_ulong rets) | |
431 | { | |
432 | sPAPRPHBState *sphb; | |
433 | sPAPRPHBClass *spc; | |
434 | uint32_t addr, option; | |
435 | uint64_t buid; | |
436 | int ret; | |
437 | ||
438 | if ((nargs != 4) || (nret != 1)) { | |
439 | goto param_error_exit; | |
440 | } | |
441 | ||
a14aa92b | 442 | buid = rtas_ldq(args, 1); |
ee954280 GS |
443 | addr = rtas_ld(args, 0); |
444 | option = rtas_ld(args, 3); | |
445 | ||
46c5874e | 446 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
447 | if (!sphb) { |
448 | goto param_error_exit; | |
449 | } | |
450 | ||
451 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
452 | if (!spc->eeh_set_option) { | |
453 | goto param_error_exit; | |
454 | } | |
455 | ||
456 | ret = spc->eeh_set_option(sphb, addr, option); | |
457 | rtas_st(rets, 0, ret); | |
458 | return; | |
459 | ||
460 | param_error_exit: | |
461 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
462 | } | |
463 | ||
464 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
28e02042 | 465 | sPAPRMachineState *spapr, |
ee954280 GS |
466 | uint32_t token, uint32_t nargs, |
467 | target_ulong args, uint32_t nret, | |
468 | target_ulong rets) | |
469 | { | |
470 | sPAPRPHBState *sphb; | |
471 | sPAPRPHBClass *spc; | |
472 | PCIDevice *pdev; | |
473 | uint32_t addr, option; | |
474 | uint64_t buid; | |
475 | ||
476 | if ((nargs != 4) || (nret != 2)) { | |
477 | goto param_error_exit; | |
478 | } | |
479 | ||
a14aa92b | 480 | buid = rtas_ldq(args, 1); |
46c5874e | 481 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
482 | if (!sphb) { |
483 | goto param_error_exit; | |
484 | } | |
485 | ||
486 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
487 | if (!spc->eeh_set_option) { | |
488 | goto param_error_exit; | |
489 | } | |
490 | ||
491 | /* | |
492 | * We always have PE address of form "00BB0001". "BB" | |
493 | * represents the bus number of PE's primary bus. | |
494 | */ | |
495 | option = rtas_ld(args, 3); | |
496 | switch (option) { | |
497 | case RTAS_GET_PE_ADDR: | |
498 | addr = rtas_ld(args, 0); | |
46c5874e | 499 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
500 | if (!pdev) { |
501 | goto param_error_exit; | |
502 | } | |
503 | ||
504 | rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); | |
505 | break; | |
506 | case RTAS_GET_PE_MODE: | |
507 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
508 | break; | |
509 | default: | |
510 | goto param_error_exit; | |
511 | } | |
512 | ||
513 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
514 | return; | |
515 | ||
516 | param_error_exit: | |
517 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
518 | } | |
519 | ||
520 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
28e02042 | 521 | sPAPRMachineState *spapr, |
ee954280 GS |
522 | uint32_t token, uint32_t nargs, |
523 | target_ulong args, uint32_t nret, | |
524 | target_ulong rets) | |
525 | { | |
526 | sPAPRPHBState *sphb; | |
527 | sPAPRPHBClass *spc; | |
528 | uint64_t buid; | |
529 | int state, ret; | |
530 | ||
531 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
532 | goto param_error_exit; | |
533 | } | |
534 | ||
a14aa92b | 535 | buid = rtas_ldq(args, 1); |
46c5874e | 536 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
537 | if (!sphb) { |
538 | goto param_error_exit; | |
539 | } | |
540 | ||
541 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
542 | if (!spc->eeh_get_state) { | |
543 | goto param_error_exit; | |
544 | } | |
545 | ||
546 | ret = spc->eeh_get_state(sphb, &state); | |
547 | rtas_st(rets, 0, ret); | |
548 | if (ret != RTAS_OUT_SUCCESS) { | |
549 | return; | |
550 | } | |
551 | ||
552 | rtas_st(rets, 1, state); | |
553 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
554 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
555 | if (nret >= 5) { | |
556 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
557 | } | |
558 | return; | |
559 | ||
560 | param_error_exit: | |
561 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
562 | } | |
563 | ||
564 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
28e02042 | 565 | sPAPRMachineState *spapr, |
ee954280 GS |
566 | uint32_t token, uint32_t nargs, |
567 | target_ulong args, uint32_t nret, | |
568 | target_ulong rets) | |
569 | { | |
570 | sPAPRPHBState *sphb; | |
571 | sPAPRPHBClass *spc; | |
572 | uint32_t option; | |
573 | uint64_t buid; | |
574 | int ret; | |
575 | ||
576 | if ((nargs != 4) || (nret != 1)) { | |
577 | goto param_error_exit; | |
578 | } | |
579 | ||
a14aa92b | 580 | buid = rtas_ldq(args, 1); |
ee954280 | 581 | option = rtas_ld(args, 3); |
46c5874e | 582 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
583 | if (!sphb) { |
584 | goto param_error_exit; | |
585 | } | |
586 | ||
587 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
588 | if (!spc->eeh_reset) { | |
589 | goto param_error_exit; | |
590 | } | |
591 | ||
592 | ret = spc->eeh_reset(sphb, option); | |
593 | rtas_st(rets, 0, ret); | |
594 | return; | |
595 | ||
596 | param_error_exit: | |
597 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
598 | } | |
599 | ||
600 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
28e02042 | 601 | sPAPRMachineState *spapr, |
ee954280 GS |
602 | uint32_t token, uint32_t nargs, |
603 | target_ulong args, uint32_t nret, | |
604 | target_ulong rets) | |
605 | { | |
606 | sPAPRPHBState *sphb; | |
607 | sPAPRPHBClass *spc; | |
608 | uint64_t buid; | |
609 | int ret; | |
610 | ||
611 | if ((nargs != 3) || (nret != 1)) { | |
612 | goto param_error_exit; | |
613 | } | |
614 | ||
a14aa92b | 615 | buid = rtas_ldq(args, 1); |
46c5874e | 616 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
617 | if (!sphb) { |
618 | goto param_error_exit; | |
619 | } | |
620 | ||
621 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
622 | if (!spc->eeh_configure) { | |
623 | goto param_error_exit; | |
624 | } | |
625 | ||
626 | ret = spc->eeh_configure(sphb); | |
627 | rtas_st(rets, 0, ret); | |
628 | return; | |
629 | ||
630 | param_error_exit: | |
631 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
632 | } | |
633 | ||
634 | /* To support it later */ | |
635 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
28e02042 | 636 | sPAPRMachineState *spapr, |
ee954280 GS |
637 | uint32_t token, uint32_t nargs, |
638 | target_ulong args, uint32_t nret, | |
639 | target_ulong rets) | |
640 | { | |
641 | sPAPRPHBState *sphb; | |
642 | sPAPRPHBClass *spc; | |
643 | int option; | |
644 | uint64_t buid; | |
645 | ||
646 | if ((nargs != 8) || (nret != 1)) { | |
647 | goto param_error_exit; | |
648 | } | |
649 | ||
a14aa92b | 650 | buid = rtas_ldq(args, 1); |
46c5874e | 651 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
652 | if (!sphb) { |
653 | goto param_error_exit; | |
654 | } | |
655 | ||
656 | spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); | |
657 | if (!spc->eeh_set_option) { | |
658 | goto param_error_exit; | |
659 | } | |
660 | ||
661 | option = rtas_ld(args, 7); | |
662 | switch (option) { | |
663 | case RTAS_SLOT_TEMP_ERR_LOG: | |
664 | case RTAS_SLOT_PERM_ERR_LOG: | |
665 | break; | |
666 | default: | |
667 | goto param_error_exit; | |
668 | } | |
669 | ||
670 | /* We don't have error log yet */ | |
671 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
672 | return; | |
673 | ||
674 | param_error_exit: | |
675 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
676 | } | |
677 | ||
7fb0bd34 DG |
678 | static int pci_spapr_swizzle(int slot, int pin) |
679 | { | |
680 | return (slot + pin) % PCI_NUM_PINS; | |
681 | } | |
682 | ||
3384f95c DG |
683 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
684 | { | |
685 | /* | |
686 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
687 | * which is less than number of IRQs on the specific bus (4). We |
688 | * use standard PCI swizzling, that is (slot number + pin number) | |
689 | * % 4. | |
3384f95c | 690 | */ |
7fb0bd34 | 691 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
692 | } |
693 | ||
694 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
695 | { | |
696 | /* | |
697 | * Here we use the number returned by pci_spapr_map_irq to find a | |
698 | * corresponding qemu_irq. | |
699 | */ | |
700 | sPAPRPHBState *phb = opaque; | |
701 | ||
caae58cb | 702 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 703 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
704 | } |
705 | ||
5cc7a967 AK |
706 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
707 | { | |
708 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); | |
709 | PCIINTxRoute route; | |
710 | ||
711 | route.mode = PCI_INTX_ENABLED; | |
712 | route.irq = sphb->lsi_table[pin].irq; | |
713 | ||
714 | return route; | |
715 | } | |
716 | ||
0ee2c058 AK |
717 | /* |
718 | * MSI/MSIX memory region implementation. | |
719 | * The handler handles both MSI and MSIX. | |
720 | * For MSI-X, the vector number is encoded as a part of the address, | |
721 | * data is set to 0. | |
722 | * For MSI, the vector number is encoded in least bits in data. | |
723 | */ | |
a8170e5e | 724 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
725 | uint64_t data, unsigned size) |
726 | { | |
28e02042 | 727 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
f1c2dc7c | 728 | uint32_t irq = data; |
0ee2c058 AK |
729 | |
730 | trace_spapr_pci_msi_write(addr, data, irq); | |
731 | ||
732 | qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); | |
733 | } | |
734 | ||
735 | static const MemoryRegionOps spapr_msi_ops = { | |
736 | /* There is no .read as the read result is undefined by PCI spec */ | |
737 | .read = NULL, | |
738 | .write = spapr_msi_write, | |
739 | .endianness = DEVICE_LITTLE_ENDIAN | |
740 | }; | |
741 | ||
298a9710 DG |
742 | /* |
743 | * PHB PCI device | |
744 | */ | |
e00387d5 | 745 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 DG |
746 | { |
747 | sPAPRPHBState *phb = opaque; | |
748 | ||
e00387d5 | 749 | return &phb->iommu_as; |
edded454 DG |
750 | } |
751 | ||
16b0ea1d ND |
752 | static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) |
753 | { | |
754 | char *path = NULL, *buf = NULL, *host = NULL; | |
755 | ||
756 | /* Get the PCI VFIO host id */ | |
757 | host = object_property_get_str(OBJECT(pdev), "host", NULL); | |
758 | if (!host) { | |
759 | goto err_out; | |
760 | } | |
761 | ||
762 | /* Construct the path of the file that will give us the DT location */ | |
763 | path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); | |
764 | g_free(host); | |
765 | if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { | |
766 | goto err_out; | |
767 | } | |
768 | g_free(path); | |
769 | ||
770 | /* Construct and read from host device tree the loc-code */ | |
771 | path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); | |
772 | g_free(buf); | |
773 | if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { | |
774 | goto err_out; | |
775 | } | |
776 | return buf; | |
777 | ||
778 | err_out: | |
779 | g_free(path); | |
780 | return NULL; | |
781 | } | |
782 | ||
783 | static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) | |
784 | { | |
785 | char *buf; | |
786 | const char *devtype = "qemu"; | |
787 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
788 | ||
789 | if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
790 | buf = spapr_phb_vfio_get_loc_code(sphb, pdev); | |
791 | if (buf) { | |
792 | return buf; | |
793 | } | |
794 | devtype = "vfio"; | |
795 | } | |
796 | /* | |
797 | * For emulated devices and VFIO-failure case, make up | |
798 | * the loc-code. | |
799 | */ | |
800 | buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", | |
801 | devtype, pdev->name, sphb->index, busnr, | |
802 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
803 | return buf; | |
804 | } | |
805 | ||
7454c7af MR |
806 | /* Macros to operate with address in OF binding to PCI */ |
807 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
808 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
809 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
810 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
811 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
812 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
813 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
814 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
815 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
816 | ||
817 | /* for 'reg'/'assigned-addresses' OF properties */ | |
818 | #define RESOURCE_CELLS_SIZE 2 | |
819 | #define RESOURCE_CELLS_ADDRESS 3 | |
820 | ||
821 | typedef struct ResourceFields { | |
822 | uint32_t phys_hi; | |
823 | uint32_t phys_mid; | |
824 | uint32_t phys_lo; | |
825 | uint32_t size_hi; | |
826 | uint32_t size_lo; | |
827 | } QEMU_PACKED ResourceFields; | |
828 | ||
829 | typedef struct ResourceProps { | |
830 | ResourceFields reg[8]; | |
831 | ResourceFields assigned[7]; | |
832 | uint32_t reg_len; | |
833 | uint32_t assigned_len; | |
834 | } ResourceProps; | |
835 | ||
836 | /* fill in the 'reg'/'assigned-resources' OF properties for | |
837 | * a PCI device. 'reg' describes resource requirements for a | |
838 | * device's IO/MEM regions, 'assigned-addresses' describes the | |
839 | * actual resource assignments. | |
840 | * | |
841 | * the properties are arrays of ('phys-addr', 'size') pairs describing | |
842 | * the addressable regions of the PCI device, where 'phys-addr' is a | |
843 | * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to | |
844 | * (phys.hi, phys.mid, phys.lo), and 'size' is a | |
845 | * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). | |
846 | * | |
847 | * phys.hi = 0xYYXXXXZZ, where: | |
848 | * 0xYY = npt000ss | |
849 | * ||| | | |
72187935 ND |
850 | * ||| +-- space code |
851 | * ||| | | |
852 | * ||| + 00 if configuration space | |
853 | * ||| + 01 if IO region, | |
854 | * ||| + 10 if 32-bit MEM region | |
855 | * ||| + 11 if 64-bit MEM region | |
856 | * ||| | |
7454c7af MR |
857 | * ||+------ for non-relocatable IO: 1 if aliased |
858 | * || for relocatable IO: 1 if below 64KB | |
859 | * || for MEM: 1 if below 1MB | |
860 | * |+------- 1 if region is prefetchable | |
861 | * +-------- 1 if region is non-relocatable | |
862 | * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function | |
863 | * bits respectively | |
864 | * 0xZZ = rrrrrrrr, the register number of the BAR corresponding | |
865 | * to the region | |
866 | * | |
867 | * phys.mid and phys.lo correspond respectively to the hi/lo portions | |
868 | * of the actual address of the region. | |
869 | * | |
870 | * how the phys-addr/size values are used differ slightly between | |
871 | * 'reg' and 'assigned-addresses' properties. namely, 'reg' has | |
872 | * an additional description for the config space region of the | |
873 | * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 | |
874 | * to describe the region as relocatable, with an address-mapping | |
875 | * that corresponds directly to the PHB's address space for the | |
876 | * resource. 'assigned-addresses' always has n=1 set with an absolute | |
877 | * address assigned for the resource. in general, 'assigned-addresses' | |
878 | * won't be populated, since addresses for PCI devices are generally | |
879 | * unmapped initially and left to the guest to assign. | |
880 | * | |
881 | * note also that addresses defined in these properties are, at least | |
882 | * for PAPR guests, relative to the PHBs IO/MEM windows, and | |
883 | * correspond directly to the addresses in the BARs. | |
884 | * | |
885 | * in accordance with PCI Bus Binding to Open Firmware, | |
886 | * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, | |
887 | * Appendix C. | |
888 | */ | |
889 | static void populate_resource_props(PCIDevice *d, ResourceProps *rp) | |
890 | { | |
891 | int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); | |
892 | uint32_t dev_id = (b_bbbbbbbb(bus_num) | | |
893 | b_ddddd(PCI_SLOT(d->devfn)) | | |
894 | b_fff(PCI_FUNC(d->devfn))); | |
895 | ResourceFields *reg, *assigned; | |
896 | int i, reg_idx = 0, assigned_idx = 0; | |
897 | ||
898 | /* config space region */ | |
899 | reg = &rp->reg[reg_idx++]; | |
900 | reg->phys_hi = cpu_to_be32(dev_id); | |
901 | reg->phys_mid = 0; | |
902 | reg->phys_lo = 0; | |
903 | reg->size_hi = 0; | |
904 | reg->size_lo = 0; | |
905 | ||
906 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
907 | if (!d->io_regions[i].size) { | |
908 | continue; | |
909 | } | |
910 | ||
911 | reg = &rp->reg[reg_idx++]; | |
912 | ||
913 | reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); | |
914 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
915 | reg->phys_hi |= cpu_to_be32(b_ss(1)); | |
72187935 ND |
916 | } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
917 | reg->phys_hi |= cpu_to_be32(b_ss(3)); | |
7454c7af MR |
918 | } else { |
919 | reg->phys_hi |= cpu_to_be32(b_ss(2)); | |
920 | } | |
921 | reg->phys_mid = 0; | |
922 | reg->phys_lo = 0; | |
923 | reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); | |
924 | reg->size_lo = cpu_to_be32(d->io_regions[i].size); | |
925 | ||
926 | if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { | |
927 | continue; | |
928 | } | |
929 | ||
930 | assigned = &rp->assigned[assigned_idx++]; | |
931 | assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); | |
932 | assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); | |
933 | assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); | |
934 | assigned->size_hi = reg->size_hi; | |
935 | assigned->size_lo = reg->size_lo; | |
936 | } | |
937 | ||
938 | rp->reg_len = reg_idx * sizeof(ResourceFields); | |
939 | rp->assigned_len = assigned_idx * sizeof(ResourceFields); | |
940 | } | |
941 | ||
e634b89c ND |
942 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
943 | PCIDevice *pdev); | |
944 | ||
7454c7af | 945 | static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, |
16b0ea1d | 946 | sPAPRPHBState *sphb) |
7454c7af MR |
947 | { |
948 | ResourceProps rp; | |
949 | bool is_bridge = false; | |
16b0ea1d ND |
950 | int pci_status, err; |
951 | char *buf = NULL; | |
e634b89c | 952 | uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); |
a8ad731a | 953 | uint32_t max_msi, max_msix; |
7454c7af MR |
954 | |
955 | if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == | |
956 | PCI_HEADER_TYPE_BRIDGE) { | |
957 | is_bridge = true; | |
958 | } | |
959 | ||
960 | /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ | |
961 | _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", | |
962 | pci_default_read_config(dev, PCI_VENDOR_ID, 2))); | |
963 | _FDT(fdt_setprop_cell(fdt, offset, "device-id", | |
964 | pci_default_read_config(dev, PCI_DEVICE_ID, 2))); | |
965 | _FDT(fdt_setprop_cell(fdt, offset, "revision-id", | |
966 | pci_default_read_config(dev, PCI_REVISION_ID, 1))); | |
967 | _FDT(fdt_setprop_cell(fdt, offset, "class-code", | |
4a7c3474 | 968 | pci_default_read_config(dev, PCI_CLASS_PROG, 3))); |
7454c7af MR |
969 | if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { |
970 | _FDT(fdt_setprop_cell(fdt, offset, "interrupts", | |
971 | pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); | |
972 | } | |
973 | ||
974 | if (!is_bridge) { | |
975 | _FDT(fdt_setprop_cell(fdt, offset, "min-grant", | |
976 | pci_default_read_config(dev, PCI_MIN_GNT, 1))); | |
977 | _FDT(fdt_setprop_cell(fdt, offset, "max-latency", | |
978 | pci_default_read_config(dev, PCI_MAX_LAT, 1))); | |
979 | } | |
980 | ||
981 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { | |
982 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", | |
983 | pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); | |
984 | } | |
985 | ||
986 | if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { | |
987 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", | |
988 | pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); | |
989 | } | |
990 | ||
991 | _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", | |
992 | pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); | |
993 | ||
994 | /* the following fdt cells are masked off the pci status register */ | |
995 | pci_status = pci_default_read_config(dev, PCI_STATUS, 2); | |
996 | _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", | |
997 | PCI_STATUS_DEVSEL_MASK & pci_status)); | |
998 | ||
999 | if (pci_status & PCI_STATUS_FAST_BACK) { | |
1000 | _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); | |
1001 | } | |
1002 | if (pci_status & PCI_STATUS_66MHZ) { | |
1003 | _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); | |
1004 | } | |
1005 | if (pci_status & PCI_STATUS_UDF) { | |
1006 | _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); | |
1007 | } | |
1008 | ||
1009 | /* NOTE: this is normally generated by firmware via path/unit name, | |
1010 | * but in our case we must set it manually since it does not get | |
1011 | * processed by OF beforehand | |
1012 | */ | |
1013 | _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); | |
16b0ea1d ND |
1014 | buf = spapr_phb_get_loc_code(sphb, dev); |
1015 | if (!buf) { | |
1016 | error_report("Failed setting the ibm,loc-code"); | |
1017 | return -1; | |
1018 | } | |
1019 | ||
1020 | err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); | |
1021 | g_free(buf); | |
1022 | if (err < 0) { | |
1023 | return err; | |
1024 | } | |
1025 | ||
e634b89c ND |
1026 | if (drc_index) { |
1027 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); | |
1028 | } | |
7454c7af MR |
1029 | |
1030 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", | |
1031 | RESOURCE_CELLS_ADDRESS)); | |
1032 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", | |
1033 | RESOURCE_CELLS_SIZE)); | |
a8ad731a MR |
1034 | |
1035 | max_msi = msi_nr_vectors_allocated(dev); | |
1036 | if (max_msi) { | |
1037 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); | |
1038 | } | |
1039 | max_msix = dev->msix_entries_nr; | |
1040 | if (max_msix) { | |
1041 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); | |
1042 | } | |
7454c7af MR |
1043 | |
1044 | populate_resource_props(dev, &rp); | |
1045 | _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); | |
1046 | _FDT(fdt_setprop(fdt, offset, "assigned-addresses", | |
1047 | (uint8_t *)rp.assigned, rp.assigned_len)); | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | /* create OF node for pci device and required OF DT properties */ | |
1d2d9742 | 1053 | static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, |
1d2d9742 | 1054 | void *fdt, int node_offset) |
7454c7af | 1055 | { |
1d2d9742 | 1056 | int offset, ret; |
7454c7af MR |
1057 | int slot = PCI_SLOT(dev->devfn); |
1058 | int func = PCI_FUNC(dev->devfn); | |
9b7d9284 | 1059 | char nodename[FDT_NAME_MAX]; |
7454c7af | 1060 | |
7454c7af | 1061 | if (func != 0) { |
9b7d9284 | 1062 | snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); |
7454c7af | 1063 | } else { |
9b7d9284 | 1064 | snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); |
7454c7af | 1065 | } |
1d2d9742 | 1066 | offset = fdt_add_subnode(fdt, node_offset, nodename); |
e634b89c ND |
1067 | ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); |
1068 | ||
7454c7af | 1069 | g_assert(!ret); |
1d2d9742 ND |
1070 | if (ret) { |
1071 | return 0; | |
1072 | } | |
1073 | return offset; | |
7454c7af MR |
1074 | } |
1075 | ||
1076 | static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, | |
1077 | sPAPRPHBState *phb, | |
1078 | PCIDevice *pdev, | |
1079 | Error **errp) | |
1080 | { | |
1081 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1082 | DeviceState *dev = DEVICE(pdev); | |
7454c7af | 1083 | void *fdt = NULL; |
1d2d9742 | 1084 | int fdt_start_offset = 0, fdt_size; |
7454c7af | 1085 | |
7454c7af | 1086 | if (dev->hotplugged) { |
1d2d9742 | 1087 | fdt = create_device_tree(&fdt_size); |
e634b89c | 1088 | fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); |
1d2d9742 ND |
1089 | if (!fdt_start_offset) { |
1090 | error_setg(errp, "Failed to create pci child device tree node"); | |
1091 | goto out; | |
1092 | } | |
7454c7af MR |
1093 | } |
1094 | ||
1095 | drck->attach(drc, DEVICE(pdev), | |
1096 | fdt, fdt_start_offset, !dev->hotplugged, errp); | |
1d2d9742 | 1097 | out: |
7454c7af MR |
1098 | if (*errp) { |
1099 | g_free(fdt); | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) | |
1104 | { | |
1105 | /* some version guests do not wait for completion of a device | |
1106 | * cleanup (generally done asynchronously by the kernel) before | |
1107 | * signaling to QEMU that the device is safe, but instead sleep | |
1108 | * for some 'safe' period of time. unfortunately on a busy host | |
1109 | * this sleep isn't guaranteed to be long enough, resulting in | |
1110 | * bad things like IRQ lines being left asserted during final | |
1111 | * device removal. to deal with this we call reset just prior | |
1112 | * to finalizing the device, which will put the device back into | |
1113 | * an 'idle' state, as the device cleanup code expects. | |
1114 | */ | |
1115 | pci_device_reset(PCI_DEVICE(dev)); | |
1116 | object_unparent(OBJECT(dev)); | |
1117 | } | |
1118 | ||
1119 | static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, | |
1120 | sPAPRPHBState *phb, | |
1121 | PCIDevice *pdev, | |
1122 | Error **errp) | |
1123 | { | |
1124 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1125 | ||
1126 | drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); | |
1127 | } | |
1128 | ||
1129 | static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, | |
1130 | PCIDevice *pdev) | |
1131 | { | |
1132 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
1133 | return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, | |
1134 | (phb->index << 16) | | |
1135 | (busnr << 8) | | |
1136 | pdev->devfn); | |
1137 | } | |
1138 | ||
1d2d9742 ND |
1139 | static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, |
1140 | PCIDevice *pdev) | |
1141 | { | |
1142 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1143 | sPAPRDRConnectorClass *drck; | |
1144 | ||
1145 | if (!drc) { | |
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1150 | return drck->get_index(drc); | |
1151 | } | |
1152 | ||
7454c7af MR |
1153 | static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, |
1154 | DeviceState *plugged_dev, Error **errp) | |
1155 | { | |
1156 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1157 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1158 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1159 | Error *local_err = NULL; | |
1160 | ||
1161 | /* if DR is disabled we don't need to do anything in the case of | |
1162 | * hotplug or coldplug callbacks | |
1163 | */ | |
1164 | if (!phb->dr_enabled) { | |
1165 | /* if this is a hotplug operation initiated by the user | |
1166 | * we need to let them know it's not enabled | |
1167 | */ | |
1168 | if (plugged_dev->hotplugged) { | |
c6bd8c70 MA |
1169 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1170 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1171 | } |
1172 | return; | |
1173 | } | |
1174 | ||
1175 | g_assert(drc); | |
1176 | ||
1177 | spapr_phb_add_pci_device(drc, phb, pdev, &local_err); | |
1178 | if (local_err) { | |
1179 | error_propagate(errp, local_err); | |
1180 | return; | |
1181 | } | |
c5bc152b | 1182 | if (plugged_dev->hotplugged) { |
7a36ae7a | 1183 | spapr_hotplug_req_add_by_index(drc); |
c5bc152b | 1184 | } |
7454c7af MR |
1185 | } |
1186 | ||
1187 | static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, | |
1188 | DeviceState *plugged_dev, Error **errp) | |
1189 | { | |
1190 | sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1191 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); | |
1192 | sPAPRDRConnectorClass *drck; | |
1193 | sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); | |
1194 | Error *local_err = NULL; | |
1195 | ||
1196 | if (!phb->dr_enabled) { | |
c6bd8c70 MA |
1197 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1198 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1199 | return; |
1200 | } | |
1201 | ||
1202 | g_assert(drc); | |
1203 | ||
1204 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
1205 | if (!drck->release_pending(drc)) { | |
1206 | spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); | |
1207 | if (local_err) { | |
1208 | error_propagate(errp, local_err); | |
1209 | return; | |
1210 | } | |
7a36ae7a | 1211 | spapr_hotplug_req_remove_by_index(drc); |
7454c7af MR |
1212 | } |
1213 | } | |
1214 | ||
c6ba42f6 | 1215 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 1216 | { |
28e02042 | 1217 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
c6ba42f6 | 1218 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
8c9f64df | 1219 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 1220 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
da6ccee4 | 1221 | sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); |
298a9710 DG |
1222 | char *namebuf; |
1223 | int i; | |
3384f95c | 1224 | PCIBus *bus; |
8c46f7ec | 1225 | uint64_t msi_window_size = 4096; |
3384f95c | 1226 | |
421b1b27 | 1227 | if (sphb->index != (uint32_t)-1) { |
caae58cb DG |
1228 | hwaddr windows_base; |
1229 | ||
421b1b27 DG |
1230 | if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) |
1231 | || (sphb->mem_win_addr != (hwaddr)-1) | |
1232 | || (sphb->io_win_addr != (hwaddr)-1)) { | |
c6ba42f6 AK |
1233 | error_setg(errp, "Either \"index\" or other parameters must" |
1234 | " be specified for PAPR PHB, not both"); | |
1235 | return; | |
caae58cb DG |
1236 | } |
1237 | ||
3e4ac968 DG |
1238 | if (sphb->index > SPAPR_PCI_MAX_INDEX) { |
1239 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
1240 | SPAPR_PCI_MAX_INDEX); | |
1241 | return; | |
1242 | } | |
1243 | ||
caae58cb | 1244 | sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; |
c8545818 | 1245 | sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); |
caae58cb DG |
1246 | |
1247 | windows_base = SPAPR_PCI_WINDOW_BASE | |
1248 | + sphb->index * SPAPR_PCI_WINDOW_SPACING; | |
1249 | sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; | |
1250 | sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; | |
caae58cb DG |
1251 | } |
1252 | ||
421b1b27 | 1253 | if (sphb->buid == (uint64_t)-1) { |
c6ba42f6 AK |
1254 | error_setg(errp, "BUID not specified for PHB"); |
1255 | return; | |
caae58cb DG |
1256 | } |
1257 | ||
421b1b27 | 1258 | if (sphb->dma_liobn == (uint32_t)-1) { |
c6ba42f6 AK |
1259 | error_setg(errp, "LIOBN not specified for PHB"); |
1260 | return; | |
caae58cb DG |
1261 | } |
1262 | ||
421b1b27 | 1263 | if (sphb->mem_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1264 | error_setg(errp, "Memory window address not specified for PHB"); |
1265 | return; | |
caae58cb DG |
1266 | } |
1267 | ||
421b1b27 | 1268 | if (sphb->io_win_addr == (hwaddr)-1) { |
c6ba42f6 AK |
1269 | error_setg(errp, "IO window address not specified for PHB"); |
1270 | return; | |
caae58cb DG |
1271 | } |
1272 | ||
46c5874e | 1273 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
c6ba42f6 AK |
1274 | error_setg(errp, "PCI host bridges must have unique BUIDs"); |
1275 | return; | |
caae58cb DG |
1276 | } |
1277 | ||
8c9f64df | 1278 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 1279 | |
8c9f64df | 1280 | namebuf = alloca(strlen(sphb->dtbusname) + 32); |
3384f95c | 1281 | |
298a9710 | 1282 | /* Initialize memory regions */ |
8c9f64df | 1283 | sprintf(namebuf, "%s.mmio", sphb->dtbusname); |
92b8e39c | 1284 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
3384f95c | 1285 | |
8c9f64df | 1286 | sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); |
40c5dce9 PB |
1287 | memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), |
1288 | namebuf, &sphb->memspace, | |
8c9f64df AF |
1289 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
1290 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, | |
1291 | &sphb->memwindow); | |
3384f95c | 1292 | |
fabe9ee1 | 1293 | /* Initialize IO regions */ |
8c9f64df | 1294 | sprintf(namebuf, "%s.io", sphb->dtbusname); |
40c5dce9 PB |
1295 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
1296 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
3384f95c | 1297 | |
a3cfa18e | 1298 | sprintf(namebuf, "%s.io-alias", sphb->dtbusname); |
66aab867 | 1299 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 1300 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
8c9f64df | 1301 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 1302 | &sphb->iowindow); |
1b8601b0 AK |
1303 | |
1304 | bus = pci_register_bus(dev, NULL, | |
8c9f64df AF |
1305 | pci_spapr_set_irq, pci_spapr_map_irq, sphb, |
1306 | &sphb->memspace, &sphb->iospace, | |
60a0e443 | 1307 | PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); |
8c9f64df | 1308 | phb->bus = bus; |
7454c7af | 1309 | qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); |
298a9710 | 1310 | |
cca7fad5 AK |
1311 | /* |
1312 | * Initialize PHB address space. | |
1313 | * By default there will be at least one subregion for default | |
1314 | * 32bit DMA window. | |
1315 | * Later the guest might want to create another DMA window | |
1316 | * which will become another memory subregion. | |
1317 | */ | |
1318 | sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); | |
1319 | ||
1320 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), | |
1321 | namebuf, UINT64_MAX); | |
1322 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, | |
1323 | sphb->dtbusname); | |
1324 | ||
8c46f7ec GK |
1325 | /* |
1326 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
1327 | * we need to allocate some memory to catch those writes coming | |
1328 | * from msi_notify()/msix_notify(). | |
1329 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
1330 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
1331 | * be used. | |
1332 | * | |
1333 | * For KVM we want to ensure that this memory is a full page so that | |
1334 | * our memory slot is of page size granularity. | |
1335 | */ | |
1336 | #ifdef CONFIG_KVM | |
1337 | if (kvm_enabled()) { | |
1338 | msi_window_size = getpagesize(); | |
1339 | } | |
1340 | #endif | |
1341 | ||
1342 | memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, | |
1343 | "msi", msi_window_size); | |
1344 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
1345 | &sphb->msiwindow); | |
1346 | ||
e00387d5 | 1347 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 1348 | |
5cc7a967 AK |
1349 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
1350 | ||
8c9f64df | 1351 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
1352 | |
1353 | /* Initialize the LSI table */ | |
7fb0bd34 | 1354 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 1355 | uint32_t irq; |
298a9710 | 1356 | |
bee763db | 1357 | irq = xics_alloc_block(spapr->icp, 0, 1, true, false); |
a307d594 | 1358 | if (!irq) { |
c6ba42f6 AK |
1359 | error_setg(errp, "spapr_allocate_lsi failed"); |
1360 | return; | |
298a9710 DG |
1361 | } |
1362 | ||
8c9f64df | 1363 | sphb->lsi_table[i].irq = irq; |
298a9710 | 1364 | } |
da6ccee4 | 1365 | |
62083979 MR |
1366 | /* allocate connectors for child PCI devices */ |
1367 | if (sphb->dr_enabled) { | |
1368 | for (i = 0; i < PCI_SLOT_MAX * 8; i++) { | |
1369 | spapr_dr_connector_new(OBJECT(phb), | |
1370 | SPAPR_DR_CONNECTOR_TYPE_PCI, | |
1371 | (sphb->index << 16) | i); | |
1372 | } | |
1373 | } | |
1374 | ||
da6ccee4 AK |
1375 | if (!info->finish_realize) { |
1376 | error_setg(errp, "finish_realize not defined"); | |
1377 | return; | |
1378 | } | |
1379 | ||
1380 | info->finish_realize(sphb, errp); | |
9a321e92 AK |
1381 | |
1382 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); | |
da6ccee4 AK |
1383 | } |
1384 | ||
1385 | static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) | |
1386 | { | |
e28c16f6 | 1387 | sPAPRTCETable *tcet; |
3e1a01cb | 1388 | uint32_t nb_table; |
e28c16f6 | 1389 | |
3e1a01cb | 1390 | nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; |
e28c16f6 | 1391 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, |
3e1a01cb | 1392 | 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); |
e28c16f6 | 1393 | if (!tcet) { |
da6ccee4 AK |
1394 | error_setg(errp, "Unable to create TCE table for %s", |
1395 | sphb->dtbusname); | |
1396 | return ; | |
1397 | } | |
cca7fad5 AK |
1398 | |
1399 | /* Register default 32bit DMA window */ | |
1400 | memory_region_add_subregion(&sphb->iommu_root, 0, | |
e28c16f6 | 1401 | spapr_tce_get_iommu(tcet)); |
298a9710 DG |
1402 | } |
1403 | ||
e28c16f6 | 1404 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 1405 | { |
e28c16f6 AK |
1406 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
1407 | ||
1408 | if (dev) { | |
1409 | device_reset(dev); | |
1410 | } | |
eddeed26 | 1411 | |
e28c16f6 AK |
1412 | return 0; |
1413 | } | |
1414 | ||
1415 | static void spapr_phb_reset(DeviceState *qdev) | |
1416 | { | |
eddeed26 | 1417 | /* Reset the IOMMU state */ |
e28c16f6 | 1418 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
eddeed26 DG |
1419 | } |
1420 | ||
298a9710 | 1421 | static Property spapr_phb_properties[] = { |
3e4ac968 | 1422 | DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), |
c7bcc85d PB |
1423 | DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), |
1424 | DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), | |
1425 | DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), | |
1426 | DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, | |
1427 | SPAPR_PCI_MMIO_WIN_SIZE), | |
1428 | DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), | |
1429 | DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, | |
1430 | SPAPR_PCI_IO_WIN_SIZE), | |
7619c7b0 MR |
1431 | DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, |
1432 | true), | |
298a9710 DG |
1433 | DEFINE_PROP_END_OF_LIST(), |
1434 | }; | |
1435 | ||
1112cf94 DG |
1436 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
1437 | .name = "spapr_pci/lsi", | |
1438 | .version_id = 1, | |
1439 | .minimum_version_id = 1, | |
3aff6c2f | 1440 | .fields = (VMStateField[]) { |
1112cf94 DG |
1441 | VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), |
1442 | ||
1443 | VMSTATE_END_OF_LIST() | |
1444 | }, | |
1445 | }; | |
1446 | ||
1447 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 1448 | .name = "spapr_pci/msi", |
1112cf94 DG |
1449 | .version_id = 1, |
1450 | .minimum_version_id = 1, | |
9a321e92 AK |
1451 | .fields = (VMStateField []) { |
1452 | VMSTATE_UINT32(key, spapr_pci_msi_mig), | |
1453 | VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), | |
1454 | VMSTATE_UINT32(value.num, spapr_pci_msi_mig), | |
1112cf94 DG |
1455 | VMSTATE_END_OF_LIST() |
1456 | }, | |
1457 | }; | |
1458 | ||
9a321e92 AK |
1459 | static void spapr_pci_pre_save(void *opaque) |
1460 | { | |
1461 | sPAPRPHBState *sphb = opaque; | |
708414f0 MA |
1462 | GHashTableIter iter; |
1463 | gpointer key, value; | |
1464 | int i; | |
9a321e92 | 1465 | |
012aef07 MA |
1466 | g_free(sphb->msi_devs); |
1467 | sphb->msi_devs = NULL; | |
708414f0 MA |
1468 | sphb->msi_devs_num = g_hash_table_size(sphb->msi); |
1469 | if (!sphb->msi_devs_num) { | |
9a321e92 AK |
1470 | return; |
1471 | } | |
708414f0 | 1472 | sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); |
9a321e92 | 1473 | |
708414f0 MA |
1474 | g_hash_table_iter_init(&iter, sphb->msi); |
1475 | for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { | |
1476 | sphb->msi_devs[i].key = *(uint32_t *) key; | |
1477 | sphb->msi_devs[i].value = *(spapr_pci_msi *) value; | |
1478 | } | |
9a321e92 AK |
1479 | } |
1480 | ||
1481 | static int spapr_pci_post_load(void *opaque, int version_id) | |
1482 | { | |
1483 | sPAPRPHBState *sphb = opaque; | |
1484 | gpointer key, value; | |
1485 | int i; | |
1486 | ||
1487 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
1488 | key = g_memdup(&sphb->msi_devs[i].key, | |
1489 | sizeof(sphb->msi_devs[i].key)); | |
1490 | value = g_memdup(&sphb->msi_devs[i].value, | |
1491 | sizeof(sphb->msi_devs[i].value)); | |
1492 | g_hash_table_insert(sphb->msi, key, value); | |
1493 | } | |
012aef07 MA |
1494 | g_free(sphb->msi_devs); |
1495 | sphb->msi_devs = NULL; | |
9a321e92 AK |
1496 | sphb->msi_devs_num = 0; |
1497 | ||
1498 | return 0; | |
1499 | } | |
1500 | ||
1112cf94 DG |
1501 | static const VMStateDescription vmstate_spapr_pci = { |
1502 | .name = "spapr_pci", | |
9a321e92 AK |
1503 | .version_id = 2, |
1504 | .minimum_version_id = 2, | |
1505 | .pre_save = spapr_pci_pre_save, | |
1506 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 1507 | .fields = (VMStateField[]) { |
1112cf94 DG |
1508 | VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), |
1509 | VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), | |
1510 | VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), | |
1511 | VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), | |
1512 | VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), | |
1513 | VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), | |
1112cf94 DG |
1514 | VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, |
1515 | vmstate_spapr_pci_lsi, struct spapr_pci_lsi), | |
9a321e92 AK |
1516 | VMSTATE_INT32(msi_devs_num, sPAPRPHBState), |
1517 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, | |
1518 | vmstate_spapr_pci_msi, spapr_pci_msi_mig), | |
1112cf94 DG |
1519 | VMSTATE_END_OF_LIST() |
1520 | }, | |
1521 | }; | |
1522 | ||
568f0690 DG |
1523 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
1524 | PCIBus *rootbus) | |
1525 | { | |
1526 | sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); | |
1527 | ||
1528 | return sphb->dtbusname; | |
1529 | } | |
1530 | ||
298a9710 DG |
1531 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
1532 | { | |
568f0690 | 1533 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 1534 | DeviceClass *dc = DEVICE_CLASS(klass); |
da6ccee4 | 1535 | sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); |
7454c7af | 1536 | HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); |
298a9710 | 1537 | |
568f0690 | 1538 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 1539 | dc->realize = spapr_phb_realize; |
298a9710 | 1540 | dc->props = spapr_phb_properties; |
eddeed26 | 1541 | dc->reset = spapr_phb_reset; |
1112cf94 | 1542 | dc->vmsd = &vmstate_spapr_pci; |
09aa9a52 AK |
1543 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
1544 | dc->cannot_instantiate_with_device_add_yet = false; | |
da6ccee4 | 1545 | spc->finish_realize = spapr_phb_finish_realize; |
7454c7af MR |
1546 | hp->plug = spapr_phb_hot_plug_child; |
1547 | hp->unplug = spapr_phb_hot_unplug_child; | |
298a9710 | 1548 | } |
3384f95c | 1549 | |
4240abff | 1550 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 1551 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 1552 | .parent = TYPE_PCI_HOST_BRIDGE, |
298a9710 DG |
1553 | .instance_size = sizeof(sPAPRPHBState), |
1554 | .class_init = spapr_phb_class_init, | |
da6ccee4 | 1555 | .class_size = sizeof(sPAPRPHBClass), |
7454c7af MR |
1556 | .interfaces = (InterfaceInfo[]) { |
1557 | { TYPE_HOTPLUG_HANDLER }, | |
1558 | { } | |
1559 | } | |
298a9710 DG |
1560 | }; |
1561 | ||
28e02042 | 1562 | PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) |
298a9710 DG |
1563 | { |
1564 | DeviceState *dev; | |
1565 | ||
8c9f64df | 1566 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
caae58cb | 1567 | qdev_prop_set_uint32(dev, "index", index); |
298a9710 | 1568 | qdev_init_nofail(dev); |
caae58cb DG |
1569 | |
1570 | return PCI_HOST_BRIDGE(dev); | |
3384f95c DG |
1571 | } |
1572 | ||
1d2d9742 ND |
1573 | typedef struct sPAPRFDT { |
1574 | void *fdt; | |
1575 | int node_off; | |
1576 | sPAPRPHBState *sphb; | |
1577 | } sPAPRFDT; | |
1578 | ||
1579 | static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, | |
1580 | void *opaque) | |
1581 | { | |
1582 | PCIBus *sec_bus; | |
1583 | sPAPRFDT *p = opaque; | |
1584 | int offset; | |
1585 | sPAPRFDT s_fdt; | |
1d2d9742 | 1586 | |
e634b89c | 1587 | offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); |
1d2d9742 ND |
1588 | if (!offset) { |
1589 | error_report("Failed to create pci child device tree node"); | |
1590 | return; | |
1591 | } | |
1592 | ||
1593 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
1594 | PCI_HEADER_TYPE_BRIDGE)) { | |
1595 | return; | |
1596 | } | |
1597 | ||
1598 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
1599 | if (!sec_bus) { | |
1600 | return; | |
1601 | } | |
1602 | ||
1603 | s_fdt.fdt = p->fdt; | |
1604 | s_fdt.node_off = offset; | |
1605 | s_fdt.sphb = p->sphb; | |
1606 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
1607 | spapr_populate_pci_devices_dt, | |
1608 | &s_fdt); | |
1609 | } | |
1610 | ||
1611 | static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, | |
1612 | void *opaque) | |
1613 | { | |
1614 | unsigned int *bus_no = opaque; | |
1615 | unsigned int primary = *bus_no; | |
1616 | unsigned int subordinate = 0xff; | |
1617 | PCIBus *sec_bus = NULL; | |
1618 | ||
1619 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
1620 | PCI_HEADER_TYPE_BRIDGE)) { | |
1621 | return; | |
1622 | } | |
1623 | ||
1624 | (*bus_no)++; | |
1625 | pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); | |
1626 | pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); | |
1627 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
1628 | ||
1629 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
1630 | if (!sec_bus) { | |
1631 | return; | |
1632 | } | |
1633 | ||
1634 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); | |
1635 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
1636 | spapr_phb_pci_enumerate_bridge, bus_no); | |
1637 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
1638 | } | |
1639 | ||
1640 | static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) | |
1641 | { | |
1642 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; | |
1643 | unsigned int bus_no = 0; | |
1644 | ||
1645 | pci_for_each_device(bus, pci_bus_num(bus), | |
1646 | spapr_phb_pci_enumerate_bridge, | |
1647 | &bus_no); | |
1648 | ||
1649 | } | |
1650 | ||
e0fdbd7c AK |
1651 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
1652 | uint32_t xics_phandle, | |
1653 | void *fdt) | |
3384f95c | 1654 | { |
62083979 | 1655 | int bus_off, i, j, ret; |
9b7d9284 | 1656 | char nodename[FDT_NAME_MAX]; |
3384f95c | 1657 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
b194df47 AK |
1658 | const uint64_t mmiosize = memory_region_size(&phb->memwindow); |
1659 | const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; | |
1660 | const uint64_t w32size = MIN(w32max, mmiosize); | |
1661 | const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; | |
3384f95c DG |
1662 | struct { |
1663 | uint32_t hi; | |
1664 | uint64_t child; | |
1665 | uint64_t parent; | |
1666 | uint64_t size; | |
c4889f54 | 1667 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
1668 | { |
1669 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
1670 | cpu_to_be64(phb->io_win_addr), | |
1671 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
1672 | }, | |
1673 | { | |
1674 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
1675 | cpu_to_be64(phb->mem_win_addr), | |
b194df47 AK |
1676 | cpu_to_be64(w32size), |
1677 | }, | |
1678 | { | |
1679 | cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), | |
1680 | cpu_to_be64(phb->mem_win_addr + w32size), | |
1681 | cpu_to_be64(w64size) | |
3384f95c DG |
1682 | }, |
1683 | }; | |
b194df47 | 1684 | const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); |
3384f95c DG |
1685 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
1686 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
1687 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
1688 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
ccf9ff85 | 1689 | sPAPRTCETable *tcet; |
1d2d9742 ND |
1690 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; |
1691 | sPAPRFDT s_fdt; | |
3384f95c DG |
1692 | |
1693 | /* Start populating the FDT */ | |
9b7d9284 | 1694 | snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); |
3384f95c DG |
1695 | bus_off = fdt_add_subnode(fdt, 0, nodename); |
1696 | if (bus_off < 0) { | |
1697 | return bus_off; | |
1698 | } | |
1699 | ||
3384f95c DG |
1700 | /* Write PHB properties */ |
1701 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
1702 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
1703 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
1704 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
1705 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
1706 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
1707 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 1708 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 1709 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 1710 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
9dbae977 | 1711 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); |
3384f95c | 1712 | |
4d8d5467 BH |
1713 | /* Build the interrupt-map, this must matches what is done |
1714 | * in pci_spapr_map_irq | |
1715 | */ | |
1716 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
1717 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
1718 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
1719 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
1720 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
1721 | int lsi_num = pci_spapr_swizzle(i, j); | |
1722 | ||
1723 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
1724 | irqmap[1] = 0; | |
1725 | irqmap[2] = 0; | |
1726 | irqmap[3] = cpu_to_be32(j+1); | |
1727 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 1728 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
1729 | irqmap[6] = cpu_to_be32(0x8); |
1730 | } | |
3384f95c | 1731 | } |
3384f95c DG |
1732 | /* Write interrupt map */ |
1733 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 1734 | sizeof(interrupt_map))); |
3384f95c | 1735 | |
ccf9ff85 AK |
1736 | tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); |
1737 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", | |
1738 | tcet->liobn, tcet->bus_offset, | |
1739 | tcet->nb_table << tcet->page_shift); | |
edded454 | 1740 | |
1d2d9742 ND |
1741 | /* Walk the bridges and program the bus numbers*/ |
1742 | spapr_phb_pci_enumerate(phb); | |
1743 | _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); | |
1744 | ||
1745 | /* Populate tree nodes with PCI devices attached */ | |
1746 | s_fdt.fdt = fdt; | |
1747 | s_fdt.node_off = bus_off; | |
1748 | s_fdt.sphb = phb; | |
1749 | pci_for_each_device(bus, pci_bus_num(bus), | |
1750 | spapr_populate_pci_devices_dt, | |
1751 | &s_fdt); | |
1752 | ||
62083979 MR |
1753 | ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), |
1754 | SPAPR_DR_CONNECTOR_TYPE_PCI); | |
1755 | if (ret) { | |
1756 | return ret; | |
1757 | } | |
1758 | ||
3384f95c DG |
1759 | return 0; |
1760 | } | |
298a9710 | 1761 | |
fa28f71b AK |
1762 | void spapr_pci_rtas_init(void) |
1763 | { | |
3a3b8502 AK |
1764 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
1765 | rtas_read_pci_config); | |
1766 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
1767 | rtas_write_pci_config); | |
1768 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
1769 | rtas_ibm_read_pci_config); | |
1770 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
1771 | rtas_ibm_write_pci_config); | |
0ee2c058 | 1772 | if (msi_supported) { |
3a3b8502 AK |
1773 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
1774 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 1775 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
1776 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
1777 | rtas_ibm_change_msi); | |
0ee2c058 | 1778 | } |
ee954280 GS |
1779 | |
1780 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
1781 | "ibm,set-eeh-option", | |
1782 | rtas_ibm_set_eeh_option); | |
1783 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
1784 | "ibm,get-config-addr-info2", | |
1785 | rtas_ibm_get_config_addr_info2); | |
1786 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
1787 | "ibm,read-slot-reset-state2", | |
1788 | rtas_ibm_read_slot_reset_state2); | |
1789 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
1790 | "ibm,set-slot-reset", | |
1791 | rtas_ibm_set_slot_reset); | |
1792 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
1793 | "ibm,configure-pe", | |
1794 | rtas_ibm_configure_pe); | |
1795 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
1796 | "ibm,slot-error-detail", | |
1797 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
1798 | } |
1799 | ||
8c9f64df | 1800 | static void spapr_pci_register_types(void) |
298a9710 DG |
1801 | { |
1802 | type_register_static(&spapr_phb_info); | |
1803 | } | |
8c9f64df AF |
1804 | |
1805 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
1806 | |
1807 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
1808 | { | |
1809 | bool be = *(bool *)opaque; | |
1810 | ||
1811 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
1812 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
1813 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
1814 | &error_abort); | |
1815 | } | |
1816 | return 0; | |
1817 | } | |
1818 | ||
1819 | void spapr_pci_switch_vga(bool big_endian) | |
1820 | { | |
28e02042 | 1821 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
eefaccc0 DG |
1822 | sPAPRPHBState *sphb; |
1823 | ||
1824 | /* | |
1825 | * For backward compatibility with existing guests, we switch | |
1826 | * the endianness of the VGA controller when changing the guest | |
1827 | * interrupt mode | |
1828 | */ | |
1829 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
1830 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
1831 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
1832 | &big_endian); | |
1833 | } | |
1834 | } |