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9fc34ada AK |
1 | /* |
2 | * QEMU sPAPR PCI host for VFIO | |
3 | * | |
4 | * Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, | |
9 | * or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0d75590d | 20 | #include "qemu/osdep.h" |
9fc34ada AK |
21 | #include "hw/ppc/spapr.h" |
22 | #include "hw/pci-host/spapr.h" | |
6319b1da | 23 | #include "hw/pci/msix.h" |
9fc34ada | 24 | #include "linux/vfio.h" |
cf7087db | 25 | #include "hw/vfio/vfio.h" |
9fc34ada AK |
26 | |
27 | static Property spapr_phb_vfio_properties[] = { | |
28 | DEFINE_PROP_INT32("iommu", sPAPRPHBVFIOState, iommugroupid, -1), | |
29 | DEFINE_PROP_END_OF_LIST(), | |
30 | }; | |
31 | ||
32 | static void spapr_phb_vfio_finish_realize(sPAPRPHBState *sphb, Error **errp) | |
33 | { | |
34 | sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb); | |
35 | struct vfio_iommu_spapr_tce_info info = { .argsz = sizeof(info) }; | |
36 | int ret; | |
37 | sPAPRTCETable *tcet; | |
38 | uint32_t liobn = svphb->phb.dma_liobn; | |
39 | ||
40 | if (svphb->iommugroupid == -1) { | |
41 | error_setg(errp, "Wrong IOMMU group ID %d", svphb->iommugroupid); | |
42 | return; | |
43 | } | |
44 | ||
45 | ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid, | |
46 | VFIO_CHECK_EXTENSION, | |
47 | (void *) VFIO_SPAPR_TCE_IOMMU); | |
48 | if (ret != 1) { | |
49 | error_setg_errno(errp, -ret, | |
50 | "spapr-vfio: SPAPR extension is not supported"); | |
51 | return; | |
52 | } | |
53 | ||
54 | ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid, | |
55 | VFIO_IOMMU_SPAPR_TCE_GET_INFO, &info); | |
56 | if (ret) { | |
57 | error_setg_errno(errp, -ret, | |
58 | "spapr-vfio: get info from container failed"); | |
59 | return; | |
60 | } | |
61 | ||
62 | tcet = spapr_tce_new_table(DEVICE(sphb), liobn, info.dma32_window_start, | |
63 | SPAPR_TCE_PAGE_SHIFT, | |
64 | info.dma32_window_size >> SPAPR_TCE_PAGE_SHIFT, | |
65 | true); | |
66 | if (!tcet) { | |
67 | error_setg(errp, "spapr-vfio: failed to create VFIO TCE table"); | |
68 | return; | |
69 | } | |
70 | ||
71 | /* Register default 32bit DMA window */ | |
72 | memory_region_add_subregion(&sphb->iommu_root, tcet->bus_offset, | |
73 | spapr_tce_get_iommu(tcet)); | |
74 | } | |
75 | ||
c1fa017c DG |
76 | bool spapr_phb_eeh_available(sPAPRPHBState *sphb) |
77 | { | |
78 | return vfio_eeh_as_ok(&sphb->iommu_as); | |
79 | } | |
80 | ||
76a9e9f6 | 81 | static void spapr_phb_vfio_eeh_reenable(sPAPRPHBState *sphb) |
aef87d1b | 82 | { |
76a9e9f6 | 83 | vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE); |
aef87d1b GS |
84 | } |
85 | ||
fbb4e983 | 86 | void spapr_phb_vfio_reset(DeviceState *qdev) |
9fc34ada | 87 | { |
aef87d1b GS |
88 | /* |
89 | * The PE might be in frozen state. To reenable the EEH | |
90 | * functionality on it will clean the frozen state, which | |
91 | * ensures that the contained PCI devices will work properly | |
92 | * after reboot. | |
93 | */ | |
76a9e9f6 | 94 | spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev)); |
9fc34ada AK |
95 | } |
96 | ||
fbb4e983 DG |
97 | int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb, |
98 | unsigned int addr, int option) | |
2aad88f4 | 99 | { |
76a9e9f6 | 100 | uint32_t op; |
2aad88f4 GS |
101 | int ret; |
102 | ||
103 | switch (option) { | |
104 | case RTAS_EEH_DISABLE: | |
76a9e9f6 | 105 | op = VFIO_EEH_PE_DISABLE; |
2aad88f4 GS |
106 | break; |
107 | case RTAS_EEH_ENABLE: { | |
108 | PCIHostState *phb; | |
109 | PCIDevice *pdev; | |
110 | ||
111 | /* | |
112 | * The EEH functionality is enabled on basis of PCI device, | |
113 | * instead of PE. We need check the validity of the PCI | |
114 | * device address. | |
115 | */ | |
116 | phb = PCI_HOST_BRIDGE(sphb); | |
117 | pdev = pci_find_device(phb->bus, | |
118 | (addr >> 16) & 0xFF, (addr >> 8) & 0xFF); | |
d76548a9 | 119 | if (!pdev || !object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { |
2aad88f4 GS |
120 | return RTAS_OUT_PARAM_ERROR; |
121 | } | |
122 | ||
76a9e9f6 | 123 | op = VFIO_EEH_PE_ENABLE; |
2aad88f4 GS |
124 | break; |
125 | } | |
126 | case RTAS_EEH_THAW_IO: | |
76a9e9f6 | 127 | op = VFIO_EEH_PE_UNFREEZE_IO; |
2aad88f4 GS |
128 | break; |
129 | case RTAS_EEH_THAW_DMA: | |
76a9e9f6 | 130 | op = VFIO_EEH_PE_UNFREEZE_DMA; |
2aad88f4 GS |
131 | break; |
132 | default: | |
133 | return RTAS_OUT_PARAM_ERROR; | |
134 | } | |
135 | ||
76a9e9f6 | 136 | ret = vfio_eeh_as_op(&sphb->iommu_as, op); |
2aad88f4 GS |
137 | if (ret < 0) { |
138 | return RTAS_OUT_HW_ERROR; | |
139 | } | |
140 | ||
141 | return RTAS_OUT_SUCCESS; | |
142 | } | |
143 | ||
fbb4e983 | 144 | int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state) |
2aad88f4 | 145 | { |
2aad88f4 GS |
146 | int ret; |
147 | ||
76a9e9f6 | 148 | ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE); |
2aad88f4 GS |
149 | if (ret < 0) { |
150 | return RTAS_OUT_PARAM_ERROR; | |
151 | } | |
152 | ||
153 | *state = ret; | |
154 | return RTAS_OUT_SUCCESS; | |
155 | } | |
156 | ||
6319b1da GS |
157 | static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus, |
158 | PCIDevice *pdev, | |
159 | void *opaque) | |
160 | { | |
161 | /* Check if the device is VFIO PCI device */ | |
162 | if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
163 | return; | |
164 | } | |
165 | ||
166 | /* | |
167 | * The MSIx table will be cleaned out by reset. We need | |
168 | * disable it so that it can be reenabled properly. Also, | |
169 | * the cached MSIx table should be cleared as it's not | |
170 | * reflecting the contents in hardware. | |
171 | */ | |
172 | if (msix_enabled(pdev)) { | |
173 | uint16_t flags; | |
174 | ||
175 | flags = pci_host_config_read_common(pdev, | |
176 | pdev->msix_cap + PCI_MSIX_FLAGS, | |
177 | pci_config_size(pdev), 2); | |
178 | flags &= ~PCI_MSIX_FLAGS_ENABLE; | |
179 | pci_host_config_write_common(pdev, | |
180 | pdev->msix_cap + PCI_MSIX_FLAGS, | |
181 | pci_config_size(pdev), flags, 2); | |
182 | } | |
183 | ||
184 | msix_reset(pdev); | |
185 | } | |
186 | ||
187 | static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque) | |
188 | { | |
189 | pci_for_each_device(bus, pci_bus_num(bus), | |
190 | spapr_phb_vfio_eeh_clear_dev_msix, NULL); | |
191 | } | |
192 | ||
193 | static void spapr_phb_vfio_eeh_pre_reset(sPAPRPHBState *sphb) | |
194 | { | |
195 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); | |
196 | ||
197 | pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL); | |
198 | } | |
199 | ||
fbb4e983 | 200 | int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option) |
2aad88f4 | 201 | { |
76a9e9f6 | 202 | uint32_t op; |
2aad88f4 GS |
203 | int ret; |
204 | ||
205 | switch (option) { | |
206 | case RTAS_SLOT_RESET_DEACTIVATE: | |
76a9e9f6 | 207 | op = VFIO_EEH_PE_RESET_DEACTIVATE; |
2aad88f4 GS |
208 | break; |
209 | case RTAS_SLOT_RESET_HOT: | |
6319b1da | 210 | spapr_phb_vfio_eeh_pre_reset(sphb); |
76a9e9f6 | 211 | op = VFIO_EEH_PE_RESET_HOT; |
2aad88f4 GS |
212 | break; |
213 | case RTAS_SLOT_RESET_FUNDAMENTAL: | |
6319b1da | 214 | spapr_phb_vfio_eeh_pre_reset(sphb); |
76a9e9f6 | 215 | op = VFIO_EEH_PE_RESET_FUNDAMENTAL; |
2aad88f4 GS |
216 | break; |
217 | default: | |
218 | return RTAS_OUT_PARAM_ERROR; | |
219 | } | |
220 | ||
76a9e9f6 | 221 | ret = vfio_eeh_as_op(&sphb->iommu_as, op); |
2aad88f4 GS |
222 | if (ret < 0) { |
223 | return RTAS_OUT_HW_ERROR; | |
224 | } | |
225 | ||
226 | return RTAS_OUT_SUCCESS; | |
227 | } | |
228 | ||
fbb4e983 | 229 | int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb) |
2aad88f4 | 230 | { |
2aad88f4 GS |
231 | int ret; |
232 | ||
76a9e9f6 | 233 | ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE); |
2aad88f4 GS |
234 | if (ret < 0) { |
235 | return RTAS_OUT_PARAM_ERROR; | |
236 | } | |
237 | ||
238 | return RTAS_OUT_SUCCESS; | |
239 | } | |
240 | ||
9fc34ada AK |
241 | static void spapr_phb_vfio_class_init(ObjectClass *klass, void *data) |
242 | { | |
243 | DeviceClass *dc = DEVICE_CLASS(klass); | |
244 | sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); | |
245 | ||
246 | dc->props = spapr_phb_vfio_properties; | |
9fc34ada AK |
247 | spc->finish_realize = spapr_phb_vfio_finish_realize; |
248 | } | |
249 | ||
250 | static const TypeInfo spapr_phb_vfio_info = { | |
251 | .name = TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE, | |
252 | .parent = TYPE_SPAPR_PCI_HOST_BRIDGE, | |
253 | .instance_size = sizeof(sPAPRPHBVFIOState), | |
254 | .class_init = spapr_phb_vfio_class_init, | |
255 | .class_size = sizeof(sPAPRPHBClass), | |
256 | }; | |
257 | ||
258 | static void spapr_pci_vfio_register_types(void) | |
259 | { | |
260 | type_register_static(&spapr_phb_vfio_info); | |
261 | } | |
262 | ||
263 | type_init(spapr_pci_vfio_register_types) |