]>
Commit | Line | Data |
---|---|---|
12f42174 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * RTAS Real Time Clock | |
5 | * | |
6 | * Copyright (c) 2010-2011 David Gibson, IBM Corporation. | |
7 | * Copyright 2014 David Gibson, Red Hat. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
26 | * | |
27 | */ | |
28 | #include "cpu.h" | |
e0cf11f3 | 29 | #include "qemu/timer.h" |
f01c5d84 | 30 | #include "sysemu/sysemu.h" |
12f42174 DG |
31 | #include "hw/ppc/spapr.h" |
32 | #include "qapi-event.h" | |
33 | ||
28df36a1 DG |
34 | #define SPAPR_RTC(obj) \ |
35 | OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) | |
36 | ||
37 | typedef struct sPAPRRTCState sPAPRRTCState; | |
38 | struct sPAPRRTCState { | |
39 | /*< private >*/ | |
40 | SysBusDevice parent_obj; | |
880ae7de | 41 | int64_t ns_offset; |
28df36a1 DG |
42 | }; |
43 | ||
28df36a1 | 44 | void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns) |
e5dad1d7 | 45 | { |
28df36a1 | 46 | sPAPRRTCState *rtc = SPAPR_RTC(dev); |
f01c5d84 | 47 | int64_t host_ns = qemu_clock_get_ns(rtc_clock); |
880ae7de | 48 | int64_t guest_ns; |
f01c5d84 DG |
49 | time_t guest_s; |
50 | ||
28df36a1 DG |
51 | assert(rtc); |
52 | ||
880ae7de | 53 | guest_ns = host_ns + rtc->ns_offset; |
13566fe3 | 54 | guest_s = guest_ns / NANOSECONDS_PER_SECOND; |
f01c5d84 DG |
55 | |
56 | if (tm) { | |
57 | gmtime_r(&guest_s, tm); | |
58 | } | |
e5dad1d7 | 59 | if (ns) { |
880ae7de | 60 | *ns = guest_ns; |
e5dad1d7 DG |
61 | } |
62 | } | |
63 | ||
880ae7de DG |
64 | int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset) |
65 | { | |
66 | sPAPRRTCState *rtc; | |
67 | ||
68 | if (!dev) { | |
69 | return -ENODEV; | |
70 | } | |
71 | ||
72 | rtc = SPAPR_RTC(dev); | |
73 | ||
13566fe3 | 74 | rtc->ns_offset = legacy_offset * NANOSECONDS_PER_SECOND; |
880ae7de DG |
75 | |
76 | return 0; | |
77 | } | |
78 | ||
28e02042 | 79 | static void rtas_get_time_of_day(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
12f42174 DG |
80 | uint32_t token, uint32_t nargs, |
81 | target_ulong args, | |
82 | uint32_t nret, target_ulong rets) | |
83 | { | |
84 | struct tm tm; | |
e5dad1d7 | 85 | uint32_t ns; |
12f42174 | 86 | |
bbade206 | 87 | if ((nargs != 0) || (nret != 8)) { |
12f42174 DG |
88 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
89 | return; | |
90 | } | |
91 | ||
28df36a1 DG |
92 | if (!spapr->rtc) { |
93 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); | |
94 | return; | |
95 | } | |
96 | ||
97 | spapr_rtc_read(spapr->rtc, &tm, &ns); | |
12f42174 DG |
98 | |
99 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
100 | rtas_st(rets, 1, tm.tm_year + 1900); | |
101 | rtas_st(rets, 2, tm.tm_mon + 1); | |
102 | rtas_st(rets, 3, tm.tm_mday); | |
103 | rtas_st(rets, 4, tm.tm_hour); | |
104 | rtas_st(rets, 5, tm.tm_min); | |
105 | rtas_st(rets, 6, tm.tm_sec); | |
e5dad1d7 | 106 | rtas_st(rets, 7, ns); |
12f42174 DG |
107 | } |
108 | ||
28e02042 | 109 | static void rtas_set_time_of_day(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
12f42174 DG |
110 | uint32_t token, uint32_t nargs, |
111 | target_ulong args, | |
112 | uint32_t nret, target_ulong rets) | |
113 | { | |
880ae7de | 114 | sPAPRRTCState *rtc; |
12f42174 | 115 | struct tm tm; |
f01c5d84 DG |
116 | time_t new_s; |
117 | int64_t host_ns; | |
12f42174 | 118 | |
bbade206 DG |
119 | if ((nargs != 7) || (nret != 1)) { |
120 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
121 | return; | |
122 | } | |
123 | ||
28df36a1 DG |
124 | if (!spapr->rtc) { |
125 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); | |
126 | return; | |
127 | } | |
128 | ||
12f42174 DG |
129 | tm.tm_year = rtas_ld(args, 0) - 1900; |
130 | tm.tm_mon = rtas_ld(args, 1) - 1; | |
131 | tm.tm_mday = rtas_ld(args, 2); | |
132 | tm.tm_hour = rtas_ld(args, 3); | |
133 | tm.tm_min = rtas_ld(args, 4); | |
134 | tm.tm_sec = rtas_ld(args, 5); | |
135 | ||
f01c5d84 DG |
136 | new_s = mktimegm(&tm); |
137 | if (new_s == -1) { | |
138 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
139 | return; | |
140 | } | |
141 | ||
142 | /* Generate a monitor event for the change */ | |
12f42174 | 143 | qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort); |
f01c5d84 | 144 | |
880ae7de DG |
145 | rtc = SPAPR_RTC(spapr->rtc); |
146 | ||
f01c5d84 DG |
147 | host_ns = qemu_clock_get_ns(rtc_clock); |
148 | ||
13566fe3 | 149 | rtc->ns_offset = (new_s * NANOSECONDS_PER_SECOND) - host_ns; |
12f42174 DG |
150 | |
151 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
152 | } | |
153 | ||
74e5ae28 DG |
154 | static void spapr_rtc_qom_date(Object *obj, struct tm *current_tm, Error **errp) |
155 | { | |
156 | spapr_rtc_read(DEVICE(obj), current_tm, NULL); | |
157 | } | |
158 | ||
28df36a1 | 159 | static void spapr_rtc_realize(DeviceState *dev, Error **errp) |
12f42174 | 160 | { |
880ae7de | 161 | sPAPRRTCState *rtc = SPAPR_RTC(dev); |
f01c5d84 DG |
162 | struct tm tm; |
163 | time_t host_s; | |
164 | int64_t rtc_ns; | |
165 | ||
166 | /* Initialize the RTAS RTC from host time */ | |
167 | ||
168 | qemu_get_timedate(&tm, 0); | |
169 | host_s = mktimegm(&tm); | |
170 | rtc_ns = qemu_clock_get_ns(rtc_clock); | |
13566fe3 | 171 | rtc->ns_offset = host_s * NANOSECONDS_PER_SECOND - rtc_ns; |
74e5ae28 DG |
172 | |
173 | object_property_add_tm(OBJECT(rtc), "date", spapr_rtc_qom_date, NULL); | |
28df36a1 DG |
174 | } |
175 | ||
880ae7de DG |
176 | static const VMStateDescription vmstate_spapr_rtc = { |
177 | .name = "spapr/rtc", | |
178 | .version_id = 1, | |
179 | .minimum_version_id = 1, | |
180 | .fields = (VMStateField[]) { | |
181 | VMSTATE_INT64(ns_offset, sPAPRRTCState), | |
182 | VMSTATE_END_OF_LIST() | |
183 | }, | |
184 | }; | |
185 | ||
28df36a1 DG |
186 | static void spapr_rtc_class_init(ObjectClass *oc, void *data) |
187 | { | |
188 | DeviceClass *dc = DEVICE_CLASS(oc); | |
189 | ||
190 | dc->realize = spapr_rtc_realize; | |
880ae7de | 191 | dc->vmsd = &vmstate_spapr_rtc; |
f01c5d84 | 192 | |
12f42174 DG |
193 | spapr_rtas_register(RTAS_GET_TIME_OF_DAY, "get-time-of-day", |
194 | rtas_get_time_of_day); | |
195 | spapr_rtas_register(RTAS_SET_TIME_OF_DAY, "set-time-of-day", | |
196 | rtas_set_time_of_day); | |
197 | } | |
28df36a1 DG |
198 | |
199 | static const TypeInfo spapr_rtc_info = { | |
200 | .name = TYPE_SPAPR_RTC, | |
201 | .parent = TYPE_SYS_BUS_DEVICE, | |
202 | .instance_size = sizeof(sPAPRRTCState), | |
28df36a1 DG |
203 | .class_init = spapr_rtc_class_init, |
204 | }; | |
205 | ||
206 | static void spapr_rtc_register_types(void) | |
207 | { | |
208 | type_register_static(&spapr_rtc_info); | |
209 | } | |
210 | type_init(spapr_rtc_register_types) |