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12f42174 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * RTAS Real Time Clock | |
5 | * | |
6 | * Copyright (c) 2010-2011 David Gibson, IBM Corporation. | |
7 | * Copyright 2014 David Gibson, Red Hat. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
12f42174 | 26 | */ |
e688df6b | 27 | |
0d75590d | 28 | #include "qemu/osdep.h" |
a8d25326 | 29 | #include "qemu-common.h" |
12f42174 | 30 | #include "cpu.h" |
e0cf11f3 | 31 | #include "qemu/timer.h" |
f01c5d84 | 32 | #include "sysemu/sysemu.h" |
12f42174 | 33 | #include "hw/ppc/spapr.h" |
e688df6b | 34 | #include "qapi/error.h" |
b0227cdb | 35 | #include "qapi/qapi-events-misc-target.h" |
f348b6d1 | 36 | #include "qemu/cutils.h" |
0b8fa32f | 37 | #include "qemu/module.h" |
12f42174 | 38 | |
ce2918cb | 39 | void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns) |
e5dad1d7 | 40 | { |
f01c5d84 | 41 | int64_t host_ns = qemu_clock_get_ns(rtc_clock); |
880ae7de | 42 | int64_t guest_ns; |
f01c5d84 DG |
43 | time_t guest_s; |
44 | ||
28df36a1 DG |
45 | assert(rtc); |
46 | ||
880ae7de | 47 | guest_ns = host_ns + rtc->ns_offset; |
13566fe3 | 48 | guest_s = guest_ns / NANOSECONDS_PER_SECOND; |
f01c5d84 DG |
49 | |
50 | if (tm) { | |
51 | gmtime_r(&guest_s, tm); | |
52 | } | |
e5dad1d7 | 53 | if (ns) { |
880ae7de | 54 | *ns = guest_ns; |
e5dad1d7 DG |
55 | } |
56 | } | |
57 | ||
ce2918cb | 58 | int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset) |
880ae7de | 59 | { |
147ff807 | 60 | if (!rtc) { |
880ae7de DG |
61 | return -ENODEV; |
62 | } | |
63 | ||
13566fe3 | 64 | rtc->ns_offset = legacy_offset * NANOSECONDS_PER_SECOND; |
880ae7de DG |
65 | |
66 | return 0; | |
67 | } | |
68 | ||
ce2918cb | 69 | static void rtas_get_time_of_day(PowerPCCPU *cpu, SpaprMachineState *spapr, |
12f42174 DG |
70 | uint32_t token, uint32_t nargs, |
71 | target_ulong args, | |
72 | uint32_t nret, target_ulong rets) | |
73 | { | |
74 | struct tm tm; | |
e5dad1d7 | 75 | uint32_t ns; |
12f42174 | 76 | |
bbade206 | 77 | if ((nargs != 0) || (nret != 8)) { |
12f42174 DG |
78 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
79 | return; | |
80 | } | |
81 | ||
147ff807 | 82 | spapr_rtc_read(&spapr->rtc, &tm, &ns); |
12f42174 DG |
83 | |
84 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
85 | rtas_st(rets, 1, tm.tm_year + 1900); | |
86 | rtas_st(rets, 2, tm.tm_mon + 1); | |
87 | rtas_st(rets, 3, tm.tm_mday); | |
88 | rtas_st(rets, 4, tm.tm_hour); | |
89 | rtas_st(rets, 5, tm.tm_min); | |
90 | rtas_st(rets, 6, tm.tm_sec); | |
e5dad1d7 | 91 | rtas_st(rets, 7, ns); |
12f42174 DG |
92 | } |
93 | ||
ce2918cb | 94 | static void rtas_set_time_of_day(PowerPCCPU *cpu, SpaprMachineState *spapr, |
12f42174 DG |
95 | uint32_t token, uint32_t nargs, |
96 | target_ulong args, | |
97 | uint32_t nret, target_ulong rets) | |
98 | { | |
ce2918cb | 99 | SpaprRtcState *rtc = &spapr->rtc; |
12f42174 | 100 | struct tm tm; |
f01c5d84 DG |
101 | time_t new_s; |
102 | int64_t host_ns; | |
12f42174 | 103 | |
bbade206 DG |
104 | if ((nargs != 7) || (nret != 1)) { |
105 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
106 | return; | |
107 | } | |
108 | ||
12f42174 DG |
109 | tm.tm_year = rtas_ld(args, 0) - 1900; |
110 | tm.tm_mon = rtas_ld(args, 1) - 1; | |
111 | tm.tm_mday = rtas_ld(args, 2); | |
112 | tm.tm_hour = rtas_ld(args, 3); | |
113 | tm.tm_min = rtas_ld(args, 4); | |
114 | tm.tm_sec = rtas_ld(args, 5); | |
115 | ||
f01c5d84 DG |
116 | new_s = mktimegm(&tm); |
117 | if (new_s == -1) { | |
118 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
119 | return; | |
120 | } | |
121 | ||
122 | /* Generate a monitor event for the change */ | |
3ab72385 | 123 | qapi_event_send_rtc_change(qemu_timedate_diff(&tm)); |
f01c5d84 DG |
124 | |
125 | host_ns = qemu_clock_get_ns(rtc_clock); | |
126 | ||
13566fe3 | 127 | rtc->ns_offset = (new_s * NANOSECONDS_PER_SECOND) - host_ns; |
12f42174 DG |
128 | |
129 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
130 | } | |
131 | ||
74e5ae28 DG |
132 | static void spapr_rtc_qom_date(Object *obj, struct tm *current_tm, Error **errp) |
133 | { | |
147ff807 | 134 | spapr_rtc_read(SPAPR_RTC(obj), current_tm, NULL); |
74e5ae28 DG |
135 | } |
136 | ||
28df36a1 | 137 | static void spapr_rtc_realize(DeviceState *dev, Error **errp) |
12f42174 | 138 | { |
ce2918cb | 139 | SpaprRtcState *rtc = SPAPR_RTC(dev); |
f01c5d84 DG |
140 | struct tm tm; |
141 | time_t host_s; | |
142 | int64_t rtc_ns; | |
143 | ||
144 | /* Initialize the RTAS RTC from host time */ | |
145 | ||
146 | qemu_get_timedate(&tm, 0); | |
147 | host_s = mktimegm(&tm); | |
148 | rtc_ns = qemu_clock_get_ns(rtc_clock); | |
13566fe3 | 149 | rtc->ns_offset = host_s * NANOSECONDS_PER_SECOND - rtc_ns; |
74e5ae28 DG |
150 | |
151 | object_property_add_tm(OBJECT(rtc), "date", spapr_rtc_qom_date, NULL); | |
28df36a1 DG |
152 | } |
153 | ||
880ae7de DG |
154 | static const VMStateDescription vmstate_spapr_rtc = { |
155 | .name = "spapr/rtc", | |
156 | .version_id = 1, | |
157 | .minimum_version_id = 1, | |
158 | .fields = (VMStateField[]) { | |
ce2918cb | 159 | VMSTATE_INT64(ns_offset, SpaprRtcState), |
880ae7de DG |
160 | VMSTATE_END_OF_LIST() |
161 | }, | |
162 | }; | |
163 | ||
28df36a1 DG |
164 | static void spapr_rtc_class_init(ObjectClass *oc, void *data) |
165 | { | |
166 | DeviceClass *dc = DEVICE_CLASS(oc); | |
167 | ||
168 | dc->realize = spapr_rtc_realize; | |
880ae7de | 169 | dc->vmsd = &vmstate_spapr_rtc; |
8ccccff9 TH |
170 | /* Reason: This is an internal device only for handling the hypercalls */ |
171 | dc->user_creatable = false; | |
f01c5d84 | 172 | |
12f42174 DG |
173 | spapr_rtas_register(RTAS_GET_TIME_OF_DAY, "get-time-of-day", |
174 | rtas_get_time_of_day); | |
175 | spapr_rtas_register(RTAS_SET_TIME_OF_DAY, "set-time-of-day", | |
176 | rtas_set_time_of_day); | |
177 | } | |
28df36a1 DG |
178 | |
179 | static const TypeInfo spapr_rtc_info = { | |
180 | .name = TYPE_SPAPR_RTC, | |
147ff807 | 181 | .parent = TYPE_DEVICE, |
ce2918cb | 182 | .instance_size = sizeof(SpaprRtcState), |
28df36a1 DG |
183 | .class_init = spapr_rtc_class_init, |
184 | }; | |
185 | ||
186 | static void spapr_rtc_register_types(void) | |
187 | { | |
188 | type_register_static(&spapr_rtc_info); | |
189 | } | |
190 | type_init(spapr_rtc_register_types) |