]>
Commit | Line | Data |
---|---|---|
4040ab72 DG |
1 | /* |
2 | * QEMU sPAPR VIO code | |
3 | * | |
4 | * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com> | |
5 | * Based on the s390 virtio bus code: | |
6 | * Copyright (c) 2009 Alexander Graf <agraf@suse.de> | |
7 | * | |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
19 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
0d75590d | 22 | #include "qemu/osdep.h" |
ce9863b7 | 23 | #include "qemu/error-report.h" |
da34e65c | 24 | #include "qapi/error.h" |
efe2add7 | 25 | #include "qapi/visitor.h" |
64552b6b | 26 | #include "hw/irq.h" |
03dd024f | 27 | #include "qemu/log.h" |
83c9f4ca | 28 | #include "hw/loader.h" |
4040ab72 DG |
29 | #include "elf.h" |
30 | #include "hw/sysbus.h" | |
9c17d615 PB |
31 | #include "sysemu/kvm.h" |
32 | #include "sysemu/device_tree.h" | |
b45d63b6 | 33 | #include "kvm_ppc.h" |
d6454270 | 34 | #include "migration/vmstate.h" |
efe2add7 | 35 | #include "sysemu/qtest.h" |
4040ab72 | 36 | |
0d09e41a PB |
37 | #include "hw/ppc/spapr.h" |
38 | #include "hw/ppc/spapr_vio.h" | |
bf5a6696 | 39 | #include "hw/ppc/fdt.h" |
7ab6a501 | 40 | #include "trace.h" |
4040ab72 | 41 | |
4040ab72 | 42 | #include <libfdt.h> |
4040ab72 | 43 | |
82cffa2e CLG |
44 | #define SPAPR_VIO_REG_BASE 0x71000000 |
45 | ||
c4eda5b7 DG |
46 | static char *spapr_vio_get_dev_name(DeviceState *qdev) |
47 | { | |
ce2918cb DG |
48 | SpaprVioDevice *dev = VIO_SPAPR_DEVICE(qdev); |
49 | SpaprVioDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev); | |
c4eda5b7 DG |
50 | |
51 | /* Device tree style name device@reg */ | |
9be38598 | 52 | return g_strdup_printf("%s@%x", pc->dt_name, dev->reg); |
c4eda5b7 DG |
53 | } |
54 | ||
55 | static void spapr_vio_bus_class_init(ObjectClass *klass, void *data) | |
56 | { | |
57 | BusClass *k = BUS_CLASS(klass); | |
58 | ||
59 | k->get_dev_path = spapr_vio_get_dev_name; | |
5a06393f | 60 | k->get_fw_dev_path = spapr_vio_get_dev_name; |
c4eda5b7 DG |
61 | } |
62 | ||
0d936928 AL |
63 | static const TypeInfo spapr_vio_bus_info = { |
64 | .name = TYPE_SPAPR_VIO_BUS, | |
65 | .parent = TYPE_BUS, | |
c4eda5b7 | 66 | .class_init = spapr_vio_bus_class_init, |
ce2918cb | 67 | .instance_size = sizeof(SpaprVioBus), |
4040ab72 DG |
68 | }; |
69 | ||
ce2918cb | 70 | SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg) |
4040ab72 | 71 | { |
0866aca1 | 72 | BusChild *kid; |
ce2918cb | 73 | SpaprVioDevice *dev = NULL; |
4040ab72 | 74 | |
0866aca1 | 75 | QTAILQ_FOREACH(kid, &bus->bus.children, sibling) { |
ce2918cb | 76 | dev = (SpaprVioDevice *)kid->child; |
4040ab72 | 77 | if (dev->reg == reg) { |
5435352c | 78 | return dev; |
4040ab72 DG |
79 | } |
80 | } | |
81 | ||
5435352c | 82 | return NULL; |
4040ab72 DG |
83 | } |
84 | ||
ce2918cb | 85 | static int vio_make_devnode(SpaprVioDevice *dev, |
4040ab72 DG |
86 | void *fdt) |
87 | { | |
ce2918cb | 88 | SpaprVioDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev); |
1e34d859 ME |
89 | int vdevice_off, node_off, ret; |
90 | char *dt_name; | |
4040ab72 DG |
91 | |
92 | vdevice_off = fdt_path_offset(fdt, "/vdevice"); | |
93 | if (vdevice_off < 0) { | |
94 | return vdevice_off; | |
95 | } | |
96 | ||
c4eda5b7 | 97 | dt_name = spapr_vio_get_dev_name(DEVICE(dev)); |
1e34d859 | 98 | node_off = fdt_add_subnode(fdt, vdevice_off, dt_name); |
4ecf8aa5 | 99 | g_free(dt_name); |
4040ab72 DG |
100 | if (node_off < 0) { |
101 | return node_off; | |
102 | } | |
103 | ||
104 | ret = fdt_setprop_cell(fdt, node_off, "reg", dev->reg); | |
105 | if (ret < 0) { | |
106 | return ret; | |
107 | } | |
108 | ||
3954d33a | 109 | if (pc->dt_type) { |
4040ab72 | 110 | ret = fdt_setprop_string(fdt, node_off, "device_type", |
3954d33a | 111 | pc->dt_type); |
4040ab72 DG |
112 | if (ret < 0) { |
113 | return ret; | |
114 | } | |
115 | } | |
116 | ||
3954d33a | 117 | if (pc->dt_compatible) { |
4040ab72 | 118 | ret = fdt_setprop_string(fdt, node_off, "compatible", |
3954d33a | 119 | pc->dt_compatible); |
4040ab72 DG |
120 | if (ret < 0) { |
121 | return ret; | |
122 | } | |
123 | } | |
124 | ||
a307d594 | 125 | if (dev->irq) { |
bb2d8ab6 | 126 | uint32_t ints_prop[2]; |
00dc738d | 127 | |
5c7adcf4 | 128 | spapr_dt_irq(ints_prop, dev->irq, false); |
00dc738d DG |
129 | ret = fdt_setprop(fdt, node_off, "interrupts", ints_prop, |
130 | sizeof(ints_prop)); | |
131 | if (ret < 0) { | |
132 | return ret; | |
133 | } | |
134 | } | |
135 | ||
2b7dc949 | 136 | ret = spapr_tcet_dma_dt(fdt, node_off, "ibm,my-dma-window", dev->tcet); |
ad0ebb91 DG |
137 | if (ret < 0) { |
138 | return ret; | |
ee86dfee DG |
139 | } |
140 | ||
3954d33a AL |
141 | if (pc->devnode) { |
142 | ret = (pc->devnode)(dev, fdt, node_off); | |
4040ab72 DG |
143 | if (ret < 0) { |
144 | return ret; | |
145 | } | |
146 | } | |
147 | ||
148 | return node_off; | |
149 | } | |
4040ab72 | 150 | |
b45d63b6 BH |
151 | /* |
152 | * CRQ handling | |
153 | */ | |
ce2918cb | 154 | static target_ulong h_reg_crq(PowerPCCPU *cpu, SpaprMachineState *spapr, |
b45d63b6 BH |
155 | target_ulong opcode, target_ulong *args) |
156 | { | |
157 | target_ulong reg = args[0]; | |
158 | target_ulong queue_addr = args[1]; | |
159 | target_ulong queue_len = args[2]; | |
ce2918cb | 160 | SpaprVioDevice *dev = spapr_vio_find_by_reg(spapr->vio_bus, reg); |
b45d63b6 BH |
161 | |
162 | if (!dev) { | |
d9599c92 | 163 | hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); |
b45d63b6 BH |
164 | return H_PARAMETER; |
165 | } | |
166 | ||
167 | /* We can't grok a queue size bigger than 256M for now */ | |
168 | if (queue_len < 0x1000 || queue_len > 0x10000000) { | |
d9599c92 DG |
169 | hcall_dprintf("Queue size too small or too big (0x" TARGET_FMT_lx |
170 | ")\n", queue_len); | |
b45d63b6 BH |
171 | return H_PARAMETER; |
172 | } | |
173 | ||
174 | /* Check queue alignment */ | |
175 | if (queue_addr & 0xfff) { | |
d9599c92 | 176 | hcall_dprintf("Queue not aligned (0x" TARGET_FMT_lx ")\n", queue_addr); |
b45d63b6 BH |
177 | return H_PARAMETER; |
178 | } | |
179 | ||
180 | /* Check if device supports CRQs */ | |
181 | if (!dev->crq.SendFunc) { | |
8e01f355 | 182 | hcall_dprintf("Device does not support CRQ\n"); |
b45d63b6 BH |
183 | return H_NOT_FOUND; |
184 | } | |
185 | ||
b45d63b6 BH |
186 | /* Already a queue ? */ |
187 | if (dev->crq.qsize) { | |
8e01f355 | 188 | hcall_dprintf("CRQ already registered\n"); |
b45d63b6 BH |
189 | return H_RESOURCE; |
190 | } | |
191 | dev->crq.qladdr = queue_addr; | |
192 | dev->crq.qsize = queue_len; | |
193 | dev->crq.qnext = 0; | |
194 | ||
7ab6a501 | 195 | trace_spapr_vio_h_reg_crq(reg, queue_addr, queue_len); |
b45d63b6 BH |
196 | return H_SUCCESS; |
197 | } | |
198 | ||
ce2918cb | 199 | static target_ulong free_crq(SpaprVioDevice *dev) |
8e01f355 DG |
200 | { |
201 | dev->crq.qladdr = 0; | |
202 | dev->crq.qsize = 0; | |
203 | dev->crq.qnext = 0; | |
204 | ||
7ab6a501 | 205 | trace_spapr_vio_free_crq(dev->reg); |
8e01f355 DG |
206 | |
207 | return H_SUCCESS; | |
208 | } | |
209 | ||
ce2918cb | 210 | static target_ulong h_free_crq(PowerPCCPU *cpu, SpaprMachineState *spapr, |
b45d63b6 BH |
211 | target_ulong opcode, target_ulong *args) |
212 | { | |
213 | target_ulong reg = args[0]; | |
ce2918cb | 214 | SpaprVioDevice *dev = spapr_vio_find_by_reg(spapr->vio_bus, reg); |
b45d63b6 BH |
215 | |
216 | if (!dev) { | |
d9599c92 | 217 | hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); |
b45d63b6 BH |
218 | return H_PARAMETER; |
219 | } | |
220 | ||
8e01f355 | 221 | return free_crq(dev); |
b45d63b6 BH |
222 | } |
223 | ||
ce2918cb | 224 | static target_ulong h_send_crq(PowerPCCPU *cpu, SpaprMachineState *spapr, |
b45d63b6 BH |
225 | target_ulong opcode, target_ulong *args) |
226 | { | |
227 | target_ulong reg = args[0]; | |
228 | target_ulong msg_hi = args[1]; | |
229 | target_ulong msg_lo = args[2]; | |
ce2918cb | 230 | SpaprVioDevice *dev = spapr_vio_find_by_reg(spapr->vio_bus, reg); |
b45d63b6 BH |
231 | uint64_t crq_mangle[2]; |
232 | ||
233 | if (!dev) { | |
d9599c92 | 234 | hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); |
b45d63b6 BH |
235 | return H_PARAMETER; |
236 | } | |
237 | crq_mangle[0] = cpu_to_be64(msg_hi); | |
238 | crq_mangle[1] = cpu_to_be64(msg_lo); | |
239 | ||
240 | if (dev->crq.SendFunc) { | |
241 | return dev->crq.SendFunc(dev, (uint8_t *)crq_mangle); | |
242 | } | |
243 | ||
244 | return H_HARDWARE; | |
245 | } | |
246 | ||
ce2918cb | 247 | static target_ulong h_enable_crq(PowerPCCPU *cpu, SpaprMachineState *spapr, |
b45d63b6 BH |
248 | target_ulong opcode, target_ulong *args) |
249 | { | |
250 | target_ulong reg = args[0]; | |
ce2918cb | 251 | SpaprVioDevice *dev = spapr_vio_find_by_reg(spapr->vio_bus, reg); |
b45d63b6 BH |
252 | |
253 | if (!dev) { | |
d9599c92 | 254 | hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); |
b45d63b6 BH |
255 | return H_PARAMETER; |
256 | } | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | /* Returns negative error, 0 success, or positive: queue full */ | |
ce2918cb | 262 | int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq) |
b45d63b6 BH |
263 | { |
264 | int rc; | |
265 | uint8_t byte; | |
266 | ||
267 | if (!dev->crq.qsize) { | |
ce9863b7 | 268 | error_report("spapr_vio_send_creq on uninitialized queue"); |
b45d63b6 BH |
269 | return -1; |
270 | } | |
271 | ||
272 | /* Maybe do a fast path for KVM just writing to the pages */ | |
ad0ebb91 | 273 | rc = spapr_vio_dma_read(dev, dev->crq.qladdr + dev->crq.qnext, &byte, 1); |
b45d63b6 BH |
274 | if (rc) { |
275 | return rc; | |
276 | } | |
277 | if (byte != 0) { | |
278 | return 1; | |
279 | } | |
280 | ||
ad0ebb91 | 281 | rc = spapr_vio_dma_write(dev, dev->crq.qladdr + dev->crq.qnext + 8, |
b45d63b6 BH |
282 | &crq[8], 8); |
283 | if (rc) { | |
284 | return rc; | |
285 | } | |
286 | ||
287 | kvmppc_eieio(); | |
288 | ||
ad0ebb91 | 289 | rc = spapr_vio_dma_write(dev, dev->crq.qladdr + dev->crq.qnext, crq, 8); |
b45d63b6 BH |
290 | if (rc) { |
291 | return rc; | |
292 | } | |
293 | ||
294 | dev->crq.qnext = (dev->crq.qnext + 16) % dev->crq.qsize; | |
295 | ||
296 | if (dev->signal_state & 1) { | |
a307d594 | 297 | qemu_irq_pulse(spapr_vio_qirq(dev)); |
b45d63b6 BH |
298 | } |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
08942ac1 BH |
303 | /* "quiesce" handling */ |
304 | ||
ce2918cb | 305 | static void spapr_vio_quiesce_one(SpaprVioDevice *dev) |
08942ac1 | 306 | { |
2b7dc949 | 307 | if (dev->tcet) { |
a83000f5 | 308 | device_reset(DEVICE(dev->tcet)); |
08942ac1 | 309 | } |
4dd96f24 | 310 | free_crq(dev); |
08942ac1 BH |
311 | } |
312 | ||
ce2918cb | 313 | void spapr_vio_set_bypass(SpaprVioDevice *dev, bool bypass) |
ee9a569a AK |
314 | { |
315 | if (!dev->tcet) { | |
316 | return; | |
317 | } | |
318 | ||
319 | memory_region_set_enabled(&dev->mrbypass, bypass); | |
320 | memory_region_set_enabled(spapr_tce_get_iommu(dev->tcet), !bypass); | |
321 | ||
322 | dev->tcet->bypass = bypass; | |
323 | } | |
324 | ||
ce2918cb | 325 | static void rtas_set_tce_bypass(PowerPCCPU *cpu, SpaprMachineState *spapr, |
210b580b | 326 | uint32_t token, |
08942ac1 BH |
327 | uint32_t nargs, target_ulong args, |
328 | uint32_t nret, target_ulong rets) | |
329 | { | |
ce2918cb DG |
330 | SpaprVioBus *bus = spapr->vio_bus; |
331 | SpaprVioDevice *dev; | |
08942ac1 BH |
332 | uint32_t unit, enable; |
333 | ||
334 | if (nargs != 2) { | |
a64d325d | 335 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
08942ac1 BH |
336 | return; |
337 | } | |
338 | unit = rtas_ld(args, 0); | |
339 | enable = rtas_ld(args, 1); | |
340 | dev = spapr_vio_find_by_reg(bus, unit); | |
341 | if (!dev) { | |
a64d325d | 342 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
08942ac1 BH |
343 | return; |
344 | } | |
ad0ebb91 | 345 | |
2b7dc949 | 346 | if (!dev->tcet) { |
a64d325d | 347 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
53724ee5 | 348 | return; |
08942ac1 BH |
349 | } |
350 | ||
ee9a569a | 351 | spapr_vio_set_bypass(dev, !!enable); |
53724ee5 | 352 | |
a64d325d | 353 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
08942ac1 BH |
354 | } |
355 | ||
ce2918cb | 356 | static void rtas_quiesce(PowerPCCPU *cpu, SpaprMachineState *spapr, |
210b580b | 357 | uint32_t token, |
08942ac1 BH |
358 | uint32_t nargs, target_ulong args, |
359 | uint32_t nret, target_ulong rets) | |
360 | { | |
ce2918cb | 361 | SpaprVioBus *bus = spapr->vio_bus; |
0866aca1 | 362 | BusChild *kid; |
ce2918cb | 363 | SpaprVioDevice *dev = NULL; |
08942ac1 BH |
364 | |
365 | if (nargs != 0) { | |
a64d325d | 366 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
08942ac1 BH |
367 | return; |
368 | } | |
369 | ||
0866aca1 | 370 | QTAILQ_FOREACH(kid, &bus->bus.children, sibling) { |
ce2918cb | 371 | dev = (SpaprVioDevice *)kid->child; |
08942ac1 BH |
372 | spapr_vio_quiesce_one(dev); |
373 | } | |
374 | ||
a64d325d | 375 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
08942ac1 BH |
376 | } |
377 | ||
ce2918cb | 378 | static SpaprVioDevice *reg_conflict(SpaprVioDevice *dev) |
9fc380d3 | 379 | { |
ce2918cb | 380 | SpaprVioBus *bus = SPAPR_VIO_BUS(dev->qdev.parent_bus); |
0866aca1 | 381 | BusChild *kid; |
ce2918cb | 382 | SpaprVioDevice *other; |
9fc380d3 ME |
383 | |
384 | /* | |
d601fac4 DG |
385 | * Check for a device other than the given one which is already |
386 | * using the requested address. We have to open code this because | |
387 | * the given dev might already be in the list. | |
9fc380d3 | 388 | */ |
0866aca1 | 389 | QTAILQ_FOREACH(kid, &bus->bus.children, sibling) { |
fd506b4f | 390 | other = VIO_SPAPR_DEVICE(kid->child); |
9fc380d3 | 391 | |
d601fac4 DG |
392 | if (other != dev && other->reg == dev->reg) { |
393 | return other; | |
9fc380d3 ME |
394 | } |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
b1c7f725 | 400 | static void spapr_vio_busdev_reset(DeviceState *qdev) |
8e01f355 | 401 | { |
ce2918cb DG |
402 | SpaprVioDevice *dev = VIO_SPAPR_DEVICE(qdev); |
403 | SpaprVioDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev); | |
8e01f355 | 404 | |
4dd96f24 DG |
405 | /* Shut down the request queue and TCEs if necessary */ |
406 | spapr_vio_quiesce_one(dev); | |
407 | ||
408 | dev->signal_state = 0; | |
b1c7f725 | 409 | |
ee9a569a | 410 | spapr_vio_set_bypass(dev, false); |
b1c7f725 DG |
411 | if (pc->reset) { |
412 | pc->reset(dev); | |
413 | } | |
8e01f355 DG |
414 | } |
415 | ||
82cffa2e CLG |
416 | /* |
417 | * The register property of a VIO device is defined in livirt using | |
418 | * 0x1000 as a base register number plus a 0x1000 increment. For the | |
419 | * VIO tty device, the base number is changed to 0x30000000. QEMU uses | |
420 | * a base register number of 0x71000000 and then a simple increment. | |
421 | * | |
422 | * The formula below tries to compute a unique index number from the | |
423 | * register value that will be used to define the IRQ number of the | |
424 | * VIO device. | |
425 | * | |
426 | * A maximum of 256 VIO devices is covered. Collisions are possible | |
427 | * but they will be detected when the IRQ is claimed. | |
428 | */ | |
429 | static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg) | |
430 | { | |
431 | uint32_t irq; | |
432 | ||
433 | if (reg >= SPAPR_VIO_REG_BASE) { | |
434 | /* | |
435 | * VIO device register values when allocated by QEMU. For | |
436 | * these, we simply mask the high bits to fit the overall | |
437 | * range: [0x00 - 0xff]. | |
438 | * | |
439 | * The nvram VIO device (reg=0x71000000) is a static device of | |
440 | * the pseries machine and so is always allocated by QEMU. Its | |
441 | * IRQ number is 0x0. | |
442 | */ | |
443 | irq = reg & 0xff; | |
444 | ||
445 | } else if (reg >= 0x30000000) { | |
446 | /* | |
447 | * VIO tty devices register values, when allocated by livirt, | |
448 | * are mapped in range [0xf0 - 0xff], gives us a maximum of 16 | |
449 | * vtys. | |
450 | */ | |
451 | irq = 0xf0 | ((reg >> 12) & 0xf); | |
452 | ||
453 | } else { | |
454 | /* | |
455 | * Other VIO devices register values, when allocated by | |
456 | * livirt, should be mapped in range [0x00 - 0xef]. Conflicts | |
457 | * will be detected when IRQ is claimed. | |
458 | */ | |
459 | irq = (reg >> 12) & 0xff; | |
460 | } | |
461 | ||
462 | return SPAPR_IRQ_VIO | irq; | |
463 | } | |
464 | ||
28b07e73 | 465 | static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp) |
4040ab72 | 466 | { |
ce2918cb DG |
467 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
468 | SpaprVioDevice *dev = (SpaprVioDevice *)qdev; | |
469 | SpaprVioDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev); | |
4040ab72 | 470 | char *id; |
a005b3ef | 471 | Error *local_err = NULL; |
9fc380d3 | 472 | |
d601fac4 DG |
473 | if (dev->reg != -1) { |
474 | /* | |
475 | * Explicitly assigned address, just verify that no-one else | |
476 | * is using it. other mechanism). We have to open code this | |
477 | * rather than using spapr_vio_find_by_reg() because sdev | |
478 | * itself is already in the list. | |
479 | */ | |
ce2918cb | 480 | SpaprVioDevice *other = reg_conflict(dev); |
d601fac4 DG |
481 | |
482 | if (other) { | |
28b07e73 MA |
483 | error_setg(errp, "%s and %s devices conflict at address %#x", |
484 | object_get_typename(OBJECT(qdev)), | |
485 | object_get_typename(OBJECT(&other->qdev)), | |
486 | dev->reg); | |
487 | return; | |
d601fac4 DG |
488 | } |
489 | } else { | |
490 | /* Need to assign an address */ | |
ce2918cb | 491 | SpaprVioBus *bus = SPAPR_VIO_BUS(dev->qdev.parent_bus); |
d601fac4 DG |
492 | |
493 | do { | |
494 | dev->reg = bus->next_reg++; | |
495 | } while (reg_conflict(dev)); | |
9fc380d3 | 496 | } |
4040ab72 | 497 | |
1e34d859 ME |
498 | /* Don't overwrite ids assigned on the command line */ |
499 | if (!dev->qdev.id) { | |
c4eda5b7 | 500 | id = spapr_vio_get_dev_name(DEVICE(dev)); |
1e34d859 | 501 | dev->qdev.id = id; |
4040ab72 DG |
502 | } |
503 | ||
48822064 | 504 | dev->irq = spapr_vio_reg_to_irq(dev->reg); |
82cffa2e | 505 | |
48822064 CLG |
506 | if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { |
507 | dev->irq = spapr_irq_findone(spapr, &local_err); | |
508 | if (local_err) { | |
509 | error_propagate(errp, local_err); | |
510 | return; | |
4fe75a8c CLG |
511 | } |
512 | } | |
513 | ||
514 | spapr_irq_claim(spapr, dev->irq, false, &local_err); | |
a005b3ef GK |
515 | if (local_err) { |
516 | error_propagate(errp, local_err); | |
28b07e73 | 517 | return; |
416343b1 | 518 | } |
4040ab72 | 519 | |
53724ee5 | 520 | if (pc->rtce_window_size) { |
4290ca49 | 521 | uint32_t liobn = SPAPR_VIO_LIOBN(dev->reg); |
ee9a569a AK |
522 | |
523 | memory_region_init(&dev->mrroot, OBJECT(dev), "iommu-spapr-root", | |
524 | ram_size); | |
525 | memory_region_init_alias(&dev->mrbypass, OBJECT(dev), | |
526 | "iommu-spapr-bypass", get_system_memory(), | |
527 | 0, ram_size); | |
528 | memory_region_add_subregion_overlap(&dev->mrroot, 0, &dev->mrbypass, 1); | |
529 | address_space_init(&dev->as, &dev->mrroot, qdev->id); | |
530 | ||
df7625d4 AK |
531 | dev->tcet = spapr_tce_new_table(qdev, liobn); |
532 | spapr_tce_table_enable(dev->tcet, SPAPR_TCE_PAGE_SHIFT, 0, | |
533 | pc->rtce_window_size >> SPAPR_TCE_PAGE_SHIFT); | |
ee9a569a AK |
534 | dev->tcet->vdev = dev; |
535 | memory_region_add_subregion_overlap(&dev->mrroot, 0, | |
536 | spapr_tce_get_iommu(dev->tcet), 2); | |
53724ee5 | 537 | } |
ee86dfee | 538 | |
28b07e73 | 539 | pc->realize(dev, errp); |
4040ab72 DG |
540 | } |
541 | ||
ce2918cb | 542 | static target_ulong h_vio_signal(PowerPCCPU *cpu, SpaprMachineState *spapr, |
00dc738d DG |
543 | target_ulong opcode, |
544 | target_ulong *args) | |
545 | { | |
546 | target_ulong reg = args[0]; | |
547 | target_ulong mode = args[1]; | |
ce2918cb DG |
548 | SpaprVioDevice *dev = spapr_vio_find_by_reg(spapr->vio_bus, reg); |
549 | SpaprVioDeviceClass *pc; | |
00dc738d DG |
550 | |
551 | if (!dev) { | |
552 | return H_PARAMETER; | |
553 | } | |
554 | ||
3954d33a | 555 | pc = VIO_SPAPR_DEVICE_GET_CLASS(dev); |
00dc738d | 556 | |
3954d33a | 557 | if (mode & ~pc->signal_mask) { |
00dc738d DG |
558 | return H_PARAMETER; |
559 | } | |
560 | ||
561 | dev->signal_state = mode; | |
562 | ||
563 | return H_SUCCESS; | |
564 | } | |
565 | ||
ce2918cb | 566 | SpaprVioBus *spapr_vio_bus_init(void) |
4040ab72 | 567 | { |
ce2918cb | 568 | SpaprVioBus *bus; |
4040ab72 DG |
569 | BusState *qbus; |
570 | DeviceState *dev; | |
4040ab72 DG |
571 | |
572 | /* Create bridge device */ | |
215e2098 | 573 | dev = qdev_create(NULL, TYPE_SPAPR_VIO_BRIDGE); |
4040ab72 DG |
574 | qdev_init_nofail(dev); |
575 | ||
576 | /* Create bus on bridge device */ | |
0d936928 | 577 | qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio"); |
215e2098 | 578 | bus = SPAPR_VIO_BUS(qbus); |
82cffa2e | 579 | bus->next_reg = SPAPR_VIO_REG_BASE; |
4040ab72 | 580 | |
00dc738d DG |
581 | /* hcall-vio */ |
582 | spapr_register_hypercall(H_VIO_SIGNAL, h_vio_signal); | |
583 | ||
b45d63b6 BH |
584 | /* hcall-crq */ |
585 | spapr_register_hypercall(H_REG_CRQ, h_reg_crq); | |
586 | spapr_register_hypercall(H_FREE_CRQ, h_free_crq); | |
587 | spapr_register_hypercall(H_SEND_CRQ, h_send_crq); | |
588 | spapr_register_hypercall(H_ENABLE_CRQ, h_enable_crq); | |
589 | ||
08942ac1 | 590 | /* RTAS calls */ |
3a3b8502 AK |
591 | spapr_rtas_register(RTAS_IBM_SET_TCE_BYPASS, "ibm,set-tce-bypass", |
592 | rtas_set_tce_bypass); | |
593 | spapr_rtas_register(RTAS_QUIESCE, "quiesce", rtas_quiesce); | |
08942ac1 | 594 | |
4040ab72 DG |
595 | return bus; |
596 | } | |
597 | ||
999e12bb AL |
598 | static void spapr_vio_bridge_class_init(ObjectClass *klass, void *data) |
599 | { | |
5a06393f | 600 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 601 | |
5a06393f | 602 | dc->fw_name = "vdevice"; |
999e12bb AL |
603 | } |
604 | ||
8c43a6f0 | 605 | static const TypeInfo spapr_vio_bridge_info = { |
215e2098 | 606 | .name = TYPE_SPAPR_VIO_BRIDGE, |
39bffca2 | 607 | .parent = TYPE_SYS_BUS_DEVICE, |
39bffca2 | 608 | .class_init = spapr_vio_bridge_class_init, |
4040ab72 DG |
609 | }; |
610 | ||
b368a7d8 DG |
611 | const VMStateDescription vmstate_spapr_vio = { |
612 | .name = "spapr_vio", | |
613 | .version_id = 1, | |
614 | .minimum_version_id = 1, | |
3aff6c2f | 615 | .fields = (VMStateField[]) { |
b368a7d8 | 616 | /* Sanity check */ |
ce2918cb DG |
617 | VMSTATE_UINT32_EQUAL(reg, SpaprVioDevice, NULL), |
618 | VMSTATE_UINT32_EQUAL(irq, SpaprVioDevice, NULL), | |
b368a7d8 DG |
619 | |
620 | /* General VIO device state */ | |
ce2918cb DG |
621 | VMSTATE_UINT64(signal_state, SpaprVioDevice), |
622 | VMSTATE_UINT64(crq.qladdr, SpaprVioDevice), | |
623 | VMSTATE_UINT32(crq.qsize, SpaprVioDevice), | |
624 | VMSTATE_UINT32(crq.qnext, SpaprVioDevice), | |
b368a7d8 DG |
625 | |
626 | VMSTATE_END_OF_LIST() | |
627 | }, | |
628 | }; | |
629 | ||
39bffca2 AL |
630 | static void vio_spapr_device_class_init(ObjectClass *klass, void *data) |
631 | { | |
632 | DeviceClass *k = DEVICE_CLASS(klass); | |
28b07e73 | 633 | k->realize = spapr_vio_busdev_realize; |
b1c7f725 | 634 | k->reset = spapr_vio_busdev_reset; |
0d936928 | 635 | k->bus_type = TYPE_SPAPR_VIO_BUS; |
39bffca2 AL |
636 | } |
637 | ||
8c43a6f0 | 638 | static const TypeInfo spapr_vio_type_info = { |
3954d33a AL |
639 | .name = TYPE_VIO_SPAPR_DEVICE, |
640 | .parent = TYPE_DEVICE, | |
ce2918cb | 641 | .instance_size = sizeof(SpaprVioDevice), |
3954d33a | 642 | .abstract = true, |
ce2918cb | 643 | .class_size = sizeof(SpaprVioDeviceClass), |
39bffca2 | 644 | .class_init = vio_spapr_device_class_init, |
3954d33a AL |
645 | }; |
646 | ||
83f7d43a | 647 | static void spapr_vio_register_types(void) |
4040ab72 | 648 | { |
0d936928 | 649 | type_register_static(&spapr_vio_bus_info); |
39bffca2 | 650 | type_register_static(&spapr_vio_bridge_info); |
3954d33a | 651 | type_register_static(&spapr_vio_type_info); |
4040ab72 DG |
652 | } |
653 | ||
83f7d43a | 654 | type_init(spapr_vio_register_types) |
4040ab72 | 655 | |
05c19438 DG |
656 | static int compare_reg(const void *p1, const void *p2) |
657 | { | |
ce2918cb | 658 | SpaprVioDevice const *dev1, *dev2; |
05c19438 | 659 | |
ce2918cb DG |
660 | dev1 = (SpaprVioDevice *)*(DeviceState **)p1; |
661 | dev2 = (SpaprVioDevice *)*(DeviceState **)p2; | |
05c19438 DG |
662 | |
663 | if (dev1->reg < dev2->reg) { | |
664 | return -1; | |
665 | } | |
666 | if (dev1->reg == dev2->reg) { | |
667 | return 0; | |
668 | } | |
669 | ||
670 | /* dev1->reg > dev2->reg */ | |
671 | return 1; | |
672 | } | |
673 | ||
ce2918cb | 674 | void spapr_dt_vdevice(SpaprVioBus *bus, void *fdt) |
4040ab72 | 675 | { |
05c19438 | 676 | DeviceState *qdev, **qdevs; |
0866aca1 | 677 | BusChild *kid; |
05c19438 | 678 | int i, num, ret = 0; |
bf5a6696 DG |
679 | int node; |
680 | ||
681 | _FDT(node = fdt_add_subnode(fdt, 0, "vdevice")); | |
682 | ||
683 | _FDT(fdt_setprop_string(fdt, node, "device_type", "vdevice")); | |
684 | _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,vdevice")); | |
685 | _FDT(fdt_setprop_cell(fdt, node, "#address-cells", 1)); | |
686 | _FDT(fdt_setprop_cell(fdt, node, "#size-cells", 0)); | |
687 | _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); | |
688 | _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); | |
4040ab72 | 689 | |
05c19438 DG |
690 | /* Count qdevs on the bus list */ |
691 | num = 0; | |
0866aca1 | 692 | QTAILQ_FOREACH(kid, &bus->bus.children, sibling) { |
05c19438 DG |
693 | num++; |
694 | } | |
695 | ||
696 | /* Copy out into an array of pointers */ | |
dec4ec40 | 697 | qdevs = g_new(DeviceState *, num); |
05c19438 | 698 | num = 0; |
0866aca1 AL |
699 | QTAILQ_FOREACH(kid, &bus->bus.children, sibling) { |
700 | qdevs[num++] = kid->child; | |
05c19438 DG |
701 | } |
702 | ||
703 | /* Sort the array */ | |
704 | qsort(qdevs, num, sizeof(qdev), compare_reg); | |
705 | ||
706 | /* Hack alert. Give the devices to libfdt in reverse order, we happen | |
707 | * to know that will mean they are in forward order in the tree. */ | |
708 | for (i = num - 1; i >= 0; i--) { | |
ce2918cb DG |
709 | SpaprVioDevice *dev = (SpaprVioDevice *)(qdevs[i]); |
710 | SpaprVioDeviceClass *vdc = VIO_SPAPR_DEVICE_GET_CLASS(dev); | |
4040ab72 DG |
711 | |
712 | ret = vio_make_devnode(dev, fdt); | |
4040ab72 | 713 | if (ret < 0) { |
bf5a6696 DG |
714 | error_report("Couldn't create device node /vdevice/%s@%"PRIx32, |
715 | vdc->dt_name, dev->reg); | |
716 | exit(1); | |
4040ab72 DG |
717 | } |
718 | } | |
719 | ||
5f1d1fc5 | 720 | g_free(qdevs); |
4040ab72 | 721 | } |
68f3a94c | 722 | |
ce2918cb | 723 | gchar *spapr_vio_stdout_path(SpaprVioBus *bus) |
68f3a94c | 724 | { |
ce2918cb | 725 | SpaprVioDevice *dev; |
68f3a94c | 726 | char *name, *path; |
68f3a94c DG |
727 | |
728 | dev = spapr_vty_get_default(bus); | |
7c866c6a DG |
729 | if (!dev) { |
730 | return NULL; | |
68f3a94c DG |
731 | } |
732 | ||
c4eda5b7 | 733 | name = spapr_vio_get_dev_name(DEVICE(dev)); |
4ecf8aa5 | 734 | path = g_strdup_printf("/vdevice/%s", name); |
68f3a94c | 735 | |
4ecf8aa5 | 736 | g_free(name); |
7c866c6a | 737 | return path; |
68f3a94c | 738 | } |