[mirror_qemu.git] / hw / ppc / virtex_ml507.c

/*
 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
 *
 * Copyright (c) 2010 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/char/serial.h"
#include "hw/block/flash.h"
#include "sysemu/sysemu.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "sysemu/device_tree.h"
#include "hw/loader.h"
#include "elf.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"

#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "ppc405.h"

#include "sysemu/block-backend.h"

#define EPAPR_MAGIC    (0x45504150)
#define FLASH_SIZE     (16 * 1024 * 1024)

#define INTC_BASEADDR       0x81800000
#define UART16550_BASEADDR  0x83e01003
#define TIMER_BASEADDR      0x83c00000
#define PFLASH_BASEADDR     0xfc000000

#define TIMER_IRQ           3
#define UART16550_IRQ       9

static struct boot_info
{
    uint32_t bootstrap_pc;
    uint32_t cmdline;
    uint32_t fdt;
    uint32_t ima_size;
    void *vfdt;
} boot_info;

/* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
                                     target_ulong va,
                                     hwaddr pa)
{
    ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];

    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1U << 31; /* up to 0x80000000  */
    tlb->EPN = va & TARGET_PAGE_MASK;
    tlb->RPN = pa & TARGET_PAGE_MASK;
    tlb->PID = 0;

    tlb = &env->tlb.tlbe[1];
    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1U << 31; /* up to 0xffffffff  */
    tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->PID = 0;
}

static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
                                      int do_init,
                                      const char *cpu_model,
                                      uint32_t sysclk)
{
    PowerPCCPU *cpu;
    CPUPPCState *env;
    qemu_irq *irqs;

    cpu = cpu_ppc_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "Unable to initialize CPU!\n");
        exit(1);
    }
    env = &cpu->env;

    ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);

    ppc_dcr_init(env, NULL, NULL);

    /* interrupt controller */
    irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
    irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
    irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
    ppcuic_init(env, irqs, 0x0C0, 0, 1);
    return cpu;
}

static void main_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    struct boot_info *bi = env->load_info;

    cpu_reset(CPU(cpu));
    /* Linux Kernel Parameters (passing device tree):
       *   r3: pointer to the fdt
       *   r4: 0
       *   r5: 0
       *   r6: epapr magic
       *   r7: size of IMA in bytes
       *   r8: 0
       *   r9: 0
    */
    env->gpr[1] = (16<<20) - 8;
    /* Provide a device-tree.  */
    env->gpr[3] = bi->fdt;
    env->nip = bi->bootstrap_pc;

    /* Create a mapping for the kernel.  */
    mmubooke_create_initial_mapping(env, 0, 0);
    env->gpr[6] = tswap32(EPAPR_MAGIC);
    env->gpr[7] = bi->ima_size;
}

#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
static int xilinx_load_device_tree(hwaddr addr,
                                      uint32_t ramsize,
                                      hwaddr initrd_base,
                                      hwaddr initrd_size,
                                      const char *kernel_cmdline)
{
    char *path;
    int fdt_size;
    void *fdt = NULL;
    int r;
    const char *dtb_filename;

    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
    if (dtb_filename) {
        fdt = load_device_tree(dtb_filename, &fdt_size);
        if (!fdt) {
            error_report("Error while loading device tree file '%s'",
                dtb_filename);
        }
    } else {
        /* Try the local "ppc.dtb" override.  */
        fdt = load_device_tree("ppc.dtb", &fdt_size);
        if (!fdt) {
            path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
            if (path) {
                fdt = load_device_tree(path, &fdt_size);
                g_free(path);
            }
        }
    }
    if (!fdt) {
        return 0;
    }

    r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
                              initrd_base);
    if (r < 0) {
        error_report("couldn't set /chosen/linux,initrd-start");
    }

    r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
                              (initrd_base + initrd_size));
    if (r < 0) {
        error_report("couldn't set /chosen/linux,initrd-end");
    }

    r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
    if (r < 0)
        fprintf(stderr, "couldn't set /chosen/bootargs\n");
    cpu_physical_memory_write(addr, fdt, fdt_size);
    return fdt_size;
}

static void virtex_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    hwaddr initrd_base = 0;
    int initrd_size = 0;
    MemoryRegion *address_space_mem = get_system_memory();
    DeviceState *dev;
    PowerPCCPU *cpu;
    CPUPPCState *env;
    hwaddr ram_base = 0;
    DriveInfo *dinfo;
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32], *cpu_irq;
    int kernel_size;
    int i;

    /* init CPUs */
    if (machine->cpu_model == NULL) {
        machine->cpu_model = "440-Xilinx";
    }

    cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_model, 400000000);
    env = &cpu->env;
    qemu_register_reset(main_cpu_reset, cpu);

    memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          (64 * 1024), FLASH_SIZE >> 16,
                          1, 0x89, 0x18, 0x0000, 0x0, 1);

    cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
    dev = qdev_create(NULL, "xlnx.xps-intc");
    qdev_prop_set_uint32(dev, "kind-of-intr", 0);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }

    serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
                   115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);

    /* 2 timers at irq 2 @ 62 Mhz.  */
    dev = qdev_create(NULL, "xlnx.xps-timer");
    qdev_prop_set_uint32(dev, "one-timer-only", 0);
    qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);

    if (kernel_filename) {
        uint64_t entry, low, high;
        hwaddr boot_offset;

        /* Boots a kernel elf binary.  */
        kernel_size = load_elf(kernel_filename, NULL, NULL,
                               &entry, &low, &high, 1, PPC_ELF_MACHINE,
                               0, 0);
        boot_info.bootstrap_pc = entry & 0x00ffffff;

        if (kernel_size < 0) {
            boot_offset = 0x1200000;
            /* If we failed loading ELF's try a raw image.  */
            kernel_size = load_image_targphys(kernel_filename,
                                              boot_offset,
                                              ram_size);
            boot_info.bootstrap_pc = boot_offset;
            high = boot_info.bootstrap_pc + kernel_size + 8192;
        }

        boot_info.ima_size = kernel_size;

        /* Load initrd. */
        if (machine->initrd_filename) {
            initrd_base = high = ROUND_UP(high, 4);
            initrd_size = load_image_targphys(machine->initrd_filename,
                                              high, ram_size - high);

            if (initrd_size < 0) {
                error_report("couldn't load ram disk '%s'",
                             machine->initrd_filename);
                exit(1);
            }
            high = ROUND_UP(high + initrd_size, 4);
        }

        /* Provide a device-tree.  */
        boot_info.fdt = high + (8192 * 2);
        boot_info.fdt &= ~8191;

        xilinx_load_device_tree(boot_info.fdt, ram_size,
                                initrd_base, initrd_size,
                                kernel_cmdline);
    }
    env->load_info = &boot_info;
}

static void virtex_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx Virtex ML507 reference design";
    mc->init = virtex_init;
}

DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
Commit	Line	Data
2c50e26e EI	1	/*
	2	* Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
	3	*
	4	* Copyright (c) 2010 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
0d75590d	25	#include "qemu/osdep.h"
33c11879	26	#include "cpu.h"
83c9f4ca PB	27	#include "hw/sysbus.h"
83c9f4ca PB	28	#include "hw/hw.h"
0d09e41a PB	29	#include "hw/char/serial.h"
0d09e41a PB	30	#include "hw/block/flash.h"
9c17d615	31	#include "sysemu/sysemu.h"
bd2be150	32	#include "hw/devices.h"
83c9f4ca	33	#include "hw/boards.h"
9c17d615	34	#include "sysemu/device_tree.h"
83c9f4ca	35	#include "hw/loader.h"
2c50e26e	36	#include "elf.h"
d49b6836	37	#include "qemu/error-report.h"
1de7afc9	38	#include "qemu/log.h"
022c62cb	39	#include "exec/address-spaces.h"
2c50e26e	40
0d09e41a PB	41	#include "hw/ppc/ppc.h"
0d09e41a PB	42	#include "hw/ppc/ppc4xx.h"
47b43a1f	43	#include "ppc405.h"
2c50e26e	44
fa1d36df	45	#include "sysemu/block-backend.h"
2c50e26e EI	46
	47	#define EPAPR_MAGIC (0x45504150)
	48	#define FLASH_SIZE (16 * 1024 * 1024)
	49
81cce07e PC	50	#define INTC_BASEADDR 0x81800000
	51	#define UART16550_BASEADDR 0x83e01003
	52	#define TIMER_BASEADDR 0x83c00000
	53	#define PFLASH_BASEADDR 0xfc000000
	54
	55	#define TIMER_IRQ 3
	56	#define UART16550_IRQ 9
	57
2c50e26e EI	58	static struct boot_info
	59	{
	60	uint32_t bootstrap_pc;
	61	uint32_t cmdline;
	62	uint32_t fdt;
	63	uint32_t ima_size;
	64	void *vfdt;
	65	} boot_info;
	66
	67	/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
e2684c0b	68	static void mmubooke_create_initial_mapping(CPUPPCState *env,
2c50e26e	69	target_ulong va,
a8170e5e	70	hwaddr pa)
2c50e26e	71	{
1c53accc	72	ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
2c50e26e EI	73
	74	tlb->attr = 0;
	75	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
a1f7f97b	76	tlb->size = 1U << 31; /* up to 0x80000000 */
2c50e26e EI	77	tlb->EPN = va & TARGET_PAGE_MASK;
	78	tlb->RPN = pa & TARGET_PAGE_MASK;
	79	tlb->PID = 0;
	80
1c53accc	81	tlb = &env->tlb.tlbe[1];
2c50e26e EI	82	tlb->attr = 0;
2c50e26e EI	83	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
a1f7f97b	84	tlb->size = 1U << 31; /* up to 0xffffffff */
2c50e26e EI	85	tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
	86	tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
	87	tlb->PID = 0;
	88	}
	89
68281699 AF	90	static PowerPCCPU ppc440_init_xilinx(ram_addr_t ram_size,
	91	int do_init,
	92	const char *cpu_model,
	93	uint32_t sysclk)
2c50e26e	94	{
d1d4938b	95	PowerPCCPU *cpu;
e2684c0b	96	CPUPPCState *env;
2c50e26e EI	97	qemu_irq *irqs;
2c50e26e EI	98
d1d4938b AF	99	cpu = cpu_ppc_init(cpu_model);
d1d4938b AF	100	if (cpu == NULL) {
2c50e26e EI	101	fprintf(stderr, "Unable to initialize CPU!\n");
	102	exit(1);
	103	}
d1d4938b	104	env = &cpu->env;
2c50e26e	105
a34a92b9	106	ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
2c50e26e EI	107
	108	ppc_dcr_init(env, NULL, NULL);
	109
	110	/* interrupt controller */
7267c094	111	irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2c50e26e EI	112	irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2c50e26e EI	113	irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
49a2942d	114	ppcuic_init(env, irqs, 0x0C0, 0, 1);
68281699	115	return cpu;
2c50e26e EI	116	}
	117
	118	static void main_cpu_reset(void *opaque)
	119	{
f8031482 AF	120	PowerPCCPU *cpu = opaque;
f8031482 AF	121	CPUPPCState *env = &cpu->env;
2c50e26e EI	122	struct boot_info *bi = env->load_info;
2c50e26e EI	123
f8031482	124	cpu_reset(CPU(cpu));
2c50e26e EI	125	/* Linux Kernel Parameters (passing device tree):
	126	* r3: pointer to the fdt
	127	* r4: 0
	128	* r5: 0
	129	* r6: epapr magic
	130	* r7: size of IMA in bytes
	131	* r8: 0
	132	* r9: 0
	133	*/
	134	env->gpr[1] = (16<<20) - 8;
	135	/* Provide a device-tree. */
	136	env->gpr[3] = bi->fdt;
	137	env->nip = bi->bootstrap_pc;
	138
	139	/* Create a mapping for the kernel. */
	140	mmubooke_create_initial_mapping(env, 0, 0);
	141	env->gpr[6] = tswap32(EPAPR_MAGIC);
	142	env->gpr[7] = bi->ima_size;
	143	}
	144
	145	#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
a8170e5e	146	static int xilinx_load_device_tree(hwaddr addr,
2c50e26e	147	uint32_t ramsize,
a8170e5e AK	148	hwaddr initrd_base,
a8170e5e AK	149	hwaddr initrd_size,
2c50e26e EI	150	const char *kernel_cmdline)
	151	{
	152	char *path;
	153	int fdt_size;
daf285b6	154	void *fdt = NULL;
2c50e26e	155	int r;
daf285b6	156	const char *dtb_filename;
2c50e26e	157
daf285b6 EV	158	dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
	159	if (dtb_filename) {
	160	fdt = load_device_tree(dtb_filename, &fdt_size);
	161	if (!fdt) {
	162	error_report("Error while loading device tree file '%s'",
	163	dtb_filename);
2c50e26e	164	}
daf285b6 EV	165	} else {
	166	/* Try the local "ppc.dtb" override. */
	167	fdt = load_device_tree("ppc.dtb", &fdt_size);
3b2e3dc9	168	if (!fdt) {
daf285b6 EV	169	path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
	170	if (path) {
	171	fdt = load_device_tree(path, &fdt_size);
	172	g_free(path);
	173	}
3b2e3dc9	174	}
2c50e26e	175	}
daf285b6 EV	176	if (!fdt) {
	177	return 0;
	178	}
0658aa9c EI	179
	180	r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
	181	initrd_base);
	182	if (r < 0) {
	183	error_report("couldn't set /chosen/linux,initrd-start");
	184	}
	185
	186	r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
	187	(initrd_base + initrd_size));
	188	if (r < 0) {
	189	error_report("couldn't set /chosen/linux,initrd-end");
	190	}
	191
5a4348d1	192	r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
2c50e26e EI	193	if (r < 0)
2c50e26e EI	194	fprintf(stderr, "couldn't set /chosen/bootargs\n");
e1fe50dc	195	cpu_physical_memory_write(addr, fdt, fdt_size);
2c50e26e EI	196	return fdt_size;
	197	}
	198
3ef96221	199	static void virtex_init(MachineState *machine)
2c50e26e	200	{
3ef96221	201	ram_addr_t ram_size = machine->ram_size;
3ef96221 MA	202	const char *kernel_filename = machine->kernel_filename;
3ef96221 MA	203	const char *kernel_cmdline = machine->kernel_cmdline;
0658aa9c EI	204	hwaddr initrd_base = 0;
0658aa9c EI	205	int initrd_size = 0;
39186d8a	206	MemoryRegion *address_space_mem = get_system_memory();
2c50e26e	207	DeviceState *dev;
68281699	208	PowerPCCPU *cpu;
e2684c0b	209	CPUPPCState *env;
a8170e5e	210	hwaddr ram_base = 0;
2c50e26e	211	DriveInfo *dinfo;
333b13fc	212	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
2c50e26e	213	qemu_irq irq[32], *cpu_irq;
2c50e26e EI	214	int kernel_size;
	215	int i;
	216
	217	/* init CPUs */
19fb2c36 BR	218	if (machine->cpu_model == NULL) {
19fb2c36 BR	219	machine->cpu_model = "440-Xilinx";
2c50e26e EI	220	}
2c50e26e EI	221
19fb2c36	222	cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_model, 400000000);
68281699	223	env = &cpu->env;
f8031482	224	qemu_register_reset(main_cpu_reset, cpu);
2c50e26e	225
e938ba0c	226	memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
333b13fc	227	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
2c50e26e	228
2c50e26e	229	dinfo = drive_get(IF_PFLASH, 0, 0);
81cce07e	230	pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
4be74634	231	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df	232	(64 * 1024), FLASH_SIZE >> 16,
01e0451a	233	1, 0x89, 0x18, 0x0000, 0x0, 1);
2c50e26e EI	234
2c50e26e EI	235	cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
13c9bfbf PC	236	dev = qdev_create(NULL, "xlnx.xps-intc");
	237	qdev_prop_set_uint32(dev, "kind-of-intr", 0);
	238	qdev_init_nofail(dev);
	239	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
	240	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
2c50e26e EI	241	for (i = 0; i < 32; i++) {
	242	irq[i] = qdev_get_gpio_in(dev, i);
	243	}
	244
81cce07e PC	245	serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
81cce07e PC	246	115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
2c50e26e EI	247
2c50e26e EI	248	/* 2 timers at irq 2 @ 62 Mhz. */
29873712 PC	249	dev = qdev_create(NULL, "xlnx.xps-timer");
	250	qdev_prop_set_uint32(dev, "one-timer-only", 0);
	251	qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
	252	qdev_init_nofail(dev);
	253	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
	254	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
2c50e26e EI	255
	256	if (kernel_filename) {
	257	uint64_t entry, low, high;
a8170e5e	258	hwaddr boot_offset;
2c50e26e EI	259
	260	/* Boots a kernel elf binary. */
	261	kernel_size = load_elf(kernel_filename, NULL, NULL,
7ef295ea PC	262	&entry, &low, &high, 1, PPC_ELF_MACHINE,
7ef295ea PC	263	0, 0);
2c50e26e EI	264	boot_info.bootstrap_pc = entry & 0x00ffffff;
	265
	266	if (kernel_size < 0) {
	267	boot_offset = 0x1200000;
	268	/* If we failed loading ELF's try a raw image. */
	269	kernel_size = load_image_targphys(kernel_filename,
	270	boot_offset,
	271	ram_size);
	272	boot_info.bootstrap_pc = boot_offset;
	273	high = boot_info.bootstrap_pc + kernel_size + 8192;
	274	}
	275
	276	boot_info.ima_size = kernel_size;
	277
0658aa9c	278	/* Load initrd. */
3ef96221	279	if (machine->initrd_filename) {
0658aa9c	280	initrd_base = high = ROUND_UP(high, 4);
3ef96221	281	initrd_size = load_image_targphys(machine->initrd_filename,
0658aa9c EI	282	high, ram_size - high);
	283
	284	if (initrd_size < 0) {
	285	error_report("couldn't load ram disk '%s'",
3ef96221	286	machine->initrd_filename);
0658aa9c EI	287	exit(1);
	288	}
	289	high = ROUND_UP(high + initrd_size, 4);
	290	}
	291
2c50e26e EI	292	/* Provide a device-tree. */
	293	boot_info.fdt = high + (8192 * 2);
	294	boot_info.fdt &= ~8191;
0658aa9c EI	295
	296	xilinx_load_device_tree(boot_info.fdt, ram_size,
	297	initrd_base, initrd_size,
	298	kernel_cmdline);
2c50e26e EI	299	}
	300	env->load_info = &boot_info;
	301	}
	302
e264d29d	303	static void virtex_machine_init(MachineClass *mc)
2c50e26e	304	{
e264d29d EH	305	mc->desc = "Xilinx Virtex ML507 reference design";
e264d29d EH	306	mc->init = virtex_init;
2c50e26e EI	307	}
2c50e26e EI	308
e264d29d	309	DEFINE_MACHINE("virtex-ml507", virtex_machine_init)