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2c50e26e
EI
1/*
2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
3 *
4 * Copyright (c) 2010 Edgar E. Iglesias.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
0d75590d 25#include "qemu/osdep.h"
ab3dd749 26#include "qemu/units.h"
33c11879 27#include "cpu.h"
83c9f4ca
PB
28#include "hw/sysbus.h"
29#include "hw/hw.h"
0d09e41a
PB
30#include "hw/char/serial.h"
31#include "hw/block/flash.h"
9c17d615 32#include "sysemu/sysemu.h"
64b47457 33#include "sysemu/qtest.h"
bd2be150 34#include "hw/devices.h"
83c9f4ca 35#include "hw/boards.h"
9c17d615 36#include "sysemu/device_tree.h"
83c9f4ca 37#include "hw/loader.h"
2c50e26e 38#include "elf.h"
d49b6836 39#include "qemu/error-report.h"
1de7afc9 40#include "qemu/log.h"
922a01a0 41#include "qemu/option.h"
022c62cb 42#include "exec/address-spaces.h"
2c50e26e 43
0d09e41a
PB
44#include "hw/ppc/ppc.h"
45#include "hw/ppc/ppc4xx.h"
47b43a1f 46#include "ppc405.h"
2c50e26e 47
2c50e26e 48#define EPAPR_MAGIC (0x45504150)
ab3dd749 49#define FLASH_SIZE (16 * MiB)
2c50e26e 50
81cce07e
PC
51#define INTC_BASEADDR 0x81800000
52#define UART16550_BASEADDR 0x83e01003
53#define TIMER_BASEADDR 0x83c00000
54#define PFLASH_BASEADDR 0xfc000000
55
56#define TIMER_IRQ 3
57#define UART16550_IRQ 9
58
2c50e26e
EI
59static struct boot_info
60{
61 uint32_t bootstrap_pc;
62 uint32_t cmdline;
63 uint32_t fdt;
64 uint32_t ima_size;
65 void *vfdt;
66} boot_info;
67
68/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
e2684c0b 69static void mmubooke_create_initial_mapping(CPUPPCState *env,
2c50e26e 70 target_ulong va,
a8170e5e 71 hwaddr pa)
2c50e26e 72{
1c53accc 73 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
2c50e26e
EI
74
75 tlb->attr = 0;
76 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
a1f7f97b 77 tlb->size = 1U << 31; /* up to 0x80000000 */
2c50e26e
EI
78 tlb->EPN = va & TARGET_PAGE_MASK;
79 tlb->RPN = pa & TARGET_PAGE_MASK;
80 tlb->PID = 0;
81
1c53accc 82 tlb = &env->tlb.tlbe[1];
2c50e26e
EI
83 tlb->attr = 0;
84 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
a1f7f97b 85 tlb->size = 1U << 31; /* up to 0xffffffff */
2c50e26e
EI
86 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
87 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
88 tlb->PID = 0;
89}
90
68281699
AF
91static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
92 int do_init,
6bab8eaa 93 const char *cpu_type,
68281699 94 uint32_t sysclk)
2c50e26e 95{
d1d4938b 96 PowerPCCPU *cpu;
e2684c0b 97 CPUPPCState *env;
2c50e26e
EI
98 qemu_irq *irqs;
99
6bab8eaa 100 cpu = POWERPC_CPU(cpu_create(cpu_type));
d1d4938b 101 env = &cpu->env;
2c50e26e 102
a34a92b9 103 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
2c50e26e
EI
104
105 ppc_dcr_init(env, NULL, NULL);
106
107 /* interrupt controller */
7267c094 108 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2c50e26e
EI
109 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
110 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
49a2942d 111 ppcuic_init(env, irqs, 0x0C0, 0, 1);
68281699 112 return cpu;
2c50e26e
EI
113}
114
115static void main_cpu_reset(void *opaque)
116{
f8031482
AF
117 PowerPCCPU *cpu = opaque;
118 CPUPPCState *env = &cpu->env;
2c50e26e
EI
119 struct boot_info *bi = env->load_info;
120
f8031482 121 cpu_reset(CPU(cpu));
2c50e26e
EI
122 /* Linux Kernel Parameters (passing device tree):
123 * r3: pointer to the fdt
124 * r4: 0
125 * r5: 0
126 * r6: epapr magic
127 * r7: size of IMA in bytes
128 * r8: 0
129 * r9: 0
130 */
ab3dd749 131 env->gpr[1] = (16 * MiB) - 8;
2c50e26e
EI
132 /* Provide a device-tree. */
133 env->gpr[3] = bi->fdt;
134 env->nip = bi->bootstrap_pc;
135
136 /* Create a mapping for the kernel. */
137 mmubooke_create_initial_mapping(env, 0, 0);
138 env->gpr[6] = tswap32(EPAPR_MAGIC);
139 env->gpr[7] = bi->ima_size;
140}
141
142#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
a8170e5e 143static int xilinx_load_device_tree(hwaddr addr,
2c50e26e 144 uint32_t ramsize,
a8170e5e
AK
145 hwaddr initrd_base,
146 hwaddr initrd_size,
2c50e26e
EI
147 const char *kernel_cmdline)
148{
149 char *path;
150 int fdt_size;
daf285b6 151 void *fdt = NULL;
2c50e26e 152 int r;
daf285b6 153 const char *dtb_filename;
2c50e26e 154
daf285b6
EV
155 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
156 if (dtb_filename) {
157 fdt = load_device_tree(dtb_filename, &fdt_size);
158 if (!fdt) {
159 error_report("Error while loading device tree file '%s'",
160 dtb_filename);
2c50e26e 161 }
daf285b6
EV
162 } else {
163 /* Try the local "ppc.dtb" override. */
164 fdt = load_device_tree("ppc.dtb", &fdt_size);
3b2e3dc9 165 if (!fdt) {
daf285b6
EV
166 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
167 if (path) {
168 fdt = load_device_tree(path, &fdt_size);
169 g_free(path);
170 }
3b2e3dc9 171 }
2c50e26e 172 }
daf285b6
EV
173 if (!fdt) {
174 return 0;
175 }
0658aa9c
EI
176
177 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
178 initrd_base);
179 if (r < 0) {
180 error_report("couldn't set /chosen/linux,initrd-start");
181 }
182
183 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
184 (initrd_base + initrd_size));
185 if (r < 0) {
186 error_report("couldn't set /chosen/linux,initrd-end");
187 }
188
5a4348d1 189 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
2c50e26e
EI
190 if (r < 0)
191 fprintf(stderr, "couldn't set /chosen/bootargs\n");
e1fe50dc 192 cpu_physical_memory_write(addr, fdt, fdt_size);
2c50e26e
EI
193 return fdt_size;
194}
195
3ef96221 196static void virtex_init(MachineState *machine)
2c50e26e 197{
3ef96221 198 ram_addr_t ram_size = machine->ram_size;
3ef96221
MA
199 const char *kernel_filename = machine->kernel_filename;
200 const char *kernel_cmdline = machine->kernel_cmdline;
0658aa9c
EI
201 hwaddr initrd_base = 0;
202 int initrd_size = 0;
39186d8a 203 MemoryRegion *address_space_mem = get_system_memory();
2c50e26e 204 DeviceState *dev;
68281699 205 PowerPCCPU *cpu;
e2684c0b 206 CPUPPCState *env;
a8170e5e 207 hwaddr ram_base = 0;
2c50e26e 208 DriveInfo *dinfo;
333b13fc 209 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
2c50e26e 210 qemu_irq irq[32], *cpu_irq;
2c50e26e
EI
211 int kernel_size;
212 int i;
213
64b47457
TH
214#ifdef TARGET_PPCEMB
215 if (!qtest_enabled()) {
216 warn_report("qemu-system-ppcemb is deprecated, "
217 "please use qemu-system-ppc instead.");
218 }
219#endif
220
2c50e26e 221 /* init CPUs */
6bab8eaa 222 cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_type, 400000000);
68281699 223 env = &cpu->env;
00469dc3
VP
224
225 if (env->mmu_model != POWERPC_MMU_BOOKE) {
6f76b817
AF
226 error_report("MMU model %i not supported by this machine",
227 env->mmu_model);
00469dc3
VP
228 exit(1);
229 }
230
f8031482 231 qemu_register_reset(main_cpu_reset, cpu);
2c50e26e 232
e938ba0c 233 memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
333b13fc 234 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
2c50e26e 235
2c50e26e 236 dinfo = drive_get(IF_PFLASH, 0, 0);
81cce07e 237 pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
4be74634 238 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ab3dd749 239 64 * KiB, FLASH_SIZE >> 16,
01e0451a 240 1, 0x89, 0x18, 0x0000, 0x0, 1);
2c50e26e
EI
241
242 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
13c9bfbf
PC
243 dev = qdev_create(NULL, "xlnx.xps-intc");
244 qdev_prop_set_uint32(dev, "kind-of-intr", 0);
245 qdev_init_nofail(dev);
246 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
247 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
2c50e26e
EI
248 for (i = 0; i < 32; i++) {
249 irq[i] = qdev_get_gpio_in(dev, i);
250 }
251
81cce07e 252 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
9bca0edb 253 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
2c50e26e
EI
254
255 /* 2 timers at irq 2 @ 62 Mhz. */
29873712
PC
256 dev = qdev_create(NULL, "xlnx.xps-timer");
257 qdev_prop_set_uint32(dev, "one-timer-only", 0);
258 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
259 qdev_init_nofail(dev);
260 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
261 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
2c50e26e
EI
262
263 if (kernel_filename) {
264 uint64_t entry, low, high;
a8170e5e 265 hwaddr boot_offset;
2c50e26e
EI
266
267 /* Boots a kernel elf binary. */
268 kernel_size = load_elf(kernel_filename, NULL, NULL,
7ef295ea
PC
269 &entry, &low, &high, 1, PPC_ELF_MACHINE,
270 0, 0);
2c50e26e
EI
271 boot_info.bootstrap_pc = entry & 0x00ffffff;
272
273 if (kernel_size < 0) {
274 boot_offset = 0x1200000;
275 /* If we failed loading ELF's try a raw image. */
276 kernel_size = load_image_targphys(kernel_filename,
277 boot_offset,
278 ram_size);
279 boot_info.bootstrap_pc = boot_offset;
280 high = boot_info.bootstrap_pc + kernel_size + 8192;
281 }
282
283 boot_info.ima_size = kernel_size;
284
0658aa9c 285 /* Load initrd. */
3ef96221 286 if (machine->initrd_filename) {
0658aa9c 287 initrd_base = high = ROUND_UP(high, 4);
3ef96221 288 initrd_size = load_image_targphys(machine->initrd_filename,
0658aa9c
EI
289 high, ram_size - high);
290
291 if (initrd_size < 0) {
292 error_report("couldn't load ram disk '%s'",
3ef96221 293 machine->initrd_filename);
0658aa9c
EI
294 exit(1);
295 }
296 high = ROUND_UP(high + initrd_size, 4);
297 }
298
2c50e26e
EI
299 /* Provide a device-tree. */
300 boot_info.fdt = high + (8192 * 2);
301 boot_info.fdt &= ~8191;
0658aa9c
EI
302
303 xilinx_load_device_tree(boot_info.fdt, ram_size,
304 initrd_base, initrd_size,
305 kernel_cmdline);
2c50e26e
EI
306 }
307 env->load_info = &boot_info;
308}
309
e264d29d 310static void virtex_machine_init(MachineClass *mc)
2c50e26e 311{
e264d29d
EH
312 mc->desc = "Xilinx Virtex ML507 reference design";
313 mc->init = virtex_init;
6bab8eaa 314 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
2c50e26e
EI
315}
316
e264d29d 317DEFINE_MACHINE("virtex-ml507", virtex_machine_init)