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Commit | Line | Data |
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a541f297 | 1 | /* |
e9df014c | 2 | * QEMU generic PowerPC hardware System Emulator |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "ppc.h" | |
26 | #include "qemu-timer.h" | |
27 | #include "sysemu.h" | |
28 | #include "nvram.h" | |
3b3fb322 | 29 | #include "qemu-log.h" |
a541f297 | 30 | |
e9df014c | 31 | //#define PPC_DEBUG_IRQ |
4b6d0a4c | 32 | //#define PPC_DEBUG_TB |
e9df014c | 33 | |
d12d51d5 | 34 | #ifdef PPC_DEBUG_IRQ |
93fcfe39 | 35 | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
d12d51d5 AL |
36 | #else |
37 | # define LOG_IRQ(...) do { } while (0) | |
38 | #endif | |
39 | ||
40 | ||
41 | #ifdef PPC_DEBUG_TB | |
93fcfe39 | 42 | # define LOG_TB(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
43 | #else |
44 | # define LOG_TB(...) do { } while (0) | |
45 | #endif | |
46 | ||
dbdd2506 JM |
47 | static void cpu_ppc_tb_stop (CPUState *env); |
48 | static void cpu_ppc_tb_start (CPUState *env); | |
49 | ||
00af685f | 50 | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
47103572 | 51 | { |
47103572 JM |
52 | if (level) { |
53 | env->pending_interrupts |= 1 << n_IRQ; | |
54 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
55 | } else { | |
56 | env->pending_interrupts &= ~(1 << n_IRQ); | |
57 | if (env->pending_interrupts == 0) | |
58 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
59 | } | |
d12d51d5 | 60 | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 |
aae9366a | 61 | "req %08x\n", __func__, env, n_IRQ, level, |
a496775f | 62 | env->pending_interrupts, env->interrupt_request); |
47103572 JM |
63 | } |
64 | ||
e9df014c JM |
65 | /* PowerPC 6xx / 7xx internal IRQ controller */ |
66 | static void ppc6xx_set_irq (void *opaque, int pin, int level) | |
d537cf6c | 67 | { |
e9df014c JM |
68 | CPUState *env = opaque; |
69 | int cur_level; | |
d537cf6c | 70 | |
d12d51d5 | 71 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
a496775f | 72 | env, pin, level); |
e9df014c JM |
73 | cur_level = (env->irq_input_state >> pin) & 1; |
74 | /* Don't generate spurious events */ | |
24be5ae3 | 75 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
e9df014c | 76 | switch (pin) { |
dbdd2506 JM |
77 | case PPC6xx_INPUT_TBEN: |
78 | /* Level sensitive - active high */ | |
d12d51d5 | 79 | LOG_IRQ("%s: %s the time base\n", |
dbdd2506 | 80 | __func__, level ? "start" : "stop"); |
dbdd2506 JM |
81 | if (level) { |
82 | cpu_ppc_tb_start(env); | |
83 | } else { | |
84 | cpu_ppc_tb_stop(env); | |
85 | } | |
24be5ae3 JM |
86 | case PPC6xx_INPUT_INT: |
87 | /* Level sensitive - active high */ | |
d12d51d5 | 88 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
a496775f | 89 | __func__, level); |
e9df014c JM |
90 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
91 | break; | |
24be5ae3 | 92 | case PPC6xx_INPUT_SMI: |
e9df014c | 93 | /* Level sensitive - active high */ |
d12d51d5 | 94 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", |
a496775f | 95 | __func__, level); |
e9df014c JM |
96 | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
97 | break; | |
24be5ae3 | 98 | case PPC6xx_INPUT_MCP: |
e9df014c JM |
99 | /* Negative edge sensitive */ |
100 | /* XXX: TODO: actual reaction may depends on HID0 status | |
101 | * 603/604/740/750: check HID0[EMCP] | |
102 | */ | |
103 | if (cur_level == 1 && level == 0) { | |
d12d51d5 | 104 | LOG_IRQ("%s: raise machine check state\n", |
a496775f | 105 | __func__); |
e9df014c JM |
106 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); |
107 | } | |
108 | break; | |
24be5ae3 | 109 | case PPC6xx_INPUT_CKSTP_IN: |
e9df014c JM |
110 | /* Level sensitive - active low */ |
111 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
e63ecc6f | 112 | /* XXX: Note that the only way to restart the CPU is to reset it */ |
e9df014c | 113 | if (level) { |
d12d51d5 | 114 | LOG_IRQ("%s: stop the CPU\n", __func__); |
e9df014c | 115 | env->halted = 1; |
e9df014c JM |
116 | } |
117 | break; | |
24be5ae3 | 118 | case PPC6xx_INPUT_HRESET: |
e9df014c JM |
119 | /* Level sensitive - active low */ |
120 | if (level) { | |
d12d51d5 | 121 | LOG_IRQ("%s: reset the CPU\n", __func__); |
ef397e88 JM |
122 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
123 | /* XXX: TOFIX */ | |
124 | #if 0 | |
125 | cpu_ppc_reset(env); | |
126 | #else | |
127 | qemu_system_reset_request(); | |
e9df014c JM |
128 | #endif |
129 | } | |
130 | break; | |
24be5ae3 | 131 | case PPC6xx_INPUT_SRESET: |
d12d51d5 | 132 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
a496775f | 133 | __func__, level); |
e9df014c JM |
134 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
135 | break; | |
136 | default: | |
137 | /* Unknown pin - do nothing */ | |
d12d51d5 | 138 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
e9df014c JM |
139 | return; |
140 | } | |
141 | if (level) | |
142 | env->irq_input_state |= 1 << pin; | |
143 | else | |
144 | env->irq_input_state &= ~(1 << pin); | |
d537cf6c PB |
145 | } |
146 | } | |
147 | ||
e9df014c | 148 | void ppc6xx_irq_init (CPUState *env) |
47103572 | 149 | { |
7b62a955 JM |
150 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, |
151 | PPC6xx_INPUT_NB); | |
47103572 JM |
152 | } |
153 | ||
00af685f | 154 | #if defined(TARGET_PPC64) |
d0dfae6e JM |
155 | /* PowerPC 970 internal IRQ controller */ |
156 | static void ppc970_set_irq (void *opaque, int pin, int level) | |
157 | { | |
158 | CPUState *env = opaque; | |
159 | int cur_level; | |
160 | ||
d12d51d5 | 161 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
d0dfae6e | 162 | env, pin, level); |
d0dfae6e JM |
163 | cur_level = (env->irq_input_state >> pin) & 1; |
164 | /* Don't generate spurious events */ | |
165 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
166 | switch (pin) { | |
167 | case PPC970_INPUT_INT: | |
168 | /* Level sensitive - active high */ | |
d12d51d5 | 169 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
d0dfae6e | 170 | __func__, level); |
d0dfae6e JM |
171 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
172 | break; | |
173 | case PPC970_INPUT_THINT: | |
174 | /* Level sensitive - active high */ | |
d12d51d5 | 175 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, |
d0dfae6e | 176 | level); |
d0dfae6e JM |
177 | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
178 | break; | |
179 | case PPC970_INPUT_MCP: | |
180 | /* Negative edge sensitive */ | |
181 | /* XXX: TODO: actual reaction may depends on HID0 status | |
182 | * 603/604/740/750: check HID0[EMCP] | |
183 | */ | |
184 | if (cur_level == 1 && level == 0) { | |
d12d51d5 | 185 | LOG_IRQ("%s: raise machine check state\n", |
d0dfae6e | 186 | __func__); |
d0dfae6e JM |
187 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); |
188 | } | |
189 | break; | |
190 | case PPC970_INPUT_CKSTP: | |
191 | /* Level sensitive - active low */ | |
192 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
193 | if (level) { | |
d12d51d5 | 194 | LOG_IRQ("%s: stop the CPU\n", __func__); |
d0dfae6e JM |
195 | env->halted = 1; |
196 | } else { | |
d12d51d5 | 197 | LOG_IRQ("%s: restart the CPU\n", __func__); |
d0dfae6e JM |
198 | env->halted = 0; |
199 | } | |
200 | break; | |
201 | case PPC970_INPUT_HRESET: | |
202 | /* Level sensitive - active low */ | |
203 | if (level) { | |
204 | #if 0 // XXX: TOFIX | |
d12d51d5 | 205 | LOG_IRQ("%s: reset the CPU\n", __func__); |
d0dfae6e JM |
206 | cpu_reset(env); |
207 | #endif | |
208 | } | |
209 | break; | |
210 | case PPC970_INPUT_SRESET: | |
d12d51d5 | 211 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
d0dfae6e | 212 | __func__, level); |
d0dfae6e JM |
213 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
214 | break; | |
215 | case PPC970_INPUT_TBEN: | |
d12d51d5 | 216 | LOG_IRQ("%s: set the TBEN state to %d\n", __func__, |
d0dfae6e | 217 | level); |
d0dfae6e JM |
218 | /* XXX: TODO */ |
219 | break; | |
220 | default: | |
221 | /* Unknown pin - do nothing */ | |
d12d51d5 | 222 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
d0dfae6e JM |
223 | return; |
224 | } | |
225 | if (level) | |
226 | env->irq_input_state |= 1 << pin; | |
227 | else | |
228 | env->irq_input_state &= ~(1 << pin); | |
229 | } | |
230 | } | |
231 | ||
232 | void ppc970_irq_init (CPUState *env) | |
233 | { | |
7b62a955 JM |
234 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, |
235 | PPC970_INPUT_NB); | |
d0dfae6e | 236 | } |
00af685f | 237 | #endif /* defined(TARGET_PPC64) */ |
d0dfae6e | 238 | |
4e290a0b JM |
239 | /* PowerPC 40x internal IRQ controller */ |
240 | static void ppc40x_set_irq (void *opaque, int pin, int level) | |
24be5ae3 JM |
241 | { |
242 | CPUState *env = opaque; | |
243 | int cur_level; | |
244 | ||
d12d51d5 | 245 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
8ecc7913 | 246 | env, pin, level); |
24be5ae3 JM |
247 | cur_level = (env->irq_input_state >> pin) & 1; |
248 | /* Don't generate spurious events */ | |
249 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
250 | switch (pin) { | |
4e290a0b | 251 | case PPC40x_INPUT_RESET_SYS: |
8ecc7913 | 252 | if (level) { |
d12d51d5 | 253 | LOG_IRQ("%s: reset the PowerPC system\n", |
8ecc7913 | 254 | __func__); |
8ecc7913 JM |
255 | ppc40x_system_reset(env); |
256 | } | |
257 | break; | |
4e290a0b | 258 | case PPC40x_INPUT_RESET_CHIP: |
8ecc7913 | 259 | if (level) { |
d12d51d5 | 260 | LOG_IRQ("%s: reset the PowerPC chip\n", __func__); |
8ecc7913 JM |
261 | ppc40x_chip_reset(env); |
262 | } | |
263 | break; | |
4e290a0b | 264 | case PPC40x_INPUT_RESET_CORE: |
24be5ae3 JM |
265 | /* XXX: TODO: update DBSR[MRR] */ |
266 | if (level) { | |
d12d51d5 | 267 | LOG_IRQ("%s: reset the PowerPC core\n", __func__); |
8ecc7913 | 268 | ppc40x_core_reset(env); |
24be5ae3 JM |
269 | } |
270 | break; | |
4e290a0b | 271 | case PPC40x_INPUT_CINT: |
24be5ae3 | 272 | /* Level sensitive - active high */ |
d12d51d5 | 273 | LOG_IRQ("%s: set the critical IRQ state to %d\n", |
8ecc7913 | 274 | __func__, level); |
4e290a0b | 275 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
24be5ae3 | 276 | break; |
4e290a0b | 277 | case PPC40x_INPUT_INT: |
24be5ae3 | 278 | /* Level sensitive - active high */ |
d12d51d5 | 279 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
a496775f | 280 | __func__, level); |
24be5ae3 JM |
281 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
282 | break; | |
4e290a0b | 283 | case PPC40x_INPUT_HALT: |
24be5ae3 JM |
284 | /* Level sensitive - active low */ |
285 | if (level) { | |
d12d51d5 | 286 | LOG_IRQ("%s: stop the CPU\n", __func__); |
24be5ae3 JM |
287 | env->halted = 1; |
288 | } else { | |
d12d51d5 | 289 | LOG_IRQ("%s: restart the CPU\n", __func__); |
24be5ae3 JM |
290 | env->halted = 0; |
291 | } | |
292 | break; | |
4e290a0b | 293 | case PPC40x_INPUT_DEBUG: |
24be5ae3 | 294 | /* Level sensitive - active high */ |
d12d51d5 | 295 | LOG_IRQ("%s: set the debug pin state to %d\n", |
a496775f | 296 | __func__, level); |
a750fc0b | 297 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
24be5ae3 JM |
298 | break; |
299 | default: | |
300 | /* Unknown pin - do nothing */ | |
d12d51d5 | 301 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
24be5ae3 JM |
302 | return; |
303 | } | |
304 | if (level) | |
305 | env->irq_input_state |= 1 << pin; | |
306 | else | |
307 | env->irq_input_state &= ~(1 << pin); | |
308 | } | |
309 | } | |
310 | ||
4e290a0b | 311 | void ppc40x_irq_init (CPUState *env) |
24be5ae3 | 312 | { |
4e290a0b JM |
313 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, |
314 | env, PPC40x_INPUT_NB); | |
24be5ae3 JM |
315 | } |
316 | ||
9fddaa0c | 317 | /*****************************************************************************/ |
e9df014c | 318 | /* PowerPC time base and decrementer emulation */ |
9fddaa0c FB |
319 | struct ppc_tb_t { |
320 | /* Time base management */ | |
dbdd2506 JM |
321 | int64_t tb_offset; /* Compensation */ |
322 | int64_t atb_offset; /* Compensation */ | |
323 | uint32_t tb_freq; /* TB frequency */ | |
9fddaa0c | 324 | /* Decrementer management */ |
dbdd2506 JM |
325 | uint64_t decr_next; /* Tick for next decr interrupt */ |
326 | uint32_t decr_freq; /* decrementer frequency */ | |
9fddaa0c | 327 | struct QEMUTimer *decr_timer; |
58a7d328 JM |
328 | /* Hypervisor decrementer management */ |
329 | uint64_t hdecr_next; /* Tick for next hdecr interrupt */ | |
330 | struct QEMUTimer *hdecr_timer; | |
331 | uint64_t purr_load; | |
332 | uint64_t purr_start; | |
47103572 | 333 | void *opaque; |
9fddaa0c FB |
334 | }; |
335 | ||
dbdd2506 | 336 | static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk, |
b068d6a7 | 337 | int64_t tb_offset) |
9fddaa0c FB |
338 | { |
339 | /* TB time in tb periods */ | |
dbdd2506 | 340 | return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset; |
9fddaa0c FB |
341 | } |
342 | ||
343 | uint32_t cpu_ppc_load_tbl (CPUState *env) | |
344 | { | |
345 | ppc_tb_t *tb_env = env->tb_env; | |
346 | uint64_t tb; | |
347 | ||
dbdd2506 | 348 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
d12d51d5 | 349 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
9fddaa0c FB |
350 | |
351 | return tb & 0xFFFFFFFF; | |
352 | } | |
353 | ||
b068d6a7 | 354 | static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env) |
9fddaa0c FB |
355 | { |
356 | ppc_tb_t *tb_env = env->tb_env; | |
357 | uint64_t tb; | |
358 | ||
dbdd2506 | 359 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
d12d51d5 | 360 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
76a66253 | 361 | |
9fddaa0c FB |
362 | return tb >> 32; |
363 | } | |
364 | ||
8a84de23 JM |
365 | uint32_t cpu_ppc_load_tbu (CPUState *env) |
366 | { | |
367 | return _cpu_ppc_load_tbu(env); | |
368 | } | |
369 | ||
dbdd2506 | 370 | static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk, |
b068d6a7 JM |
371 | int64_t *tb_offsetp, |
372 | uint64_t value) | |
9fddaa0c | 373 | { |
dbdd2506 | 374 | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); |
d12d51d5 | 375 | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
aae9366a | 376 | __func__, value, *tb_offsetp); |
9fddaa0c FB |
377 | } |
378 | ||
a062e36c JM |
379 | void cpu_ppc_store_tbl (CPUState *env, uint32_t value) |
380 | { | |
381 | ppc_tb_t *tb_env = env->tb_env; | |
382 | uint64_t tb; | |
383 | ||
dbdd2506 | 384 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
a062e36c | 385 | tb &= 0xFFFFFFFF00000000ULL; |
dbdd2506 JM |
386 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
387 | &tb_env->tb_offset, tb | (uint64_t)value); | |
a062e36c JM |
388 | } |
389 | ||
b068d6a7 | 390 | static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
9fddaa0c FB |
391 | { |
392 | ppc_tb_t *tb_env = env->tb_env; | |
a062e36c | 393 | uint64_t tb; |
9fddaa0c | 394 | |
dbdd2506 | 395 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
a062e36c | 396 | tb &= 0x00000000FFFFFFFFULL; |
dbdd2506 JM |
397 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
398 | &tb_env->tb_offset, ((uint64_t)value << 32) | tb); | |
9fddaa0c FB |
399 | } |
400 | ||
8a84de23 JM |
401 | void cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
402 | { | |
403 | _cpu_ppc_store_tbu(env, value); | |
404 | } | |
405 | ||
a062e36c JM |
406 | uint32_t cpu_ppc_load_atbl (CPUState *env) |
407 | { | |
408 | ppc_tb_t *tb_env = env->tb_env; | |
409 | uint64_t tb; | |
410 | ||
dbdd2506 | 411 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
d12d51d5 | 412 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
a062e36c JM |
413 | |
414 | return tb & 0xFFFFFFFF; | |
415 | } | |
416 | ||
417 | uint32_t cpu_ppc_load_atbu (CPUState *env) | |
418 | { | |
419 | ppc_tb_t *tb_env = env->tb_env; | |
420 | uint64_t tb; | |
421 | ||
dbdd2506 | 422 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
d12d51d5 | 423 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
a062e36c JM |
424 | |
425 | return tb >> 32; | |
426 | } | |
427 | ||
428 | void cpu_ppc_store_atbl (CPUState *env, uint32_t value) | |
429 | { | |
430 | ppc_tb_t *tb_env = env->tb_env; | |
431 | uint64_t tb; | |
432 | ||
dbdd2506 | 433 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
a062e36c | 434 | tb &= 0xFFFFFFFF00000000ULL; |
dbdd2506 JM |
435 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
436 | &tb_env->atb_offset, tb | (uint64_t)value); | |
a062e36c JM |
437 | } |
438 | ||
439 | void cpu_ppc_store_atbu (CPUState *env, uint32_t value) | |
9fddaa0c FB |
440 | { |
441 | ppc_tb_t *tb_env = env->tb_env; | |
a062e36c | 442 | uint64_t tb; |
9fddaa0c | 443 | |
dbdd2506 | 444 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
a062e36c | 445 | tb &= 0x00000000FFFFFFFFULL; |
dbdd2506 JM |
446 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
447 | &tb_env->atb_offset, ((uint64_t)value << 32) | tb); | |
448 | } | |
449 | ||
450 | static void cpu_ppc_tb_stop (CPUState *env) | |
451 | { | |
452 | ppc_tb_t *tb_env = env->tb_env; | |
453 | uint64_t tb, atb, vmclk; | |
454 | ||
455 | /* If the time base is already frozen, do nothing */ | |
456 | if (tb_env->tb_freq != 0) { | |
457 | vmclk = qemu_get_clock(vm_clock); | |
458 | /* Get the time base */ | |
459 | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); | |
460 | /* Get the alternate time base */ | |
461 | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); | |
462 | /* Store the time base value (ie compute the current offset) */ | |
463 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); | |
464 | /* Store the alternate time base value (compute the current offset) */ | |
465 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); | |
466 | /* Set the time base frequency to zero */ | |
467 | tb_env->tb_freq = 0; | |
468 | /* Now, the time bases are frozen to tb_offset / atb_offset value */ | |
469 | } | |
470 | } | |
471 | ||
472 | static void cpu_ppc_tb_start (CPUState *env) | |
473 | { | |
474 | ppc_tb_t *tb_env = env->tb_env; | |
475 | uint64_t tb, atb, vmclk; | |
aae9366a | 476 | |
dbdd2506 JM |
477 | /* If the time base is not frozen, do nothing */ |
478 | if (tb_env->tb_freq == 0) { | |
479 | vmclk = qemu_get_clock(vm_clock); | |
480 | /* Get the time base from tb_offset */ | |
481 | tb = tb_env->tb_offset; | |
482 | /* Get the alternate time base from atb_offset */ | |
483 | atb = tb_env->atb_offset; | |
484 | /* Restore the tb frequency from the decrementer frequency */ | |
485 | tb_env->tb_freq = tb_env->decr_freq; | |
486 | /* Store the time base value */ | |
487 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); | |
488 | /* Store the alternate time base value */ | |
489 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); | |
490 | } | |
9fddaa0c FB |
491 | } |
492 | ||
b068d6a7 JM |
493 | static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, |
494 | uint64_t *next) | |
9fddaa0c FB |
495 | { |
496 | ppc_tb_t *tb_env = env->tb_env; | |
497 | uint32_t decr; | |
4e588a4d | 498 | int64_t diff; |
9fddaa0c | 499 | |
4e588a4d FB |
500 | diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
501 | if (diff >= 0) | |
dbdd2506 | 502 | decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); |
4e588a4d | 503 | else |
dbdd2506 | 504 | decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); |
d12d51d5 | 505 | LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); |
76a66253 | 506 | |
9fddaa0c FB |
507 | return decr; |
508 | } | |
509 | ||
58a7d328 JM |
510 | uint32_t cpu_ppc_load_decr (CPUState *env) |
511 | { | |
512 | ppc_tb_t *tb_env = env->tb_env; | |
513 | ||
514 | return _cpu_ppc_load_decr(env, &tb_env->decr_next); | |
515 | } | |
516 | ||
58a7d328 JM |
517 | uint32_t cpu_ppc_load_hdecr (CPUState *env) |
518 | { | |
519 | ppc_tb_t *tb_env = env->tb_env; | |
520 | ||
521 | return _cpu_ppc_load_decr(env, &tb_env->hdecr_next); | |
522 | } | |
523 | ||
524 | uint64_t cpu_ppc_load_purr (CPUState *env) | |
525 | { | |
526 | ppc_tb_t *tb_env = env->tb_env; | |
527 | uint64_t diff; | |
528 | ||
529 | diff = qemu_get_clock(vm_clock) - tb_env->purr_start; | |
b33c17e1 | 530 | |
58a7d328 JM |
531 | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec); |
532 | } | |
58a7d328 | 533 | |
9fddaa0c FB |
534 | /* When decrementer expires, |
535 | * all we need to do is generate or queue a CPU exception | |
536 | */ | |
b068d6a7 | 537 | static always_inline void cpu_ppc_decr_excp (CPUState *env) |
9fddaa0c FB |
538 | { |
539 | /* Raise it */ | |
d12d51d5 | 540 | LOG_TB("raise decrementer exception\n"); |
47103572 | 541 | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); |
9fddaa0c FB |
542 | } |
543 | ||
b068d6a7 | 544 | static always_inline void cpu_ppc_hdecr_excp (CPUState *env) |
58a7d328 JM |
545 | { |
546 | /* Raise it */ | |
d12d51d5 | 547 | LOG_TB("raise decrementer exception\n"); |
58a7d328 JM |
548 | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); |
549 | } | |
550 | ||
551 | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, | |
b33c17e1 JM |
552 | struct QEMUTimer *timer, |
553 | void (*raise_excp)(CPUState *), | |
554 | uint32_t decr, uint32_t value, | |
555 | int is_excp) | |
9fddaa0c FB |
556 | { |
557 | ppc_tb_t *tb_env = env->tb_env; | |
558 | uint64_t now, next; | |
559 | ||
d12d51d5 | 560 | LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
aae9366a | 561 | decr, value); |
9fddaa0c | 562 | now = qemu_get_clock(vm_clock); |
dbdd2506 | 563 | next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); |
9fddaa0c | 564 | if (is_excp) |
58a7d328 | 565 | next += *nextp - now; |
9fddaa0c | 566 | if (next == now) |
76a66253 | 567 | next++; |
58a7d328 | 568 | *nextp = next; |
9fddaa0c | 569 | /* Adjust timer */ |
58a7d328 | 570 | qemu_mod_timer(timer, next); |
9fddaa0c FB |
571 | /* If we set a negative value and the decrementer was positive, |
572 | * raise an exception. | |
573 | */ | |
574 | if ((value & 0x80000000) && !(decr & 0x80000000)) | |
58a7d328 JM |
575 | (*raise_excp)(env); |
576 | } | |
577 | ||
b068d6a7 JM |
578 | static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
579 | uint32_t value, int is_excp) | |
58a7d328 JM |
580 | { |
581 | ppc_tb_t *tb_env = env->tb_env; | |
582 | ||
583 | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, | |
584 | &cpu_ppc_decr_excp, decr, value, is_excp); | |
9fddaa0c FB |
585 | } |
586 | ||
587 | void cpu_ppc_store_decr (CPUState *env, uint32_t value) | |
588 | { | |
589 | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0); | |
590 | } | |
591 | ||
592 | static void cpu_ppc_decr_cb (void *opaque) | |
593 | { | |
594 | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); | |
595 | } | |
596 | ||
b068d6a7 JM |
597 | static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr, |
598 | uint32_t value, int is_excp) | |
58a7d328 JM |
599 | { |
600 | ppc_tb_t *tb_env = env->tb_env; | |
601 | ||
b172c56a JM |
602 | if (tb_env->hdecr_timer != NULL) { |
603 | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, | |
604 | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); | |
605 | } | |
58a7d328 JM |
606 | } |
607 | ||
608 | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value) | |
609 | { | |
610 | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0); | |
611 | } | |
612 | ||
613 | static void cpu_ppc_hdecr_cb (void *opaque) | |
614 | { | |
615 | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); | |
616 | } | |
617 | ||
618 | void cpu_ppc_store_purr (CPUState *env, uint64_t value) | |
619 | { | |
620 | ppc_tb_t *tb_env = env->tb_env; | |
621 | ||
622 | tb_env->purr_load = value; | |
623 | tb_env->purr_start = qemu_get_clock(vm_clock); | |
624 | } | |
58a7d328 | 625 | |
8ecc7913 JM |
626 | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
627 | { | |
628 | CPUState *env = opaque; | |
629 | ppc_tb_t *tb_env = env->tb_env; | |
630 | ||
631 | tb_env->tb_freq = freq; | |
dbdd2506 | 632 | tb_env->decr_freq = freq; |
8ecc7913 JM |
633 | /* There is a bug in Linux 2.4 kernels: |
634 | * if a decrementer exception is pending when it enables msr_ee at startup, | |
635 | * it's not ready to handle it... | |
636 | */ | |
637 | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); | |
58a7d328 JM |
638 | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
639 | cpu_ppc_store_purr(env, 0x0000000000000000ULL); | |
8ecc7913 JM |
640 | } |
641 | ||
9fddaa0c | 642 | /* Set up (once) timebase frequency (in Hz) */ |
8ecc7913 | 643 | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
9fddaa0c FB |
644 | { |
645 | ppc_tb_t *tb_env; | |
646 | ||
647 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); | |
648 | if (tb_env == NULL) | |
649 | return NULL; | |
650 | env->tb_env = tb_env; | |
8ecc7913 JM |
651 | /* Create new timer */ |
652 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); | |
b172c56a JM |
653 | if (0) { |
654 | /* XXX: find a suitable condition to enable the hypervisor decrementer | |
655 | */ | |
656 | tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); | |
657 | } else { | |
658 | tb_env->hdecr_timer = NULL; | |
659 | } | |
8ecc7913 | 660 | cpu_ppc_set_tb_clk(env, freq); |
9fddaa0c | 661 | |
8ecc7913 | 662 | return &cpu_ppc_set_tb_clk; |
9fddaa0c FB |
663 | } |
664 | ||
76a66253 | 665 | /* Specific helpers for POWER & PowerPC 601 RTC */ |
b1d8e52e BS |
666 | #if 0 |
667 | static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env) | |
76a66253 JM |
668 | { |
669 | return cpu_ppc_tb_init(env, 7812500); | |
670 | } | |
b1d8e52e | 671 | #endif |
76a66253 JM |
672 | |
673 | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value) | |
8a84de23 JM |
674 | { |
675 | _cpu_ppc_store_tbu(env, value); | |
676 | } | |
76a66253 JM |
677 | |
678 | uint32_t cpu_ppc601_load_rtcu (CPUState *env) | |
8a84de23 JM |
679 | { |
680 | return _cpu_ppc_load_tbu(env); | |
681 | } | |
76a66253 JM |
682 | |
683 | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value) | |
684 | { | |
685 | cpu_ppc_store_tbl(env, value & 0x3FFFFF80); | |
686 | } | |
687 | ||
688 | uint32_t cpu_ppc601_load_rtcl (CPUState *env) | |
689 | { | |
690 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; | |
691 | } | |
692 | ||
636aaad7 | 693 | /*****************************************************************************/ |
76a66253 | 694 | /* Embedded PowerPC timers */ |
636aaad7 JM |
695 | |
696 | /* PIT, FIT & WDT */ | |
697 | typedef struct ppcemb_timer_t ppcemb_timer_t; | |
698 | struct ppcemb_timer_t { | |
699 | uint64_t pit_reload; /* PIT auto-reload value */ | |
700 | uint64_t fit_next; /* Tick for next FIT interrupt */ | |
701 | struct QEMUTimer *fit_timer; | |
702 | uint64_t wdt_next; /* Tick for next WDT interrupt */ | |
703 | struct QEMUTimer *wdt_timer; | |
704 | }; | |
3b46e624 | 705 | |
636aaad7 JM |
706 | /* Fixed interval timer */ |
707 | static void cpu_4xx_fit_cb (void *opaque) | |
708 | { | |
709 | CPUState *env; | |
710 | ppc_tb_t *tb_env; | |
711 | ppcemb_timer_t *ppcemb_timer; | |
712 | uint64_t now, next; | |
713 | ||
714 | env = opaque; | |
715 | tb_env = env->tb_env; | |
716 | ppcemb_timer = tb_env->opaque; | |
717 | now = qemu_get_clock(vm_clock); | |
718 | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { | |
719 | case 0: | |
720 | next = 1 << 9; | |
721 | break; | |
722 | case 1: | |
723 | next = 1 << 13; | |
724 | break; | |
725 | case 2: | |
726 | next = 1 << 17; | |
727 | break; | |
728 | case 3: | |
729 | next = 1 << 21; | |
730 | break; | |
731 | default: | |
732 | /* Cannot occur, but makes gcc happy */ | |
733 | return; | |
734 | } | |
735 | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); | |
736 | if (next == now) | |
737 | next++; | |
738 | qemu_mod_timer(ppcemb_timer->fit_timer, next); | |
636aaad7 JM |
739 | env->spr[SPR_40x_TSR] |= 1 << 26; |
740 | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) | |
741 | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1); | |
d12d51d5 | 742 | LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, |
e96efcfc | 743 | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
636aaad7 | 744 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
636aaad7 JM |
745 | } |
746 | ||
747 | /* Programmable interval timer */ | |
4b6d0a4c | 748 | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
76a66253 | 749 | { |
636aaad7 JM |
750 | ppcemb_timer_t *ppcemb_timer; |
751 | uint64_t now, next; | |
752 | ||
636aaad7 | 753 | ppcemb_timer = tb_env->opaque; |
4b6d0a4c JM |
754 | if (ppcemb_timer->pit_reload <= 1 || |
755 | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || | |
756 | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { | |
757 | /* Stop PIT */ | |
d12d51d5 | 758 | LOG_TB("%s: stop PIT\n", __func__); |
4b6d0a4c JM |
759 | qemu_del_timer(tb_env->decr_timer); |
760 | } else { | |
d12d51d5 | 761 | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
4b6d0a4c | 762 | __func__, ppcemb_timer->pit_reload); |
4b6d0a4c | 763 | now = qemu_get_clock(vm_clock); |
636aaad7 | 764 | next = now + muldiv64(ppcemb_timer->pit_reload, |
dbdd2506 | 765 | ticks_per_sec, tb_env->decr_freq); |
4b6d0a4c JM |
766 | if (is_excp) |
767 | next += tb_env->decr_next - now; | |
636aaad7 JM |
768 | if (next == now) |
769 | next++; | |
770 | qemu_mod_timer(tb_env->decr_timer, next); | |
771 | tb_env->decr_next = next; | |
772 | } | |
4b6d0a4c JM |
773 | } |
774 | ||
775 | static void cpu_4xx_pit_cb (void *opaque) | |
776 | { | |
777 | CPUState *env; | |
778 | ppc_tb_t *tb_env; | |
779 | ppcemb_timer_t *ppcemb_timer; | |
780 | ||
781 | env = opaque; | |
782 | tb_env = env->tb_env; | |
783 | ppcemb_timer = tb_env->opaque; | |
636aaad7 JM |
784 | env->spr[SPR_40x_TSR] |= 1 << 27; |
785 | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) | |
786 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1); | |
4b6d0a4c | 787 | start_stop_pit(env, tb_env, 1); |
d12d51d5 | 788 | LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " |
e96efcfc JM |
789 | "%016" PRIx64 "\n", __func__, |
790 | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), | |
791 | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), | |
636aaad7 JM |
792 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
793 | ppcemb_timer->pit_reload); | |
636aaad7 JM |
794 | } |
795 | ||
796 | /* Watchdog timer */ | |
797 | static void cpu_4xx_wdt_cb (void *opaque) | |
798 | { | |
799 | CPUState *env; | |
800 | ppc_tb_t *tb_env; | |
801 | ppcemb_timer_t *ppcemb_timer; | |
802 | uint64_t now, next; | |
803 | ||
804 | env = opaque; | |
805 | tb_env = env->tb_env; | |
806 | ppcemb_timer = tb_env->opaque; | |
807 | now = qemu_get_clock(vm_clock); | |
808 | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { | |
809 | case 0: | |
810 | next = 1 << 17; | |
811 | break; | |
812 | case 1: | |
813 | next = 1 << 21; | |
814 | break; | |
815 | case 2: | |
816 | next = 1 << 25; | |
817 | break; | |
818 | case 3: | |
819 | next = 1 << 29; | |
820 | break; | |
821 | default: | |
822 | /* Cannot occur, but makes gcc happy */ | |
823 | return; | |
824 | } | |
dbdd2506 | 825 | next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); |
636aaad7 JM |
826 | if (next == now) |
827 | next++; | |
d12d51d5 | 828 | LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, |
636aaad7 | 829 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
636aaad7 JM |
830 | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
831 | case 0x0: | |
832 | case 0x1: | |
833 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); | |
834 | ppcemb_timer->wdt_next = next; | |
835 | env->spr[SPR_40x_TSR] |= 1 << 31; | |
836 | break; | |
837 | case 0x2: | |
838 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); | |
839 | ppcemb_timer->wdt_next = next; | |
840 | env->spr[SPR_40x_TSR] |= 1 << 30; | |
841 | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) | |
842 | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1); | |
843 | break; | |
844 | case 0x3: | |
845 | env->spr[SPR_40x_TSR] &= ~0x30000000; | |
846 | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; | |
847 | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { | |
848 | case 0x0: | |
849 | /* No reset */ | |
850 | break; | |
851 | case 0x1: /* Core reset */ | |
8ecc7913 JM |
852 | ppc40x_core_reset(env); |
853 | break; | |
636aaad7 | 854 | case 0x2: /* Chip reset */ |
8ecc7913 JM |
855 | ppc40x_chip_reset(env); |
856 | break; | |
636aaad7 | 857 | case 0x3: /* System reset */ |
8ecc7913 JM |
858 | ppc40x_system_reset(env); |
859 | break; | |
636aaad7 JM |
860 | } |
861 | } | |
76a66253 JM |
862 | } |
863 | ||
864 | void store_40x_pit (CPUState *env, target_ulong val) | |
865 | { | |
636aaad7 JM |
866 | ppc_tb_t *tb_env; |
867 | ppcemb_timer_t *ppcemb_timer; | |
636aaad7 JM |
868 | |
869 | tb_env = env->tb_env; | |
870 | ppcemb_timer = tb_env->opaque; | |
d12d51d5 | 871 | LOG_TB("%s val" ADDRX "\n", __func__, val); |
636aaad7 | 872 | ppcemb_timer->pit_reload = val; |
4b6d0a4c | 873 | start_stop_pit(env, tb_env, 0); |
76a66253 JM |
874 | } |
875 | ||
636aaad7 | 876 | target_ulong load_40x_pit (CPUState *env) |
76a66253 | 877 | { |
636aaad7 | 878 | return cpu_ppc_load_decr(env); |
76a66253 JM |
879 | } |
880 | ||
881 | void store_booke_tsr (CPUState *env, target_ulong val) | |
882 | { | |
d12d51d5 | 883 | LOG_TB("%s: val " ADDRX "\n", __func__, val); |
4b6d0a4c JM |
884 | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); |
885 | if (val & 0x80000000) | |
886 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 0); | |
636aaad7 JM |
887 | } |
888 | ||
889 | void store_booke_tcr (CPUState *env, target_ulong val) | |
890 | { | |
4b6d0a4c JM |
891 | ppc_tb_t *tb_env; |
892 | ||
893 | tb_env = env->tb_env; | |
d12d51d5 | 894 | LOG_TB("%s: val " ADDRX "\n", __func__, val); |
4b6d0a4c JM |
895 | env->spr[SPR_40x_TCR] = val & 0xFFC00000; |
896 | start_stop_pit(env, tb_env, 1); | |
8ecc7913 | 897 | cpu_4xx_wdt_cb(env); |
636aaad7 JM |
898 | } |
899 | ||
4b6d0a4c JM |
900 | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
901 | { | |
902 | CPUState *env = opaque; | |
903 | ppc_tb_t *tb_env = env->tb_env; | |
904 | ||
d12d51d5 | 905 | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
aae9366a | 906 | freq); |
4b6d0a4c | 907 | tb_env->tb_freq = freq; |
dbdd2506 | 908 | tb_env->decr_freq = freq; |
4b6d0a4c JM |
909 | /* XXX: we should also update all timers */ |
910 | } | |
911 | ||
8ecc7913 | 912 | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) |
636aaad7 JM |
913 | { |
914 | ppc_tb_t *tb_env; | |
915 | ppcemb_timer_t *ppcemb_timer; | |
916 | ||
8ecc7913 | 917 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); |
4b6d0a4c | 918 | if (tb_env == NULL) { |
8ecc7913 | 919 | return NULL; |
4b6d0a4c | 920 | } |
8ecc7913 | 921 | env->tb_env = tb_env; |
636aaad7 | 922 | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t)); |
8ecc7913 | 923 | tb_env->tb_freq = freq; |
dbdd2506 | 924 | tb_env->decr_freq = freq; |
636aaad7 | 925 | tb_env->opaque = ppcemb_timer; |
d12d51d5 | 926 | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
636aaad7 JM |
927 | if (ppcemb_timer != NULL) { |
928 | /* We use decr timer for PIT */ | |
929 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); | |
930 | ppcemb_timer->fit_timer = | |
931 | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); | |
932 | ppcemb_timer->wdt_timer = | |
933 | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); | |
934 | } | |
8ecc7913 | 935 | |
4b6d0a4c | 936 | return &ppc_emb_set_tb_clk; |
76a66253 JM |
937 | } |
938 | ||
2e719ba3 JM |
939 | /*****************************************************************************/ |
940 | /* Embedded PowerPC Device Control Registers */ | |
941 | typedef struct ppc_dcrn_t ppc_dcrn_t; | |
942 | struct ppc_dcrn_t { | |
943 | dcr_read_cb dcr_read; | |
944 | dcr_write_cb dcr_write; | |
945 | void *opaque; | |
946 | }; | |
947 | ||
a750fc0b JM |
948 | /* XXX: on 460, DCR addresses are 32 bits wide, |
949 | * using DCRIPR to get the 22 upper bits of the DCR address | |
950 | */ | |
2e719ba3 JM |
951 | #define DCRN_NB 1024 |
952 | struct ppc_dcr_t { | |
953 | ppc_dcrn_t dcrn[DCRN_NB]; | |
954 | int (*read_error)(int dcrn); | |
955 | int (*write_error)(int dcrn); | |
956 | }; | |
957 | ||
958 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) | |
959 | { | |
960 | ppc_dcrn_t *dcr; | |
961 | ||
962 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
963 | goto error; | |
964 | dcr = &dcr_env->dcrn[dcrn]; | |
965 | if (dcr->dcr_read == NULL) | |
966 | goto error; | |
967 | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); | |
968 | ||
969 | return 0; | |
970 | ||
971 | error: | |
972 | if (dcr_env->read_error != NULL) | |
973 | return (*dcr_env->read_error)(dcrn); | |
974 | ||
975 | return -1; | |
976 | } | |
977 | ||
978 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) | |
979 | { | |
980 | ppc_dcrn_t *dcr; | |
981 | ||
982 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
983 | goto error; | |
984 | dcr = &dcr_env->dcrn[dcrn]; | |
985 | if (dcr->dcr_write == NULL) | |
986 | goto error; | |
987 | (*dcr->dcr_write)(dcr->opaque, dcrn, val); | |
988 | ||
989 | return 0; | |
990 | ||
991 | error: | |
992 | if (dcr_env->write_error != NULL) | |
993 | return (*dcr_env->write_error)(dcrn); | |
994 | ||
995 | return -1; | |
996 | } | |
997 | ||
998 | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, | |
999 | dcr_read_cb dcr_read, dcr_write_cb dcr_write) | |
1000 | { | |
1001 | ppc_dcr_t *dcr_env; | |
1002 | ppc_dcrn_t *dcr; | |
1003 | ||
1004 | dcr_env = env->dcr_env; | |
1005 | if (dcr_env == NULL) | |
1006 | return -1; | |
1007 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1008 | return -1; | |
1009 | dcr = &dcr_env->dcrn[dcrn]; | |
1010 | if (dcr->opaque != NULL || | |
1011 | dcr->dcr_read != NULL || | |
1012 | dcr->dcr_write != NULL) | |
1013 | return -1; | |
1014 | dcr->opaque = opaque; | |
1015 | dcr->dcr_read = dcr_read; | |
1016 | dcr->dcr_write = dcr_write; | |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), | |
1022 | int (*write_error)(int dcrn)) | |
1023 | { | |
1024 | ppc_dcr_t *dcr_env; | |
1025 | ||
1026 | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t)); | |
1027 | if (dcr_env == NULL) | |
1028 | return -1; | |
1029 | dcr_env->read_error = read_error; | |
1030 | dcr_env->write_error = write_error; | |
1031 | env->dcr_env = dcr_env; | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
9fddaa0c FB |
1036 | #if 0 |
1037 | /*****************************************************************************/ | |
1038 | /* Handle system reset (for now, just stop emulation) */ | |
1039 | void cpu_ppc_reset (CPUState *env) | |
1040 | { | |
1041 | printf("Reset asked... Stop emulation\n"); | |
1042 | abort(); | |
1043 | } | |
1044 | #endif | |
1045 | ||
64201201 FB |
1046 | /*****************************************************************************/ |
1047 | /* Debug port */ | |
fd0bbb12 | 1048 | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
64201201 FB |
1049 | { |
1050 | addr &= 0xF; | |
1051 | switch (addr) { | |
1052 | case 0: | |
1053 | printf("%c", val); | |
1054 | break; | |
1055 | case 1: | |
1056 | printf("\n"); | |
1057 | fflush(stdout); | |
1058 | break; | |
1059 | case 2: | |
aae9366a | 1060 | printf("Set loglevel to %04" PRIx32 "\n", val); |
fd0bbb12 | 1061 | cpu_set_log(val | 0x100); |
64201201 FB |
1062 | break; |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /*****************************************************************************/ | |
1067 | /* NVRAM helpers */ | |
3cbee15b | 1068 | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
64201201 | 1069 | { |
3cbee15b | 1070 | return (*nvram->read_fn)(nvram->opaque, addr);; |
64201201 FB |
1071 | } |
1072 | ||
3cbee15b | 1073 | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
64201201 | 1074 | { |
3cbee15b | 1075 | (*nvram->write_fn)(nvram->opaque, addr, val); |
64201201 FB |
1076 | } |
1077 | ||
3cbee15b | 1078 | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value) |
64201201 | 1079 | { |
3cbee15b | 1080 | nvram_write(nvram, addr, value); |
64201201 FB |
1081 | } |
1082 | ||
3cbee15b JM |
1083 | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) |
1084 | { | |
1085 | return nvram_read(nvram, addr); | |
1086 | } | |
1087 | ||
1088 | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value) | |
1089 | { | |
1090 | nvram_write(nvram, addr, value >> 8); | |
1091 | nvram_write(nvram, addr + 1, value & 0xFF); | |
1092 | } | |
1093 | ||
1094 | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) | |
64201201 FB |
1095 | { |
1096 | uint16_t tmp; | |
1097 | ||
3cbee15b JM |
1098 | tmp = nvram_read(nvram, addr) << 8; |
1099 | tmp |= nvram_read(nvram, addr + 1); | |
1100 | ||
64201201 FB |
1101 | return tmp; |
1102 | } | |
1103 | ||
3cbee15b | 1104 | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value) |
64201201 | 1105 | { |
3cbee15b JM |
1106 | nvram_write(nvram, addr, value >> 24); |
1107 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); | |
1108 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); | |
1109 | nvram_write(nvram, addr + 3, value & 0xFF); | |
64201201 FB |
1110 | } |
1111 | ||
3cbee15b | 1112 | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
64201201 FB |
1113 | { |
1114 | uint32_t tmp; | |
1115 | ||
3cbee15b JM |
1116 | tmp = nvram_read(nvram, addr) << 24; |
1117 | tmp |= nvram_read(nvram, addr + 1) << 16; | |
1118 | tmp |= nvram_read(nvram, addr + 2) << 8; | |
1119 | tmp |= nvram_read(nvram, addr + 3); | |
76a66253 | 1120 | |
64201201 FB |
1121 | return tmp; |
1122 | } | |
1123 | ||
3cbee15b | 1124 | void NVRAM_set_string (nvram_t *nvram, uint32_t addr, |
b55266b5 | 1125 | const char *str, uint32_t max) |
64201201 FB |
1126 | { |
1127 | int i; | |
1128 | ||
1129 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
3cbee15b | 1130 | nvram_write(nvram, addr + i, str[i]); |
64201201 | 1131 | } |
3cbee15b JM |
1132 | nvram_write(nvram, addr + i, str[i]); |
1133 | nvram_write(nvram, addr + max - 1, '\0'); | |
64201201 FB |
1134 | } |
1135 | ||
3cbee15b | 1136 | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
64201201 FB |
1137 | { |
1138 | int i; | |
1139 | ||
1140 | memset(dst, 0, max); | |
1141 | for (i = 0; i < max; i++) { | |
1142 | dst[i] = NVRAM_get_byte(nvram, addr + i); | |
1143 | if (dst[i] == '\0') | |
1144 | break; | |
1145 | } | |
1146 | ||
1147 | return i; | |
1148 | } | |
1149 | ||
1150 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) | |
1151 | { | |
1152 | uint16_t tmp; | |
1153 | uint16_t pd, pd1, pd2; | |
1154 | ||
1155 | tmp = prev >> 8; | |
1156 | pd = prev ^ value; | |
1157 | pd1 = pd & 0x000F; | |
1158 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; | |
1159 | tmp ^= (pd1 << 3) | (pd1 << 8); | |
1160 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); | |
1161 | ||
1162 | return tmp; | |
1163 | } | |
1164 | ||
b1d8e52e | 1165 | static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) |
64201201 FB |
1166 | { |
1167 | uint32_t i; | |
1168 | uint16_t crc = 0xFFFF; | |
1169 | int odd; | |
1170 | ||
1171 | odd = count & 1; | |
1172 | count &= ~1; | |
1173 | for (i = 0; i != count; i++) { | |
76a66253 | 1174 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
64201201 FB |
1175 | } |
1176 | if (odd) { | |
76a66253 | 1177 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); |
64201201 FB |
1178 | } |
1179 | ||
1180 | return crc; | |
1181 | } | |
1182 | ||
fd0bbb12 FB |
1183 | #define CMDLINE_ADDR 0x017ff000 |
1184 | ||
3cbee15b | 1185 | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, |
b55266b5 | 1186 | const char *arch, |
64201201 FB |
1187 | uint32_t RAM_size, int boot_device, |
1188 | uint32_t kernel_image, uint32_t kernel_size, | |
fd0bbb12 | 1189 | const char *cmdline, |
64201201 | 1190 | uint32_t initrd_image, uint32_t initrd_size, |
fd0bbb12 FB |
1191 | uint32_t NVRAM_image, |
1192 | int width, int height, int depth) | |
64201201 FB |
1193 | { |
1194 | uint16_t crc; | |
1195 | ||
1196 | /* Set parameters for Open Hack'Ware BIOS */ | |
1197 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
1198 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ | |
1199 | NVRAM_set_word(nvram, 0x14, NVRAM_size); | |
1200 | NVRAM_set_string(nvram, 0x20, arch, 16); | |
1201 | NVRAM_set_lword(nvram, 0x30, RAM_size); | |
1202 | NVRAM_set_byte(nvram, 0x34, boot_device); | |
1203 | NVRAM_set_lword(nvram, 0x38, kernel_image); | |
1204 | NVRAM_set_lword(nvram, 0x3C, kernel_size); | |
fd0bbb12 FB |
1205 | if (cmdline) { |
1206 | /* XXX: put the cmdline in NVRAM too ? */ | |
b55266b5 | 1207 | strcpy((char *)(phys_ram_base + CMDLINE_ADDR), cmdline); |
fd0bbb12 FB |
1208 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); |
1209 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); | |
1210 | } else { | |
1211 | NVRAM_set_lword(nvram, 0x40, 0); | |
1212 | NVRAM_set_lword(nvram, 0x44, 0); | |
1213 | } | |
64201201 FB |
1214 | NVRAM_set_lword(nvram, 0x48, initrd_image); |
1215 | NVRAM_set_lword(nvram, 0x4C, initrd_size); | |
1216 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); | |
fd0bbb12 FB |
1217 | |
1218 | NVRAM_set_word(nvram, 0x54, width); | |
1219 | NVRAM_set_word(nvram, 0x56, height); | |
1220 | NVRAM_set_word(nvram, 0x58, depth); | |
1221 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); | |
3cbee15b | 1222 | NVRAM_set_word(nvram, 0xFC, crc); |
64201201 FB |
1223 | |
1224 | return 0; | |
a541f297 | 1225 | } |