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a541f297 | 1 | /* |
e9df014c | 2 | * QEMU generic PowerPC hardware System Emulator |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
a541f297 | 24 | #include "vl.h" |
fd0bbb12 | 25 | #include "m48t59.h" |
a541f297 | 26 | |
e9df014c | 27 | //#define PPC_DEBUG_IRQ |
4b6d0a4c | 28 | //#define PPC_DEBUG_TB |
e9df014c | 29 | |
47103572 JM |
30 | extern FILE *logfile; |
31 | extern int loglevel; | |
32 | ||
00af685f | 33 | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
47103572 | 34 | { |
47103572 JM |
35 | if (level) { |
36 | env->pending_interrupts |= 1 << n_IRQ; | |
37 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
38 | } else { | |
39 | env->pending_interrupts &= ~(1 << n_IRQ); | |
40 | if (env->pending_interrupts == 0) | |
41 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
42 | } | |
e9df014c | 43 | #if defined(PPC_DEBUG_IRQ) |
a496775f JM |
44 | if (loglevel & CPU_LOG_INT) { |
45 | fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n", | |
46 | __func__, env, n_IRQ, level, | |
47 | env->pending_interrupts, env->interrupt_request); | |
48 | } | |
47103572 JM |
49 | #endif |
50 | } | |
51 | ||
e9df014c JM |
52 | /* PowerPC 6xx / 7xx internal IRQ controller */ |
53 | static void ppc6xx_set_irq (void *opaque, int pin, int level) | |
d537cf6c | 54 | { |
e9df014c JM |
55 | CPUState *env = opaque; |
56 | int cur_level; | |
d537cf6c | 57 | |
e9df014c | 58 | #if defined(PPC_DEBUG_IRQ) |
a496775f JM |
59 | if (loglevel & CPU_LOG_INT) { |
60 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, | |
61 | env, pin, level); | |
62 | } | |
e9df014c JM |
63 | #endif |
64 | cur_level = (env->irq_input_state >> pin) & 1; | |
65 | /* Don't generate spurious events */ | |
24be5ae3 | 66 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
e9df014c | 67 | switch (pin) { |
24be5ae3 JM |
68 | case PPC6xx_INPUT_INT: |
69 | /* Level sensitive - active high */ | |
e9df014c | 70 | #if defined(PPC_DEBUG_IRQ) |
a496775f JM |
71 | if (loglevel & CPU_LOG_INT) { |
72 | fprintf(logfile, "%s: set the external IRQ state to %d\n", | |
73 | __func__, level); | |
74 | } | |
e9df014c JM |
75 | #endif |
76 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); | |
77 | break; | |
24be5ae3 | 78 | case PPC6xx_INPUT_SMI: |
e9df014c JM |
79 | /* Level sensitive - active high */ |
80 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
81 | if (loglevel & CPU_LOG_INT) { |
82 | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", | |
83 | __func__, level); | |
84 | } | |
e9df014c JM |
85 | #endif |
86 | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); | |
87 | break; | |
24be5ae3 | 88 | case PPC6xx_INPUT_MCP: |
e9df014c JM |
89 | /* Negative edge sensitive */ |
90 | /* XXX: TODO: actual reaction may depends on HID0 status | |
91 | * 603/604/740/750: check HID0[EMCP] | |
92 | */ | |
93 | if (cur_level == 1 && level == 0) { | |
94 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
95 | if (loglevel & CPU_LOG_INT) { |
96 | fprintf(logfile, "%s: raise machine check state\n", | |
97 | __func__); | |
98 | } | |
e9df014c JM |
99 | #endif |
100 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); | |
101 | } | |
102 | break; | |
24be5ae3 | 103 | case PPC6xx_INPUT_CKSTP_IN: |
e9df014c JM |
104 | /* Level sensitive - active low */ |
105 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
106 | if (level) { | |
107 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
108 | if (loglevel & CPU_LOG_INT) { |
109 | fprintf(logfile, "%s: stop the CPU\n", __func__); | |
110 | } | |
e9df014c JM |
111 | #endif |
112 | env->halted = 1; | |
113 | } else { | |
114 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
115 | if (loglevel & CPU_LOG_INT) { |
116 | fprintf(logfile, "%s: restart the CPU\n", __func__); | |
117 | } | |
e9df014c JM |
118 | #endif |
119 | env->halted = 0; | |
120 | } | |
121 | break; | |
24be5ae3 | 122 | case PPC6xx_INPUT_HRESET: |
e9df014c JM |
123 | /* Level sensitive - active low */ |
124 | if (level) { | |
125 | #if 0 // XXX: TOFIX | |
126 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
127 | if (loglevel & CPU_LOG_INT) { |
128 | fprintf(logfile, "%s: reset the CPU\n", __func__); | |
129 | } | |
e9df014c JM |
130 | #endif |
131 | cpu_reset(env); | |
132 | #endif | |
133 | } | |
134 | break; | |
24be5ae3 | 135 | case PPC6xx_INPUT_SRESET: |
e9df014c | 136 | #if defined(PPC_DEBUG_IRQ) |
a496775f JM |
137 | if (loglevel & CPU_LOG_INT) { |
138 | fprintf(logfile, "%s: set the RESET IRQ state to %d\n", | |
139 | __func__, level); | |
140 | } | |
e9df014c JM |
141 | #endif |
142 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); | |
143 | break; | |
144 | default: | |
145 | /* Unknown pin - do nothing */ | |
146 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
147 | if (loglevel & CPU_LOG_INT) { |
148 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); | |
149 | } | |
e9df014c JM |
150 | #endif |
151 | return; | |
152 | } | |
153 | if (level) | |
154 | env->irq_input_state |= 1 << pin; | |
155 | else | |
156 | env->irq_input_state &= ~(1 << pin); | |
d537cf6c PB |
157 | } |
158 | } | |
159 | ||
e9df014c | 160 | void ppc6xx_irq_init (CPUState *env) |
47103572 | 161 | { |
e9df014c | 162 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6); |
47103572 JM |
163 | } |
164 | ||
00af685f | 165 | #if defined(TARGET_PPC64) |
d0dfae6e JM |
166 | /* PowerPC 970 internal IRQ controller */ |
167 | static void ppc970_set_irq (void *opaque, int pin, int level) | |
168 | { | |
169 | CPUState *env = opaque; | |
170 | int cur_level; | |
171 | ||
172 | #if defined(PPC_DEBUG_IRQ) | |
173 | if (loglevel & CPU_LOG_INT) { | |
174 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, | |
175 | env, pin, level); | |
176 | } | |
177 | #endif | |
178 | cur_level = (env->irq_input_state >> pin) & 1; | |
179 | /* Don't generate spurious events */ | |
180 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
181 | switch (pin) { | |
182 | case PPC970_INPUT_INT: | |
183 | /* Level sensitive - active high */ | |
184 | #if defined(PPC_DEBUG_IRQ) | |
185 | if (loglevel & CPU_LOG_INT) { | |
186 | fprintf(logfile, "%s: set the external IRQ state to %d\n", | |
187 | __func__, level); | |
188 | } | |
189 | #endif | |
190 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); | |
191 | break; | |
192 | case PPC970_INPUT_THINT: | |
193 | /* Level sensitive - active high */ | |
194 | #if defined(PPC_DEBUG_IRQ) | |
195 | if (loglevel & CPU_LOG_INT) { | |
196 | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__, | |
197 | level); | |
198 | } | |
199 | #endif | |
200 | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); | |
201 | break; | |
202 | case PPC970_INPUT_MCP: | |
203 | /* Negative edge sensitive */ | |
204 | /* XXX: TODO: actual reaction may depends on HID0 status | |
205 | * 603/604/740/750: check HID0[EMCP] | |
206 | */ | |
207 | if (cur_level == 1 && level == 0) { | |
208 | #if defined(PPC_DEBUG_IRQ) | |
209 | if (loglevel & CPU_LOG_INT) { | |
210 | fprintf(logfile, "%s: raise machine check state\n", | |
211 | __func__); | |
212 | } | |
213 | #endif | |
214 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); | |
215 | } | |
216 | break; | |
217 | case PPC970_INPUT_CKSTP: | |
218 | /* Level sensitive - active low */ | |
219 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
220 | if (level) { | |
221 | #if defined(PPC_DEBUG_IRQ) | |
222 | if (loglevel & CPU_LOG_INT) { | |
223 | fprintf(logfile, "%s: stop the CPU\n", __func__); | |
224 | } | |
225 | #endif | |
226 | env->halted = 1; | |
227 | } else { | |
228 | #if defined(PPC_DEBUG_IRQ) | |
229 | if (loglevel & CPU_LOG_INT) { | |
230 | fprintf(logfile, "%s: restart the CPU\n", __func__); | |
231 | } | |
232 | #endif | |
233 | env->halted = 0; | |
234 | } | |
235 | break; | |
236 | case PPC970_INPUT_HRESET: | |
237 | /* Level sensitive - active low */ | |
238 | if (level) { | |
239 | #if 0 // XXX: TOFIX | |
240 | #if defined(PPC_DEBUG_IRQ) | |
241 | if (loglevel & CPU_LOG_INT) { | |
242 | fprintf(logfile, "%s: reset the CPU\n", __func__); | |
243 | } | |
244 | #endif | |
245 | cpu_reset(env); | |
246 | #endif | |
247 | } | |
248 | break; | |
249 | case PPC970_INPUT_SRESET: | |
250 | #if defined(PPC_DEBUG_IRQ) | |
251 | if (loglevel & CPU_LOG_INT) { | |
252 | fprintf(logfile, "%s: set the RESET IRQ state to %d\n", | |
253 | __func__, level); | |
254 | } | |
255 | #endif | |
256 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); | |
257 | break; | |
258 | case PPC970_INPUT_TBEN: | |
259 | #if defined(PPC_DEBUG_IRQ) | |
260 | if (loglevel & CPU_LOG_INT) { | |
261 | fprintf(logfile, "%s: set the TBEN state to %d\n", __func__, | |
262 | level); | |
263 | } | |
264 | #endif | |
265 | /* XXX: TODO */ | |
266 | break; | |
267 | default: | |
268 | /* Unknown pin - do nothing */ | |
269 | #if defined(PPC_DEBUG_IRQ) | |
270 | if (loglevel & CPU_LOG_INT) { | |
271 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); | |
272 | } | |
273 | #endif | |
274 | return; | |
275 | } | |
276 | if (level) | |
277 | env->irq_input_state |= 1 << pin; | |
278 | else | |
279 | env->irq_input_state &= ~(1 << pin); | |
280 | } | |
281 | } | |
282 | ||
283 | void ppc970_irq_init (CPUState *env) | |
284 | { | |
285 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7); | |
286 | } | |
00af685f | 287 | #endif /* defined(TARGET_PPC64) */ |
d0dfae6e | 288 | |
4e290a0b JM |
289 | /* PowerPC 40x internal IRQ controller */ |
290 | static void ppc40x_set_irq (void *opaque, int pin, int level) | |
24be5ae3 JM |
291 | { |
292 | CPUState *env = opaque; | |
293 | int cur_level; | |
294 | ||
295 | #if defined(PPC_DEBUG_IRQ) | |
8ecc7913 JM |
296 | if (loglevel & CPU_LOG_INT) { |
297 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, | |
298 | env, pin, level); | |
299 | } | |
24be5ae3 JM |
300 | #endif |
301 | cur_level = (env->irq_input_state >> pin) & 1; | |
302 | /* Don't generate spurious events */ | |
303 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
304 | switch (pin) { | |
4e290a0b | 305 | case PPC40x_INPUT_RESET_SYS: |
8ecc7913 JM |
306 | if (level) { |
307 | #if defined(PPC_DEBUG_IRQ) | |
308 | if (loglevel & CPU_LOG_INT) { | |
309 | fprintf(logfile, "%s: reset the PowerPC system\n", | |
310 | __func__); | |
311 | } | |
312 | #endif | |
313 | ppc40x_system_reset(env); | |
314 | } | |
315 | break; | |
4e290a0b | 316 | case PPC40x_INPUT_RESET_CHIP: |
8ecc7913 JM |
317 | if (level) { |
318 | #if defined(PPC_DEBUG_IRQ) | |
319 | if (loglevel & CPU_LOG_INT) { | |
320 | fprintf(logfile, "%s: reset the PowerPC chip\n", __func__); | |
321 | } | |
322 | #endif | |
323 | ppc40x_chip_reset(env); | |
324 | } | |
325 | break; | |
4e290a0b | 326 | case PPC40x_INPUT_RESET_CORE: |
24be5ae3 JM |
327 | /* XXX: TODO: update DBSR[MRR] */ |
328 | if (level) { | |
24be5ae3 | 329 | #if defined(PPC_DEBUG_IRQ) |
8ecc7913 JM |
330 | if (loglevel & CPU_LOG_INT) { |
331 | fprintf(logfile, "%s: reset the PowerPC core\n", __func__); | |
332 | } | |
24be5ae3 | 333 | #endif |
8ecc7913 | 334 | ppc40x_core_reset(env); |
24be5ae3 JM |
335 | } |
336 | break; | |
4e290a0b | 337 | case PPC40x_INPUT_CINT: |
24be5ae3 JM |
338 | /* Level sensitive - active high */ |
339 | #if defined(PPC_DEBUG_IRQ) | |
8ecc7913 JM |
340 | if (loglevel & CPU_LOG_INT) { |
341 | fprintf(logfile, "%s: set the critical IRQ state to %d\n", | |
342 | __func__, level); | |
343 | } | |
24be5ae3 | 344 | #endif |
4e290a0b | 345 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
24be5ae3 | 346 | break; |
4e290a0b | 347 | case PPC40x_INPUT_INT: |
24be5ae3 JM |
348 | /* Level sensitive - active high */ |
349 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
350 | if (loglevel & CPU_LOG_INT) { |
351 | fprintf(logfile, "%s: set the external IRQ state to %d\n", | |
352 | __func__, level); | |
353 | } | |
24be5ae3 JM |
354 | #endif |
355 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); | |
356 | break; | |
4e290a0b | 357 | case PPC40x_INPUT_HALT: |
24be5ae3 JM |
358 | /* Level sensitive - active low */ |
359 | if (level) { | |
360 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
361 | if (loglevel & CPU_LOG_INT) { |
362 | fprintf(logfile, "%s: stop the CPU\n", __func__); | |
363 | } | |
24be5ae3 JM |
364 | #endif |
365 | env->halted = 1; | |
366 | } else { | |
367 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
368 | if (loglevel & CPU_LOG_INT) { |
369 | fprintf(logfile, "%s: restart the CPU\n", __func__); | |
370 | } | |
24be5ae3 JM |
371 | #endif |
372 | env->halted = 0; | |
373 | } | |
374 | break; | |
4e290a0b | 375 | case PPC40x_INPUT_DEBUG: |
24be5ae3 JM |
376 | /* Level sensitive - active high */ |
377 | #if defined(PPC_DEBUG_IRQ) | |
a496775f | 378 | if (loglevel & CPU_LOG_INT) { |
a750fc0b | 379 | fprintf(logfile, "%s: set the debug pin state to %d\n", |
a496775f JM |
380 | __func__, level); |
381 | } | |
24be5ae3 | 382 | #endif |
a750fc0b | 383 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
24be5ae3 JM |
384 | break; |
385 | default: | |
386 | /* Unknown pin - do nothing */ | |
387 | #if defined(PPC_DEBUG_IRQ) | |
a496775f JM |
388 | if (loglevel & CPU_LOG_INT) { |
389 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); | |
390 | } | |
24be5ae3 JM |
391 | #endif |
392 | return; | |
393 | } | |
394 | if (level) | |
395 | env->irq_input_state |= 1 << pin; | |
396 | else | |
397 | env->irq_input_state &= ~(1 << pin); | |
398 | } | |
399 | } | |
400 | ||
4e290a0b | 401 | void ppc40x_irq_init (CPUState *env) |
24be5ae3 | 402 | { |
4e290a0b JM |
403 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, |
404 | env, PPC40x_INPUT_NB); | |
24be5ae3 JM |
405 | } |
406 | ||
9fddaa0c | 407 | /*****************************************************************************/ |
e9df014c | 408 | /* PowerPC time base and decrementer emulation */ |
9fddaa0c FB |
409 | struct ppc_tb_t { |
410 | /* Time base management */ | |
411 | int64_t tb_offset; /* Compensation */ | |
a062e36c | 412 | int64_t atb_offset; /* Compensation */ |
9fddaa0c FB |
413 | uint32_t tb_freq; /* TB frequency */ |
414 | /* Decrementer management */ | |
415 | uint64_t decr_next; /* Tick for next decr interrupt */ | |
416 | struct QEMUTimer *decr_timer; | |
58a7d328 JM |
417 | #if defined(TARGET_PPC64H) |
418 | /* Hypervisor decrementer management */ | |
419 | uint64_t hdecr_next; /* Tick for next hdecr interrupt */ | |
420 | struct QEMUTimer *hdecr_timer; | |
421 | uint64_t purr_load; | |
422 | uint64_t purr_start; | |
423 | #endif | |
47103572 | 424 | void *opaque; |
9fddaa0c FB |
425 | }; |
426 | ||
b068d6a7 JM |
427 | static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, |
428 | int64_t tb_offset) | |
9fddaa0c FB |
429 | { |
430 | /* TB time in tb periods */ | |
431 | return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset, | |
76a66253 | 432 | tb_env->tb_freq, ticks_per_sec); |
9fddaa0c FB |
433 | } |
434 | ||
435 | uint32_t cpu_ppc_load_tbl (CPUState *env) | |
436 | { | |
437 | ppc_tb_t *tb_env = env->tb_env; | |
438 | uint64_t tb; | |
439 | ||
a062e36c JM |
440 | tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset); |
441 | #if defined(PPC_DEBUG_TB) | |
442 | if (loglevel != 0) { | |
443 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); | |
9fddaa0c FB |
444 | } |
445 | #endif | |
446 | ||
447 | return tb & 0xFFFFFFFF; | |
448 | } | |
449 | ||
b068d6a7 | 450 | static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env) |
9fddaa0c FB |
451 | { |
452 | ppc_tb_t *tb_env = env->tb_env; | |
453 | uint64_t tb; | |
454 | ||
a062e36c | 455 | tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset); |
4b6d0a4c JM |
456 | #if defined(PPC_DEBUG_TB) |
457 | if (loglevel != 0) { | |
a496775f JM |
458 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); |
459 | } | |
9fddaa0c | 460 | #endif |
76a66253 | 461 | |
9fddaa0c FB |
462 | return tb >> 32; |
463 | } | |
464 | ||
8a84de23 JM |
465 | uint32_t cpu_ppc_load_tbu (CPUState *env) |
466 | { | |
467 | return _cpu_ppc_load_tbu(env); | |
468 | } | |
469 | ||
b068d6a7 JM |
470 | static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, |
471 | int64_t *tb_offsetp, | |
472 | uint64_t value) | |
9fddaa0c | 473 | { |
a062e36c | 474 | *tb_offsetp = muldiv64(value, ticks_per_sec, tb_env->tb_freq) |
9fddaa0c | 475 | - qemu_get_clock(vm_clock); |
4b6d0a4c JM |
476 | #ifdef PPC_DEBUG_TB |
477 | if (loglevel != 0) { | |
478 | fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value, | |
a062e36c | 479 | *tb_offsetp); |
a496775f | 480 | } |
9fddaa0c FB |
481 | #endif |
482 | } | |
483 | ||
a062e36c JM |
484 | void cpu_ppc_store_tbl (CPUState *env, uint32_t value) |
485 | { | |
486 | ppc_tb_t *tb_env = env->tb_env; | |
487 | uint64_t tb; | |
488 | ||
489 | tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset); | |
490 | tb &= 0xFFFFFFFF00000000ULL; | |
491 | cpu_ppc_store_tb(tb_env, &tb_env->tb_offset, tb | (uint64_t)value); | |
492 | } | |
493 | ||
b068d6a7 | 494 | static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
9fddaa0c FB |
495 | { |
496 | ppc_tb_t *tb_env = env->tb_env; | |
a062e36c | 497 | uint64_t tb; |
9fddaa0c | 498 | |
a062e36c JM |
499 | tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset); |
500 | tb &= 0x00000000FFFFFFFFULL; | |
501 | cpu_ppc_store_tb(tb_env, &tb_env->tb_offset, | |
502 | ((uint64_t)value << 32) | tb); | |
9fddaa0c FB |
503 | } |
504 | ||
8a84de23 JM |
505 | void cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
506 | { | |
507 | _cpu_ppc_store_tbu(env, value); | |
508 | } | |
509 | ||
a062e36c JM |
510 | uint32_t cpu_ppc_load_atbl (CPUState *env) |
511 | { | |
512 | ppc_tb_t *tb_env = env->tb_env; | |
513 | uint64_t tb; | |
514 | ||
515 | tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset); | |
516 | #if defined(PPC_DEBUG_TB) | |
517 | if (loglevel != 0) { | |
518 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); | |
519 | } | |
520 | #endif | |
521 | ||
522 | return tb & 0xFFFFFFFF; | |
523 | } | |
524 | ||
525 | uint32_t cpu_ppc_load_atbu (CPUState *env) | |
526 | { | |
527 | ppc_tb_t *tb_env = env->tb_env; | |
528 | uint64_t tb; | |
529 | ||
530 | tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset); | |
531 | #if defined(PPC_DEBUG_TB) | |
532 | if (loglevel != 0) { | |
533 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); | |
534 | } | |
535 | #endif | |
536 | ||
537 | return tb >> 32; | |
538 | } | |
539 | ||
540 | void cpu_ppc_store_atbl (CPUState *env, uint32_t value) | |
541 | { | |
542 | ppc_tb_t *tb_env = env->tb_env; | |
543 | uint64_t tb; | |
544 | ||
545 | tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset); | |
546 | tb &= 0xFFFFFFFF00000000ULL; | |
547 | cpu_ppc_store_tb(tb_env, &tb_env->atb_offset, tb | (uint64_t)value); | |
548 | } | |
549 | ||
550 | void cpu_ppc_store_atbu (CPUState *env, uint32_t value) | |
9fddaa0c FB |
551 | { |
552 | ppc_tb_t *tb_env = env->tb_env; | |
a062e36c | 553 | uint64_t tb; |
9fddaa0c | 554 | |
a062e36c JM |
555 | tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset); |
556 | tb &= 0x00000000FFFFFFFFULL; | |
557 | cpu_ppc_store_tb(tb_env, &tb_env->atb_offset, | |
558 | ((uint64_t)value << 32) | tb); | |
9fddaa0c FB |
559 | } |
560 | ||
b068d6a7 JM |
561 | static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, |
562 | uint64_t *next) | |
9fddaa0c FB |
563 | { |
564 | ppc_tb_t *tb_env = env->tb_env; | |
565 | uint32_t decr; | |
4e588a4d | 566 | int64_t diff; |
9fddaa0c | 567 | |
4e588a4d FB |
568 | diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
569 | if (diff >= 0) | |
570 | decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec); | |
571 | else | |
572 | decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec); | |
4b6d0a4c JM |
573 | #if defined(PPC_DEBUG_TB) |
574 | if (loglevel != 0) { | |
a496775f JM |
575 | fprintf(logfile, "%s: 0x%08x\n", __func__, decr); |
576 | } | |
9fddaa0c | 577 | #endif |
76a66253 | 578 | |
9fddaa0c FB |
579 | return decr; |
580 | } | |
581 | ||
58a7d328 JM |
582 | uint32_t cpu_ppc_load_decr (CPUState *env) |
583 | { | |
584 | ppc_tb_t *tb_env = env->tb_env; | |
585 | ||
586 | return _cpu_ppc_load_decr(env, &tb_env->decr_next); | |
587 | } | |
588 | ||
589 | #if defined(TARGET_PPC64H) | |
590 | uint32_t cpu_ppc_load_hdecr (CPUState *env) | |
591 | { | |
592 | ppc_tb_t *tb_env = env->tb_env; | |
593 | ||
594 | return _cpu_ppc_load_decr(env, &tb_env->hdecr_next); | |
595 | } | |
596 | ||
597 | uint64_t cpu_ppc_load_purr (CPUState *env) | |
598 | { | |
599 | ppc_tb_t *tb_env = env->tb_env; | |
600 | uint64_t diff; | |
601 | ||
602 | diff = qemu_get_clock(vm_clock) - tb_env->purr_start; | |
603 | ||
604 | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec); | |
605 | } | |
606 | #endif /* defined(TARGET_PPC64H) */ | |
607 | ||
9fddaa0c FB |
608 | /* When decrementer expires, |
609 | * all we need to do is generate or queue a CPU exception | |
610 | */ | |
b068d6a7 | 611 | static always_inline void cpu_ppc_decr_excp (CPUState *env) |
9fddaa0c FB |
612 | { |
613 | /* Raise it */ | |
4b6d0a4c JM |
614 | #ifdef PPC_DEBUG_TB |
615 | if (loglevel != 0) { | |
a496775f JM |
616 | fprintf(logfile, "raise decrementer exception\n"); |
617 | } | |
9fddaa0c | 618 | #endif |
47103572 | 619 | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); |
9fddaa0c FB |
620 | } |
621 | ||
b068d6a7 | 622 | static always_inline void cpu_ppc_hdecr_excp (CPUState *env) |
58a7d328 JM |
623 | { |
624 | /* Raise it */ | |
625 | #ifdef PPC_DEBUG_TB | |
626 | if (loglevel != 0) { | |
627 | fprintf(logfile, "raise decrementer exception\n"); | |
628 | } | |
629 | #endif | |
630 | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); | |
631 | } | |
632 | ||
633 | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, | |
634 | struct QEMUTimer *timer, | |
635 | void (*raise_excp)(CPUState *), | |
636 | uint32_t decr, uint32_t value, | |
637 | int is_excp) | |
9fddaa0c FB |
638 | { |
639 | ppc_tb_t *tb_env = env->tb_env; | |
640 | uint64_t now, next; | |
641 | ||
4b6d0a4c JM |
642 | #ifdef PPC_DEBUG_TB |
643 | if (loglevel != 0) { | |
a496775f JM |
644 | fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value); |
645 | } | |
9fddaa0c FB |
646 | #endif |
647 | now = qemu_get_clock(vm_clock); | |
648 | next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq); | |
649 | if (is_excp) | |
58a7d328 | 650 | next += *nextp - now; |
9fddaa0c | 651 | if (next == now) |
76a66253 | 652 | next++; |
58a7d328 | 653 | *nextp = next; |
9fddaa0c | 654 | /* Adjust timer */ |
58a7d328 | 655 | qemu_mod_timer(timer, next); |
9fddaa0c FB |
656 | /* If we set a negative value and the decrementer was positive, |
657 | * raise an exception. | |
658 | */ | |
659 | if ((value & 0x80000000) && !(decr & 0x80000000)) | |
58a7d328 JM |
660 | (*raise_excp)(env); |
661 | } | |
662 | ||
b068d6a7 JM |
663 | static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
664 | uint32_t value, int is_excp) | |
58a7d328 JM |
665 | { |
666 | ppc_tb_t *tb_env = env->tb_env; | |
667 | ||
668 | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, | |
669 | &cpu_ppc_decr_excp, decr, value, is_excp); | |
9fddaa0c FB |
670 | } |
671 | ||
672 | void cpu_ppc_store_decr (CPUState *env, uint32_t value) | |
673 | { | |
674 | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0); | |
675 | } | |
676 | ||
677 | static void cpu_ppc_decr_cb (void *opaque) | |
678 | { | |
679 | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); | |
680 | } | |
681 | ||
58a7d328 | 682 | #if defined(TARGET_PPC64H) |
b068d6a7 JM |
683 | static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr, |
684 | uint32_t value, int is_excp) | |
58a7d328 JM |
685 | { |
686 | ppc_tb_t *tb_env = env->tb_env; | |
687 | ||
688 | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, | |
689 | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); | |
690 | } | |
691 | ||
692 | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value) | |
693 | { | |
694 | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0); | |
695 | } | |
696 | ||
697 | static void cpu_ppc_hdecr_cb (void *opaque) | |
698 | { | |
699 | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); | |
700 | } | |
701 | ||
702 | void cpu_ppc_store_purr (CPUState *env, uint64_t value) | |
703 | { | |
704 | ppc_tb_t *tb_env = env->tb_env; | |
705 | ||
706 | tb_env->purr_load = value; | |
707 | tb_env->purr_start = qemu_get_clock(vm_clock); | |
708 | } | |
709 | #endif /* defined(TARGET_PPC64H) */ | |
710 | ||
8ecc7913 JM |
711 | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
712 | { | |
713 | CPUState *env = opaque; | |
714 | ppc_tb_t *tb_env = env->tb_env; | |
715 | ||
716 | tb_env->tb_freq = freq; | |
717 | /* There is a bug in Linux 2.4 kernels: | |
718 | * if a decrementer exception is pending when it enables msr_ee at startup, | |
719 | * it's not ready to handle it... | |
720 | */ | |
721 | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); | |
58a7d328 JM |
722 | #if defined(TARGET_PPC64H) |
723 | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); | |
724 | cpu_ppc_store_purr(env, 0x0000000000000000ULL); | |
725 | #endif /* defined(TARGET_PPC64H) */ | |
8ecc7913 JM |
726 | } |
727 | ||
9fddaa0c | 728 | /* Set up (once) timebase frequency (in Hz) */ |
8ecc7913 | 729 | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
9fddaa0c FB |
730 | { |
731 | ppc_tb_t *tb_env; | |
732 | ||
733 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); | |
734 | if (tb_env == NULL) | |
735 | return NULL; | |
736 | env->tb_env = tb_env; | |
8ecc7913 JM |
737 | /* Create new timer */ |
738 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); | |
58a7d328 JM |
739 | #if defined(TARGET_PPC64H) |
740 | tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); | |
741 | #endif /* defined(TARGET_PPC64H) */ | |
8ecc7913 | 742 | cpu_ppc_set_tb_clk(env, freq); |
9fddaa0c | 743 | |
8ecc7913 | 744 | return &cpu_ppc_set_tb_clk; |
9fddaa0c FB |
745 | } |
746 | ||
76a66253 | 747 | /* Specific helpers for POWER & PowerPC 601 RTC */ |
8ecc7913 | 748 | clk_setup_cb cpu_ppc601_rtc_init (CPUState *env) |
76a66253 JM |
749 | { |
750 | return cpu_ppc_tb_init(env, 7812500); | |
751 | } | |
752 | ||
753 | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value) | |
8a84de23 JM |
754 | { |
755 | _cpu_ppc_store_tbu(env, value); | |
756 | } | |
76a66253 JM |
757 | |
758 | uint32_t cpu_ppc601_load_rtcu (CPUState *env) | |
8a84de23 JM |
759 | { |
760 | return _cpu_ppc_load_tbu(env); | |
761 | } | |
76a66253 JM |
762 | |
763 | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value) | |
764 | { | |
765 | cpu_ppc_store_tbl(env, value & 0x3FFFFF80); | |
766 | } | |
767 | ||
768 | uint32_t cpu_ppc601_load_rtcl (CPUState *env) | |
769 | { | |
770 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; | |
771 | } | |
772 | ||
636aaad7 | 773 | /*****************************************************************************/ |
76a66253 | 774 | /* Embedded PowerPC timers */ |
636aaad7 JM |
775 | |
776 | /* PIT, FIT & WDT */ | |
777 | typedef struct ppcemb_timer_t ppcemb_timer_t; | |
778 | struct ppcemb_timer_t { | |
779 | uint64_t pit_reload; /* PIT auto-reload value */ | |
780 | uint64_t fit_next; /* Tick for next FIT interrupt */ | |
781 | struct QEMUTimer *fit_timer; | |
782 | uint64_t wdt_next; /* Tick for next WDT interrupt */ | |
783 | struct QEMUTimer *wdt_timer; | |
784 | }; | |
3b46e624 | 785 | |
636aaad7 JM |
786 | /* Fixed interval timer */ |
787 | static void cpu_4xx_fit_cb (void *opaque) | |
788 | { | |
789 | CPUState *env; | |
790 | ppc_tb_t *tb_env; | |
791 | ppcemb_timer_t *ppcemb_timer; | |
792 | uint64_t now, next; | |
793 | ||
794 | env = opaque; | |
795 | tb_env = env->tb_env; | |
796 | ppcemb_timer = tb_env->opaque; | |
797 | now = qemu_get_clock(vm_clock); | |
798 | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { | |
799 | case 0: | |
800 | next = 1 << 9; | |
801 | break; | |
802 | case 1: | |
803 | next = 1 << 13; | |
804 | break; | |
805 | case 2: | |
806 | next = 1 << 17; | |
807 | break; | |
808 | case 3: | |
809 | next = 1 << 21; | |
810 | break; | |
811 | default: | |
812 | /* Cannot occur, but makes gcc happy */ | |
813 | return; | |
814 | } | |
815 | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); | |
816 | if (next == now) | |
817 | next++; | |
818 | qemu_mod_timer(ppcemb_timer->fit_timer, next); | |
636aaad7 JM |
819 | env->spr[SPR_40x_TSR] |= 1 << 26; |
820 | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) | |
821 | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1); | |
4b6d0a4c JM |
822 | #ifdef PPC_DEBUG_TB |
823 | if (loglevel != 0) { | |
e96efcfc JM |
824 | fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, |
825 | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), | |
636aaad7 JM |
826 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
827 | } | |
4b6d0a4c | 828 | #endif |
636aaad7 JM |
829 | } |
830 | ||
831 | /* Programmable interval timer */ | |
4b6d0a4c | 832 | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
76a66253 | 833 | { |
636aaad7 JM |
834 | ppcemb_timer_t *ppcemb_timer; |
835 | uint64_t now, next; | |
836 | ||
636aaad7 | 837 | ppcemb_timer = tb_env->opaque; |
4b6d0a4c JM |
838 | if (ppcemb_timer->pit_reload <= 1 || |
839 | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || | |
840 | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { | |
841 | /* Stop PIT */ | |
842 | #ifdef PPC_DEBUG_TB | |
843 | if (loglevel != 0) { | |
844 | fprintf(logfile, "%s: stop PIT\n", __func__); | |
845 | } | |
846 | #endif | |
847 | qemu_del_timer(tb_env->decr_timer); | |
848 | } else { | |
849 | #ifdef PPC_DEBUG_TB | |
850 | if (loglevel != 0) { | |
851 | fprintf(logfile, "%s: start PIT 0x" REGX "\n", | |
852 | __func__, ppcemb_timer->pit_reload); | |
853 | } | |
854 | #endif | |
855 | now = qemu_get_clock(vm_clock); | |
636aaad7 JM |
856 | next = now + muldiv64(ppcemb_timer->pit_reload, |
857 | ticks_per_sec, tb_env->tb_freq); | |
4b6d0a4c JM |
858 | if (is_excp) |
859 | next += tb_env->decr_next - now; | |
636aaad7 JM |
860 | if (next == now) |
861 | next++; | |
862 | qemu_mod_timer(tb_env->decr_timer, next); | |
863 | tb_env->decr_next = next; | |
864 | } | |
4b6d0a4c JM |
865 | } |
866 | ||
867 | static void cpu_4xx_pit_cb (void *opaque) | |
868 | { | |
869 | CPUState *env; | |
870 | ppc_tb_t *tb_env; | |
871 | ppcemb_timer_t *ppcemb_timer; | |
872 | ||
873 | env = opaque; | |
874 | tb_env = env->tb_env; | |
875 | ppcemb_timer = tb_env->opaque; | |
636aaad7 JM |
876 | env->spr[SPR_40x_TSR] |= 1 << 27; |
877 | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) | |
878 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1); | |
4b6d0a4c JM |
879 | start_stop_pit(env, tb_env, 1); |
880 | #ifdef PPC_DEBUG_TB | |
881 | if (loglevel != 0) { | |
e96efcfc JM |
882 | fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " |
883 | "%016" PRIx64 "\n", __func__, | |
884 | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), | |
885 | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), | |
636aaad7 JM |
886 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
887 | ppcemb_timer->pit_reload); | |
888 | } | |
4b6d0a4c | 889 | #endif |
636aaad7 JM |
890 | } |
891 | ||
892 | /* Watchdog timer */ | |
893 | static void cpu_4xx_wdt_cb (void *opaque) | |
894 | { | |
895 | CPUState *env; | |
896 | ppc_tb_t *tb_env; | |
897 | ppcemb_timer_t *ppcemb_timer; | |
898 | uint64_t now, next; | |
899 | ||
900 | env = opaque; | |
901 | tb_env = env->tb_env; | |
902 | ppcemb_timer = tb_env->opaque; | |
903 | now = qemu_get_clock(vm_clock); | |
904 | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { | |
905 | case 0: | |
906 | next = 1 << 17; | |
907 | break; | |
908 | case 1: | |
909 | next = 1 << 21; | |
910 | break; | |
911 | case 2: | |
912 | next = 1 << 25; | |
913 | break; | |
914 | case 3: | |
915 | next = 1 << 29; | |
916 | break; | |
917 | default: | |
918 | /* Cannot occur, but makes gcc happy */ | |
919 | return; | |
920 | } | |
921 | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); | |
922 | if (next == now) | |
923 | next++; | |
4b6d0a4c JM |
924 | #ifdef PPC_DEBUG_TB |
925 | if (loglevel != 0) { | |
e96efcfc | 926 | fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, |
636aaad7 JM |
927 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
928 | } | |
4b6d0a4c | 929 | #endif |
636aaad7 JM |
930 | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
931 | case 0x0: | |
932 | case 0x1: | |
933 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); | |
934 | ppcemb_timer->wdt_next = next; | |
935 | env->spr[SPR_40x_TSR] |= 1 << 31; | |
936 | break; | |
937 | case 0x2: | |
938 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); | |
939 | ppcemb_timer->wdt_next = next; | |
940 | env->spr[SPR_40x_TSR] |= 1 << 30; | |
941 | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) | |
942 | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1); | |
943 | break; | |
944 | case 0x3: | |
945 | env->spr[SPR_40x_TSR] &= ~0x30000000; | |
946 | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; | |
947 | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { | |
948 | case 0x0: | |
949 | /* No reset */ | |
950 | break; | |
951 | case 0x1: /* Core reset */ | |
8ecc7913 JM |
952 | ppc40x_core_reset(env); |
953 | break; | |
636aaad7 | 954 | case 0x2: /* Chip reset */ |
8ecc7913 JM |
955 | ppc40x_chip_reset(env); |
956 | break; | |
636aaad7 | 957 | case 0x3: /* System reset */ |
8ecc7913 JM |
958 | ppc40x_system_reset(env); |
959 | break; | |
636aaad7 JM |
960 | } |
961 | } | |
76a66253 JM |
962 | } |
963 | ||
964 | void store_40x_pit (CPUState *env, target_ulong val) | |
965 | { | |
636aaad7 JM |
966 | ppc_tb_t *tb_env; |
967 | ppcemb_timer_t *ppcemb_timer; | |
636aaad7 JM |
968 | |
969 | tb_env = env->tb_env; | |
970 | ppcemb_timer = tb_env->opaque; | |
4b6d0a4c JM |
971 | #ifdef PPC_DEBUG_TB |
972 | if (loglevel != 0) { | |
636aaad7 | 973 | fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer); |
a496775f | 974 | } |
4b6d0a4c | 975 | #endif |
636aaad7 | 976 | ppcemb_timer->pit_reload = val; |
4b6d0a4c | 977 | start_stop_pit(env, tb_env, 0); |
76a66253 JM |
978 | } |
979 | ||
636aaad7 | 980 | target_ulong load_40x_pit (CPUState *env) |
76a66253 | 981 | { |
636aaad7 | 982 | return cpu_ppc_load_decr(env); |
76a66253 JM |
983 | } |
984 | ||
985 | void store_booke_tsr (CPUState *env, target_ulong val) | |
986 | { | |
4b6d0a4c JM |
987 | #ifdef PPC_DEBUG_TB |
988 | if (loglevel != 0) { | |
989 | fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val); | |
990 | } | |
991 | #endif | |
992 | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); | |
993 | if (val & 0x80000000) | |
994 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 0); | |
636aaad7 JM |
995 | } |
996 | ||
997 | void store_booke_tcr (CPUState *env, target_ulong val) | |
998 | { | |
4b6d0a4c JM |
999 | ppc_tb_t *tb_env; |
1000 | ||
1001 | tb_env = env->tb_env; | |
1002 | #ifdef PPC_DEBUG_TB | |
1003 | if (loglevel != 0) { | |
1004 | fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val); | |
1005 | } | |
1006 | #endif | |
1007 | env->spr[SPR_40x_TCR] = val & 0xFFC00000; | |
1008 | start_stop_pit(env, tb_env, 1); | |
8ecc7913 | 1009 | cpu_4xx_wdt_cb(env); |
636aaad7 JM |
1010 | } |
1011 | ||
4b6d0a4c JM |
1012 | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
1013 | { | |
1014 | CPUState *env = opaque; | |
1015 | ppc_tb_t *tb_env = env->tb_env; | |
1016 | ||
1017 | #ifdef PPC_DEBUG_TB | |
1018 | if (loglevel != 0) { | |
1019 | fprintf(logfile, "%s set new frequency to %u\n", __func__, freq); | |
1020 | } | |
1021 | #endif | |
1022 | tb_env->tb_freq = freq; | |
1023 | /* XXX: we should also update all timers */ | |
1024 | } | |
1025 | ||
8ecc7913 | 1026 | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) |
636aaad7 JM |
1027 | { |
1028 | ppc_tb_t *tb_env; | |
1029 | ppcemb_timer_t *ppcemb_timer; | |
1030 | ||
8ecc7913 | 1031 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); |
4b6d0a4c | 1032 | if (tb_env == NULL) { |
8ecc7913 | 1033 | return NULL; |
4b6d0a4c | 1034 | } |
8ecc7913 | 1035 | env->tb_env = tb_env; |
636aaad7 | 1036 | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t)); |
8ecc7913 | 1037 | tb_env->tb_freq = freq; |
636aaad7 | 1038 | tb_env->opaque = ppcemb_timer; |
4b6d0a4c JM |
1039 | #ifdef PPC_DEBUG_TB |
1040 | if (loglevel != 0) { | |
1041 | fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer, | |
1042 | &ppc_emb_set_tb_clk); | |
8ecc7913 | 1043 | } |
4b6d0a4c | 1044 | #endif |
636aaad7 JM |
1045 | if (ppcemb_timer != NULL) { |
1046 | /* We use decr timer for PIT */ | |
1047 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); | |
1048 | ppcemb_timer->fit_timer = | |
1049 | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); | |
1050 | ppcemb_timer->wdt_timer = | |
1051 | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); | |
1052 | } | |
8ecc7913 | 1053 | |
4b6d0a4c | 1054 | return &ppc_emb_set_tb_clk; |
76a66253 JM |
1055 | } |
1056 | ||
2e719ba3 JM |
1057 | /*****************************************************************************/ |
1058 | /* Embedded PowerPC Device Control Registers */ | |
1059 | typedef struct ppc_dcrn_t ppc_dcrn_t; | |
1060 | struct ppc_dcrn_t { | |
1061 | dcr_read_cb dcr_read; | |
1062 | dcr_write_cb dcr_write; | |
1063 | void *opaque; | |
1064 | }; | |
1065 | ||
a750fc0b JM |
1066 | /* XXX: on 460, DCR addresses are 32 bits wide, |
1067 | * using DCRIPR to get the 22 upper bits of the DCR address | |
1068 | */ | |
2e719ba3 JM |
1069 | #define DCRN_NB 1024 |
1070 | struct ppc_dcr_t { | |
1071 | ppc_dcrn_t dcrn[DCRN_NB]; | |
1072 | int (*read_error)(int dcrn); | |
1073 | int (*write_error)(int dcrn); | |
1074 | }; | |
1075 | ||
1076 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) | |
1077 | { | |
1078 | ppc_dcrn_t *dcr; | |
1079 | ||
1080 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1081 | goto error; | |
1082 | dcr = &dcr_env->dcrn[dcrn]; | |
1083 | if (dcr->dcr_read == NULL) | |
1084 | goto error; | |
1085 | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); | |
1086 | ||
1087 | return 0; | |
1088 | ||
1089 | error: | |
1090 | if (dcr_env->read_error != NULL) | |
1091 | return (*dcr_env->read_error)(dcrn); | |
1092 | ||
1093 | return -1; | |
1094 | } | |
1095 | ||
1096 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) | |
1097 | { | |
1098 | ppc_dcrn_t *dcr; | |
1099 | ||
1100 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1101 | goto error; | |
1102 | dcr = &dcr_env->dcrn[dcrn]; | |
1103 | if (dcr->dcr_write == NULL) | |
1104 | goto error; | |
1105 | (*dcr->dcr_write)(dcr->opaque, dcrn, val); | |
1106 | ||
1107 | return 0; | |
1108 | ||
1109 | error: | |
1110 | if (dcr_env->write_error != NULL) | |
1111 | return (*dcr_env->write_error)(dcrn); | |
1112 | ||
1113 | return -1; | |
1114 | } | |
1115 | ||
1116 | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, | |
1117 | dcr_read_cb dcr_read, dcr_write_cb dcr_write) | |
1118 | { | |
1119 | ppc_dcr_t *dcr_env; | |
1120 | ppc_dcrn_t *dcr; | |
1121 | ||
1122 | dcr_env = env->dcr_env; | |
1123 | if (dcr_env == NULL) | |
1124 | return -1; | |
1125 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1126 | return -1; | |
1127 | dcr = &dcr_env->dcrn[dcrn]; | |
1128 | if (dcr->opaque != NULL || | |
1129 | dcr->dcr_read != NULL || | |
1130 | dcr->dcr_write != NULL) | |
1131 | return -1; | |
1132 | dcr->opaque = opaque; | |
1133 | dcr->dcr_read = dcr_read; | |
1134 | dcr->dcr_write = dcr_write; | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), | |
1140 | int (*write_error)(int dcrn)) | |
1141 | { | |
1142 | ppc_dcr_t *dcr_env; | |
1143 | ||
1144 | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t)); | |
1145 | if (dcr_env == NULL) | |
1146 | return -1; | |
1147 | dcr_env->read_error = read_error; | |
1148 | dcr_env->write_error = write_error; | |
1149 | env->dcr_env = dcr_env; | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | ||
9fddaa0c FB |
1155 | #if 0 |
1156 | /*****************************************************************************/ | |
1157 | /* Handle system reset (for now, just stop emulation) */ | |
1158 | void cpu_ppc_reset (CPUState *env) | |
1159 | { | |
1160 | printf("Reset asked... Stop emulation\n"); | |
1161 | abort(); | |
1162 | } | |
1163 | #endif | |
1164 | ||
64201201 FB |
1165 | /*****************************************************************************/ |
1166 | /* Debug port */ | |
fd0bbb12 | 1167 | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
64201201 FB |
1168 | { |
1169 | addr &= 0xF; | |
1170 | switch (addr) { | |
1171 | case 0: | |
1172 | printf("%c", val); | |
1173 | break; | |
1174 | case 1: | |
1175 | printf("\n"); | |
1176 | fflush(stdout); | |
1177 | break; | |
1178 | case 2: | |
1179 | printf("Set loglevel to %04x\n", val); | |
fd0bbb12 | 1180 | cpu_set_log(val | 0x100); |
64201201 FB |
1181 | break; |
1182 | } | |
1183 | } | |
1184 | ||
1185 | /*****************************************************************************/ | |
1186 | /* NVRAM helpers */ | |
1187 | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value) | |
1188 | { | |
819385c5 | 1189 | m48t59_write(nvram, addr, value); |
64201201 FB |
1190 | } |
1191 | ||
1192 | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) | |
1193 | { | |
819385c5 | 1194 | return m48t59_read(nvram, addr); |
64201201 FB |
1195 | } |
1196 | ||
1197 | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) | |
1198 | { | |
819385c5 FB |
1199 | m48t59_write(nvram, addr, value >> 8); |
1200 | m48t59_write(nvram, addr + 1, value & 0xFF); | |
64201201 FB |
1201 | } |
1202 | ||
1203 | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) | |
1204 | { | |
1205 | uint16_t tmp; | |
1206 | ||
819385c5 FB |
1207 | tmp = m48t59_read(nvram, addr) << 8; |
1208 | tmp |= m48t59_read(nvram, addr + 1); | |
64201201 FB |
1209 | return tmp; |
1210 | } | |
1211 | ||
1212 | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) | |
1213 | { | |
819385c5 FB |
1214 | m48t59_write(nvram, addr, value >> 24); |
1215 | m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); | |
1216 | m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); | |
1217 | m48t59_write(nvram, addr + 3, value & 0xFF); | |
64201201 FB |
1218 | } |
1219 | ||
1220 | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) | |
1221 | { | |
1222 | uint32_t tmp; | |
1223 | ||
819385c5 FB |
1224 | tmp = m48t59_read(nvram, addr) << 24; |
1225 | tmp |= m48t59_read(nvram, addr + 1) << 16; | |
1226 | tmp |= m48t59_read(nvram, addr + 2) << 8; | |
1227 | tmp |= m48t59_read(nvram, addr + 3); | |
76a66253 | 1228 | |
64201201 FB |
1229 | return tmp; |
1230 | } | |
1231 | ||
1232 | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr, | |
1233 | const unsigned char *str, uint32_t max) | |
1234 | { | |
1235 | int i; | |
1236 | ||
1237 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
819385c5 | 1238 | m48t59_write(nvram, addr + i, str[i]); |
64201201 | 1239 | } |
819385c5 | 1240 | m48t59_write(nvram, addr + max - 1, '\0'); |
64201201 FB |
1241 | } |
1242 | ||
1243 | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) | |
1244 | { | |
1245 | int i; | |
1246 | ||
1247 | memset(dst, 0, max); | |
1248 | for (i = 0; i < max; i++) { | |
1249 | dst[i] = NVRAM_get_byte(nvram, addr + i); | |
1250 | if (dst[i] == '\0') | |
1251 | break; | |
1252 | } | |
1253 | ||
1254 | return i; | |
1255 | } | |
1256 | ||
1257 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) | |
1258 | { | |
1259 | uint16_t tmp; | |
1260 | uint16_t pd, pd1, pd2; | |
1261 | ||
1262 | tmp = prev >> 8; | |
1263 | pd = prev ^ value; | |
1264 | pd1 = pd & 0x000F; | |
1265 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; | |
1266 | tmp ^= (pd1 << 3) | (pd1 << 8); | |
1267 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); | |
1268 | ||
1269 | return tmp; | |
1270 | } | |
1271 | ||
1272 | uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) | |
1273 | { | |
1274 | uint32_t i; | |
1275 | uint16_t crc = 0xFFFF; | |
1276 | int odd; | |
1277 | ||
1278 | odd = count & 1; | |
1279 | count &= ~1; | |
1280 | for (i = 0; i != count; i++) { | |
76a66253 | 1281 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
64201201 FB |
1282 | } |
1283 | if (odd) { | |
76a66253 | 1284 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); |
64201201 FB |
1285 | } |
1286 | ||
1287 | return crc; | |
1288 | } | |
1289 | ||
fd0bbb12 FB |
1290 | #define CMDLINE_ADDR 0x017ff000 |
1291 | ||
64201201 FB |
1292 | int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
1293 | const unsigned char *arch, | |
1294 | uint32_t RAM_size, int boot_device, | |
1295 | uint32_t kernel_image, uint32_t kernel_size, | |
fd0bbb12 | 1296 | const char *cmdline, |
64201201 | 1297 | uint32_t initrd_image, uint32_t initrd_size, |
fd0bbb12 FB |
1298 | uint32_t NVRAM_image, |
1299 | int width, int height, int depth) | |
64201201 FB |
1300 | { |
1301 | uint16_t crc; | |
1302 | ||
1303 | /* Set parameters for Open Hack'Ware BIOS */ | |
1304 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
1305 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ | |
1306 | NVRAM_set_word(nvram, 0x14, NVRAM_size); | |
1307 | NVRAM_set_string(nvram, 0x20, arch, 16); | |
1308 | NVRAM_set_lword(nvram, 0x30, RAM_size); | |
1309 | NVRAM_set_byte(nvram, 0x34, boot_device); | |
1310 | NVRAM_set_lword(nvram, 0x38, kernel_image); | |
1311 | NVRAM_set_lword(nvram, 0x3C, kernel_size); | |
fd0bbb12 FB |
1312 | if (cmdline) { |
1313 | /* XXX: put the cmdline in NVRAM too ? */ | |
1314 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); | |
1315 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
1316 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); | |
1317 | } else { | |
1318 | NVRAM_set_lword(nvram, 0x40, 0); | |
1319 | NVRAM_set_lword(nvram, 0x44, 0); | |
1320 | } | |
64201201 FB |
1321 | NVRAM_set_lword(nvram, 0x48, initrd_image); |
1322 | NVRAM_set_lword(nvram, 0x4C, initrd_size); | |
1323 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); | |
fd0bbb12 FB |
1324 | |
1325 | NVRAM_set_word(nvram, 0x54, width); | |
1326 | NVRAM_set_word(nvram, 0x56, height); | |
1327 | NVRAM_set_word(nvram, 0x58, depth); | |
1328 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); | |
1329 | NVRAM_set_word(nvram, 0xFC, crc); | |
64201201 FB |
1330 | |
1331 | return 0; | |
a541f297 | 1332 | } |