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1a6c0886 JM |
1 | /* |
2 | * QEMU PowerPC 405 evaluation boards emulation | |
5fafdf24 | 3 | * |
1a6c0886 | 4 | * Copyright (c) 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
1a6c0886 JM |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "ppc.h" | |
1a6c0886 | 26 | #include "ppc405.h" |
87ecb68b PB |
27 | #include "nvram.h" |
28 | #include "flash.h" | |
29 | #include "sysemu.h" | |
30 | #include "block.h" | |
31 | #include "boards.h" | |
3b3fb322 | 32 | #include "qemu-log.h" |
1a6c0886 JM |
33 | |
34 | #define BIOS_FILENAME "ppc405_rom.bin" | |
35 | #undef BIOS_SIZE | |
36 | #define BIOS_SIZE (2048 * 1024) | |
37 | ||
38 | #define KERNEL_LOAD_ADDR 0x00000000 | |
39 | #define INITRD_LOAD_ADDR 0x01800000 | |
40 | ||
41 | #define USE_FLASH_BIOS | |
42 | ||
43 | #define DEBUG_BOARD_INIT | |
44 | ||
45 | /*****************************************************************************/ | |
46 | /* PPC405EP reference board (IBM) */ | |
47 | /* Standalone board with: | |
48 | * - PowerPC 405EP CPU | |
49 | * - SDRAM (0x00000000) | |
50 | * - Flash (0xFFF80000) | |
51 | * - SRAM (0xFFF00000) | |
52 | * - NVRAM (0xF0000000) | |
53 | * - FPGA (0xF0300000) | |
54 | */ | |
55 | typedef struct ref405ep_fpga_t ref405ep_fpga_t; | |
56 | struct ref405ep_fpga_t { | |
57 | uint32_t base; | |
58 | uint8_t reg0; | |
59 | uint8_t reg1; | |
60 | }; | |
61 | ||
62 | static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr) | |
63 | { | |
64 | ref405ep_fpga_t *fpga; | |
65 | uint32_t ret; | |
66 | ||
67 | fpga = opaque; | |
68 | addr -= fpga->base; | |
69 | switch (addr) { | |
70 | case 0x0: | |
71 | ret = fpga->reg0; | |
72 | break; | |
73 | case 0x1: | |
74 | ret = fpga->reg1; | |
75 | break; | |
76 | default: | |
77 | ret = 0; | |
78 | break; | |
79 | } | |
80 | ||
81 | return ret; | |
82 | } | |
83 | ||
84 | static void ref405ep_fpga_writeb (void *opaque, | |
85 | target_phys_addr_t addr, uint32_t value) | |
86 | { | |
87 | ref405ep_fpga_t *fpga; | |
88 | ||
89 | fpga = opaque; | |
90 | addr -= fpga->base; | |
91 | switch (addr) { | |
92 | case 0x0: | |
93 | /* Read only */ | |
94 | break; | |
95 | case 0x1: | |
96 | fpga->reg1 = value; | |
97 | break; | |
98 | default: | |
99 | break; | |
100 | } | |
101 | } | |
102 | ||
103 | static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr) | |
104 | { | |
105 | uint32_t ret; | |
106 | ||
107 | ret = ref405ep_fpga_readb(opaque, addr) << 8; | |
108 | ret |= ref405ep_fpga_readb(opaque, addr + 1); | |
109 | ||
110 | return ret; | |
111 | } | |
112 | ||
113 | static void ref405ep_fpga_writew (void *opaque, | |
114 | target_phys_addr_t addr, uint32_t value) | |
115 | { | |
116 | ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); | |
117 | ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); | |
118 | } | |
119 | ||
120 | static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr) | |
121 | { | |
122 | uint32_t ret; | |
123 | ||
124 | ret = ref405ep_fpga_readb(opaque, addr) << 24; | |
125 | ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; | |
126 | ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; | |
127 | ret |= ref405ep_fpga_readb(opaque, addr + 3); | |
128 | ||
129 | return ret; | |
130 | } | |
131 | ||
132 | static void ref405ep_fpga_writel (void *opaque, | |
133 | target_phys_addr_t addr, uint32_t value) | |
134 | { | |
135 | ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF); | |
136 | ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF); | |
137 | ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF); | |
138 | ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); | |
139 | } | |
140 | ||
141 | static CPUReadMemoryFunc *ref405ep_fpga_read[] = { | |
142 | &ref405ep_fpga_readb, | |
143 | &ref405ep_fpga_readw, | |
144 | &ref405ep_fpga_readl, | |
145 | }; | |
146 | ||
147 | static CPUWriteMemoryFunc *ref405ep_fpga_write[] = { | |
148 | &ref405ep_fpga_writeb, | |
149 | &ref405ep_fpga_writew, | |
150 | &ref405ep_fpga_writel, | |
151 | }; | |
152 | ||
153 | static void ref405ep_fpga_reset (void *opaque) | |
154 | { | |
155 | ref405ep_fpga_t *fpga; | |
156 | ||
157 | fpga = opaque; | |
158 | fpga->reg0 = 0x00; | |
159 | fpga->reg1 = 0x0F; | |
160 | } | |
161 | ||
162 | static void ref405ep_fpga_init (uint32_t base) | |
163 | { | |
164 | ref405ep_fpga_t *fpga; | |
165 | int fpga_memory; | |
166 | ||
167 | fpga = qemu_mallocz(sizeof(ref405ep_fpga_t)); | |
168 | if (fpga != NULL) { | |
169 | fpga->base = base; | |
170 | fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read, | |
171 | ref405ep_fpga_write, fpga); | |
172 | cpu_register_physical_memory(base, 0x00000100, fpga_memory); | |
173 | ref405ep_fpga_reset(fpga); | |
174 | qemu_register_reset(&ref405ep_fpga_reset, fpga); | |
175 | } | |
176 | } | |
177 | ||
00f82b8a | 178 | static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
6ac0e82d | 179 | const char *boot_device, DisplayState *ds, |
5fafdf24 | 180 | const char *kernel_filename, |
1a6c0886 JM |
181 | const char *kernel_cmdline, |
182 | const char *initrd_filename, | |
183 | const char *cpu_model) | |
184 | { | |
185 | char buf[1024]; | |
186 | ppc4xx_bd_info_t bd; | |
187 | CPUPPCState *env; | |
188 | qemu_irq *pic; | |
189 | ram_addr_t sram_offset, bios_offset, bdloc; | |
71db710f | 190 | target_phys_addr_t ram_bases[2], ram_sizes[2]; |
1a6c0886 JM |
191 | target_ulong sram_size, bios_size; |
192 | //int phy_addr = 0; | |
193 | //static int phy_addr = 1; | |
194 | target_ulong kernel_base, kernel_size, initrd_base, initrd_size; | |
195 | int linux_boot; | |
196 | int fl_idx, fl_sectors, len; | |
6ac0e82d | 197 | int ppc_boot_device = boot_device[0]; |
e4bcb14c | 198 | int index; |
1a6c0886 JM |
199 | |
200 | /* XXX: fix this */ | |
201 | ram_bases[0] = 0x00000000; | |
202 | ram_sizes[0] = 0x08000000; | |
203 | ram_bases[1] = 0x00000000; | |
204 | ram_sizes[1] = 0x00000000; | |
205 | ram_size = 128 * 1024 * 1024; | |
206 | #ifdef DEBUG_BOARD_INIT | |
207 | printf("%s: register cpu\n", __func__); | |
208 | #endif | |
209 | env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset, | |
210 | kernel_filename == NULL ? 0 : 1); | |
211 | /* allocate SRAM */ | |
212 | #ifdef DEBUG_BOARD_INIT | |
213 | printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset); | |
214 | #endif | |
215 | sram_size = 512 * 1024; | |
216 | cpu_register_physical_memory(0xFFF00000, sram_size, | |
217 | sram_offset | IO_MEM_RAM); | |
218 | /* allocate and load BIOS */ | |
219 | #ifdef DEBUG_BOARD_INIT | |
220 | printf("%s: register BIOS\n", __func__); | |
221 | #endif | |
222 | bios_offset = sram_offset + sram_size; | |
223 | fl_idx = 0; | |
224 | #ifdef USE_FLASH_BIOS | |
e4bcb14c TS |
225 | index = drive_get_index(IF_PFLASH, 0, fl_idx); |
226 | if (index != -1) { | |
227 | bios_size = bdrv_getlength(drives_table[index].bdrv); | |
1a6c0886 JM |
228 | fl_sectors = (bios_size + 65535) >> 16; |
229 | #ifdef DEBUG_BOARD_INIT | |
230 | printf("Register parallel flash %d size " ADDRX " at offset %08lx " | |
231 | " addr " ADDRX " '%s' %d\n", | |
232 | fl_idx, bios_size, bios_offset, -bios_size, | |
e4bcb14c | 233 | bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); |
1a6c0886 | 234 | #endif |
88eeee0a | 235 | pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
4fbd24ba AZ |
236 | drives_table[index].bdrv, 65536, fl_sectors, 1, |
237 | 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); | |
1a6c0886 JM |
238 | fl_idx++; |
239 | } else | |
240 | #endif | |
241 | { | |
242 | #ifdef DEBUG_BOARD_INIT | |
243 | printf("Load BIOS from file\n"); | |
244 | #endif | |
1192dad8 JM |
245 | if (bios_name == NULL) |
246 | bios_name = BIOS_FILENAME; | |
247 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
1a6c0886 JM |
248 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
249 | if (bios_size < 0 || bios_size > BIOS_SIZE) { | |
250 | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf); | |
251 | exit(1); | |
252 | } | |
253 | bios_size = (bios_size + 0xfff) & ~0xfff; | |
5fafdf24 | 254 | cpu_register_physical_memory((uint32_t)(-bios_size), |
1a6c0886 JM |
255 | bios_size, bios_offset | IO_MEM_ROM); |
256 | } | |
257 | bios_offset += bios_size; | |
258 | /* Register FPGA */ | |
259 | #ifdef DEBUG_BOARD_INIT | |
260 | printf("%s: register FPGA\n", __func__); | |
261 | #endif | |
262 | ref405ep_fpga_init(0xF0300000); | |
263 | /* Register NVRAM */ | |
264 | #ifdef DEBUG_BOARD_INIT | |
265 | printf("%s: register NVRAM\n", __func__); | |
266 | #endif | |
267 | m48t59_init(NULL, 0xF0000000, 0, 8192, 8); | |
268 | /* Load kernel */ | |
269 | linux_boot = (kernel_filename != NULL); | |
270 | if (linux_boot) { | |
271 | #ifdef DEBUG_BOARD_INIT | |
272 | printf("%s: load kernel\n", __func__); | |
273 | #endif | |
274 | memset(&bd, 0, sizeof(bd)); | |
275 | bd.bi_memstart = 0x00000000; | |
276 | bd.bi_memsize = ram_size; | |
217fae2d | 277 | bd.bi_flashstart = -bios_size; |
1a6c0886 JM |
278 | bd.bi_flashsize = -bios_size; |
279 | bd.bi_flashoffset = 0; | |
280 | bd.bi_sramstart = 0xFFF00000; | |
281 | bd.bi_sramsize = sram_size; | |
282 | bd.bi_bootflags = 0; | |
283 | bd.bi_intfreq = 133333333; | |
284 | bd.bi_busfreq = 33333333; | |
285 | bd.bi_baudrate = 115200; | |
286 | bd.bi_s_version[0] = 'Q'; | |
287 | bd.bi_s_version[1] = 'M'; | |
288 | bd.bi_s_version[2] = 'U'; | |
289 | bd.bi_s_version[3] = '\0'; | |
290 | bd.bi_r_version[0] = 'Q'; | |
291 | bd.bi_r_version[1] = 'E'; | |
292 | bd.bi_r_version[2] = 'M'; | |
293 | bd.bi_r_version[3] = 'U'; | |
294 | bd.bi_r_version[4] = '\0'; | |
295 | bd.bi_procfreq = 133333333; | |
296 | bd.bi_plb_busfreq = 33333333; | |
297 | bd.bi_pci_busfreq = 33333333; | |
298 | bd.bi_opbfreq = 33333333; | |
b8d3f5d1 | 299 | bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); |
1a6c0886 JM |
300 | env->gpr[3] = bdloc; |
301 | kernel_base = KERNEL_LOAD_ADDR; | |
302 | /* now we can load the kernel */ | |
303 | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); | |
304 | if (kernel_size < 0) { | |
5fafdf24 | 305 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
1a6c0886 JM |
306 | kernel_filename); |
307 | exit(1); | |
308 | } | |
309 | printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx | |
310 | " %02x %02x %02x %02x\n", kernel_size, kernel_base, | |
311 | *(char *)(phys_ram_base + kernel_base), | |
312 | *(char *)(phys_ram_base + kernel_base + 1), | |
313 | *(char *)(phys_ram_base + kernel_base + 2), | |
314 | *(char *)(phys_ram_base + kernel_base + 3)); | |
315 | /* load initrd */ | |
316 | if (initrd_filename) { | |
317 | initrd_base = INITRD_LOAD_ADDR; | |
318 | initrd_size = load_image(initrd_filename, | |
319 | phys_ram_base + initrd_base); | |
320 | if (initrd_size < 0) { | |
5fafdf24 | 321 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
1a6c0886 JM |
322 | initrd_filename); |
323 | exit(1); | |
324 | } | |
325 | } else { | |
326 | initrd_base = 0; | |
327 | initrd_size = 0; | |
328 | } | |
329 | env->gpr[4] = initrd_base; | |
330 | env->gpr[5] = initrd_size; | |
6ac0e82d | 331 | ppc_boot_device = 'm'; |
1a6c0886 JM |
332 | if (kernel_cmdline != NULL) { |
333 | len = strlen(kernel_cmdline); | |
334 | bdloc -= ((len + 255) & ~255); | |
335 | memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1); | |
336 | env->gpr[6] = bdloc; | |
337 | env->gpr[7] = bdloc + len; | |
338 | } else { | |
339 | env->gpr[6] = 0; | |
340 | env->gpr[7] = 0; | |
341 | } | |
342 | env->nip = KERNEL_LOAD_ADDR; | |
343 | } else { | |
344 | kernel_base = 0; | |
345 | kernel_size = 0; | |
346 | initrd_base = 0; | |
347 | initrd_size = 0; | |
348 | bdloc = 0; | |
349 | } | |
350 | #ifdef DEBUG_BOARD_INIT | |
351 | printf("%s: Done\n", __func__); | |
352 | #endif | |
353 | printf("bdloc %016lx %s\n", | |
354 | (unsigned long)bdloc, (char *)(phys_ram_base + bdloc)); | |
355 | } | |
356 | ||
357 | QEMUMachine ref405ep_machine = { | |
4b32e168 AL |
358 | .name = "ref405ep", |
359 | .desc = "ref405ep", | |
360 | .init = ref405ep_init, | |
361 | .ram_require = (128 * 1024 * 1024 + 4096 + 512 * 1024 + BIOS_SIZE) | RAMSIZE_FIXED, | |
1a6c0886 JM |
362 | }; |
363 | ||
364 | /*****************************************************************************/ | |
365 | /* AMCC Taihu evaluation board */ | |
366 | /* - PowerPC 405EP processor | |
367 | * - SDRAM 128 MB at 0x00000000 | |
368 | * - Boot flash 2 MB at 0xFFE00000 | |
369 | * - Application flash 32 MB at 0xFC000000 | |
370 | * - 2 serial ports | |
371 | * - 2 ethernet PHY | |
372 | * - 1 USB 1.1 device 0x50000000 | |
373 | * - 1 LCD display 0x50100000 | |
374 | * - 1 CPLD 0x50100000 | |
375 | * - 1 I2C EEPROM | |
376 | * - 1 I2C thermal sensor | |
377 | * - a set of LEDs | |
378 | * - bit-bang SPI port using GPIOs | |
379 | * - 1 EBC interface connector 0 0x50200000 | |
380 | * - 1 cardbus controller + expansion slot. | |
381 | * - 1 PCI expansion slot. | |
382 | */ | |
383 | typedef struct taihu_cpld_t taihu_cpld_t; | |
384 | struct taihu_cpld_t { | |
385 | uint32_t base; | |
386 | uint8_t reg0; | |
387 | uint8_t reg1; | |
388 | }; | |
389 | ||
390 | static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr) | |
391 | { | |
392 | taihu_cpld_t *cpld; | |
393 | uint32_t ret; | |
394 | ||
395 | cpld = opaque; | |
396 | addr -= cpld->base; | |
397 | switch (addr) { | |
398 | case 0x0: | |
399 | ret = cpld->reg0; | |
400 | break; | |
401 | case 0x1: | |
402 | ret = cpld->reg1; | |
403 | break; | |
404 | default: | |
405 | ret = 0; | |
406 | break; | |
407 | } | |
408 | ||
409 | return ret; | |
410 | } | |
411 | ||
412 | static void taihu_cpld_writeb (void *opaque, | |
413 | target_phys_addr_t addr, uint32_t value) | |
414 | { | |
415 | taihu_cpld_t *cpld; | |
416 | ||
417 | cpld = opaque; | |
418 | addr -= cpld->base; | |
419 | switch (addr) { | |
420 | case 0x0: | |
421 | /* Read only */ | |
422 | break; | |
423 | case 0x1: | |
424 | cpld->reg1 = value; | |
425 | break; | |
426 | default: | |
427 | break; | |
428 | } | |
429 | } | |
430 | ||
431 | static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr) | |
432 | { | |
433 | uint32_t ret; | |
434 | ||
435 | ret = taihu_cpld_readb(opaque, addr) << 8; | |
436 | ret |= taihu_cpld_readb(opaque, addr + 1); | |
437 | ||
438 | return ret; | |
439 | } | |
440 | ||
441 | static void taihu_cpld_writew (void *opaque, | |
442 | target_phys_addr_t addr, uint32_t value) | |
443 | { | |
444 | taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); | |
445 | taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); | |
446 | } | |
447 | ||
448 | static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr) | |
449 | { | |
450 | uint32_t ret; | |
451 | ||
452 | ret = taihu_cpld_readb(opaque, addr) << 24; | |
453 | ret |= taihu_cpld_readb(opaque, addr + 1) << 16; | |
454 | ret |= taihu_cpld_readb(opaque, addr + 2) << 8; | |
455 | ret |= taihu_cpld_readb(opaque, addr + 3); | |
456 | ||
457 | return ret; | |
458 | } | |
459 | ||
460 | static void taihu_cpld_writel (void *opaque, | |
461 | target_phys_addr_t addr, uint32_t value) | |
462 | { | |
463 | taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); | |
464 | taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); | |
465 | taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); | |
466 | taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); | |
467 | } | |
468 | ||
469 | static CPUReadMemoryFunc *taihu_cpld_read[] = { | |
470 | &taihu_cpld_readb, | |
471 | &taihu_cpld_readw, | |
472 | &taihu_cpld_readl, | |
473 | }; | |
474 | ||
475 | static CPUWriteMemoryFunc *taihu_cpld_write[] = { | |
476 | &taihu_cpld_writeb, | |
477 | &taihu_cpld_writew, | |
478 | &taihu_cpld_writel, | |
479 | }; | |
480 | ||
481 | static void taihu_cpld_reset (void *opaque) | |
482 | { | |
483 | taihu_cpld_t *cpld; | |
484 | ||
485 | cpld = opaque; | |
486 | cpld->reg0 = 0x01; | |
487 | cpld->reg1 = 0x80; | |
488 | } | |
489 | ||
490 | static void taihu_cpld_init (uint32_t base) | |
491 | { | |
492 | taihu_cpld_t *cpld; | |
493 | int cpld_memory; | |
494 | ||
495 | cpld = qemu_mallocz(sizeof(taihu_cpld_t)); | |
496 | if (cpld != NULL) { | |
497 | cpld->base = base; | |
498 | cpld_memory = cpu_register_io_memory(0, taihu_cpld_read, | |
499 | taihu_cpld_write, cpld); | |
500 | cpu_register_physical_memory(base, 0x00000100, cpld_memory); | |
501 | taihu_cpld_reset(cpld); | |
502 | qemu_register_reset(&taihu_cpld_reset, cpld); | |
503 | } | |
504 | } | |
505 | ||
00f82b8a | 506 | static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
6ac0e82d | 507 | const char *boot_device, DisplayState *ds, |
5fafdf24 | 508 | const char *kernel_filename, |
1a6c0886 JM |
509 | const char *kernel_cmdline, |
510 | const char *initrd_filename, | |
511 | const char *cpu_model) | |
512 | { | |
513 | char buf[1024]; | |
514 | CPUPPCState *env; | |
515 | qemu_irq *pic; | |
516 | ram_addr_t bios_offset; | |
71db710f | 517 | target_phys_addr_t ram_bases[2], ram_sizes[2]; |
1a6c0886 JM |
518 | target_ulong bios_size; |
519 | target_ulong kernel_base, kernel_size, initrd_base, initrd_size; | |
520 | int linux_boot; | |
521 | int fl_idx, fl_sectors; | |
6ac0e82d | 522 | int ppc_boot_device = boot_device[0]; |
e4bcb14c | 523 | int index; |
3b46e624 | 524 | |
1a6c0886 JM |
525 | /* RAM is soldered to the board so the size cannot be changed */ |
526 | ram_bases[0] = 0x00000000; | |
527 | ram_sizes[0] = 0x04000000; | |
528 | ram_bases[1] = 0x04000000; | |
529 | ram_sizes[1] = 0x04000000; | |
530 | #ifdef DEBUG_BOARD_INIT | |
531 | printf("%s: register cpu\n", __func__); | |
532 | #endif | |
533 | env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset, | |
534 | kernel_filename == NULL ? 0 : 1); | |
535 | /* allocate and load BIOS */ | |
536 | #ifdef DEBUG_BOARD_INIT | |
537 | printf("%s: register BIOS\n", __func__); | |
538 | #endif | |
539 | fl_idx = 0; | |
540 | #if defined(USE_FLASH_BIOS) | |
e4bcb14c TS |
541 | index = drive_get_index(IF_PFLASH, 0, fl_idx); |
542 | if (index != -1) { | |
543 | bios_size = bdrv_getlength(drives_table[index].bdrv); | |
1a6c0886 JM |
544 | /* XXX: should check that size is 2MB */ |
545 | // bios_size = 2 * 1024 * 1024; | |
546 | fl_sectors = (bios_size + 65535) >> 16; | |
547 | #ifdef DEBUG_BOARD_INIT | |
548 | printf("Register parallel flash %d size " ADDRX " at offset %08lx " | |
549 | " addr " ADDRX " '%s' %d\n", | |
550 | fl_idx, bios_size, bios_offset, -bios_size, | |
e4bcb14c | 551 | bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); |
1a6c0886 | 552 | #endif |
88eeee0a | 553 | pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
4fbd24ba AZ |
554 | drives_table[index].bdrv, 65536, fl_sectors, 1, |
555 | 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); | |
1a6c0886 JM |
556 | fl_idx++; |
557 | } else | |
558 | #endif | |
559 | { | |
560 | #ifdef DEBUG_BOARD_INIT | |
561 | printf("Load BIOS from file\n"); | |
562 | #endif | |
1192dad8 JM |
563 | if (bios_name == NULL) |
564 | bios_name = BIOS_FILENAME; | |
565 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
1a6c0886 JM |
566 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
567 | if (bios_size < 0 || bios_size > BIOS_SIZE) { | |
568 | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf); | |
569 | exit(1); | |
570 | } | |
571 | bios_size = (bios_size + 0xfff) & ~0xfff; | |
5fafdf24 | 572 | cpu_register_physical_memory((uint32_t)(-bios_size), |
1a6c0886 JM |
573 | bios_size, bios_offset | IO_MEM_ROM); |
574 | } | |
575 | bios_offset += bios_size; | |
576 | /* Register Linux flash */ | |
e4bcb14c TS |
577 | index = drive_get_index(IF_PFLASH, 0, fl_idx); |
578 | if (index != -1) { | |
579 | bios_size = bdrv_getlength(drives_table[index].bdrv); | |
1a6c0886 JM |
580 | /* XXX: should check that size is 32MB */ |
581 | bios_size = 32 * 1024 * 1024; | |
582 | fl_sectors = (bios_size + 65535) >> 16; | |
583 | #ifdef DEBUG_BOARD_INIT | |
584 | printf("Register parallel flash %d size " ADDRX " at offset %08lx " | |
585 | " addr " ADDRX " '%s'\n", | |
586 | fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000, | |
e4bcb14c | 587 | bdrv_get_device_name(drives_table[index].bdrv)); |
1a6c0886 | 588 | #endif |
88eeee0a | 589 | pflash_cfi02_register(0xfc000000, bios_offset, |
4fbd24ba AZ |
590 | drives_table[index].bdrv, 65536, fl_sectors, 1, |
591 | 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); | |
1a6c0886 JM |
592 | fl_idx++; |
593 | } | |
594 | /* Register CLPD & LCD display */ | |
595 | #ifdef DEBUG_BOARD_INIT | |
596 | printf("%s: register CPLD\n", __func__); | |
597 | #endif | |
598 | taihu_cpld_init(0x50100000); | |
599 | /* Load kernel */ | |
600 | linux_boot = (kernel_filename != NULL); | |
601 | if (linux_boot) { | |
602 | #ifdef DEBUG_BOARD_INIT | |
603 | printf("%s: load kernel\n", __func__); | |
604 | #endif | |
605 | kernel_base = KERNEL_LOAD_ADDR; | |
606 | /* now we can load the kernel */ | |
607 | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); | |
608 | if (kernel_size < 0) { | |
5fafdf24 | 609 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
1a6c0886 JM |
610 | kernel_filename); |
611 | exit(1); | |
612 | } | |
613 | /* load initrd */ | |
614 | if (initrd_filename) { | |
615 | initrd_base = INITRD_LOAD_ADDR; | |
616 | initrd_size = load_image(initrd_filename, | |
617 | phys_ram_base + initrd_base); | |
618 | if (initrd_size < 0) { | |
619 | fprintf(stderr, | |
5fafdf24 | 620 | "qemu: could not load initial ram disk '%s'\n", |
1a6c0886 JM |
621 | initrd_filename); |
622 | exit(1); | |
623 | } | |
624 | } else { | |
625 | initrd_base = 0; | |
626 | initrd_size = 0; | |
627 | } | |
6ac0e82d | 628 | ppc_boot_device = 'm'; |
1a6c0886 JM |
629 | } else { |
630 | kernel_base = 0; | |
631 | kernel_size = 0; | |
632 | initrd_base = 0; | |
633 | initrd_size = 0; | |
634 | } | |
635 | #ifdef DEBUG_BOARD_INIT | |
636 | printf("%s: Done\n", __func__); | |
637 | #endif | |
638 | } | |
639 | ||
640 | QEMUMachine taihu_machine = { | |
641 | "taihu", | |
642 | "taihu", | |
643 | taihu_405ep_init, | |
7fb4fdcf | 644 | (128 * 1024 * 1024 + 4096 + BIOS_SIZE + 32 * 1024 * 1024) | RAMSIZE_FIXED, |
1a6c0886 | 645 | }; |