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8ecc7913 JM |
1 | /* |
2 | * QEMU PowerPC 405 embedded processors emulation | |
5fafdf24 | 3 | * |
8ecc7913 | 4 | * Copyright (c) 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
8ecc7913 JM |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "ppc.h" | |
04f20795 | 26 | #include "ppc405.h" |
87ecb68b PB |
27 | #include "pc.h" |
28 | #include "qemu-timer.h" | |
29 | #include "sysemu.h" | |
3b3fb322 | 30 | #include "qemu-log.h" |
8ecc7913 | 31 | |
8ecc7913 JM |
32 | #define DEBUG_OPBA |
33 | #define DEBUG_SDRAM | |
34 | #define DEBUG_GPIO | |
35 | #define DEBUG_SERIAL | |
36 | #define DEBUG_OCM | |
9c02f1a2 JM |
37 | //#define DEBUG_I2C |
38 | #define DEBUG_GPT | |
39 | #define DEBUG_MAL | |
8ecc7913 | 40 | #define DEBUG_CLOCKS |
aae9366a | 41 | //#define DEBUG_CLOCKS_LL |
8ecc7913 | 42 | |
b8d3f5d1 JM |
43 | ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
44 | uint32_t flags) | |
04f20795 JM |
45 | { |
46 | ram_addr_t bdloc; | |
47 | int i, n; | |
48 | ||
49 | /* We put the bd structure at the top of memory */ | |
be58fc7c JM |
50 | if (bd->bi_memsize >= 0x01000000UL) |
51 | bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); | |
52 | else | |
53 | bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); | |
5c130f65 PB |
54 | stl_phys(bdloc + 0x00, bd->bi_memstart); |
55 | stl_phys(bdloc + 0x04, bd->bi_memsize); | |
56 | stl_phys(bdloc + 0x08, bd->bi_flashstart); | |
57 | stl_phys(bdloc + 0x0C, bd->bi_flashsize); | |
58 | stl_phys(bdloc + 0x10, bd->bi_flashoffset); | |
59 | stl_phys(bdloc + 0x14, bd->bi_sramstart); | |
60 | stl_phys(bdloc + 0x18, bd->bi_sramsize); | |
61 | stl_phys(bdloc + 0x1C, bd->bi_bootflags); | |
62 | stl_phys(bdloc + 0x20, bd->bi_ipaddr); | |
04f20795 | 63 | for (i = 0; i < 6; i++) |
5c130f65 PB |
64 | stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]); |
65 | stw_phys(bdloc + 0x2A, bd->bi_ethspeed); | |
66 | stl_phys(bdloc + 0x2C, bd->bi_intfreq); | |
67 | stl_phys(bdloc + 0x30, bd->bi_busfreq); | |
68 | stl_phys(bdloc + 0x34, bd->bi_baudrate); | |
04f20795 | 69 | for (i = 0; i < 4; i++) |
5c130f65 | 70 | stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]); |
04f20795 | 71 | for (i = 0; i < 32; i++) |
5c130f65 PB |
72 | stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]); |
73 | stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq); | |
74 | stl_phys(bdloc + 0x60, bd->bi_pci_busfreq); | |
04f20795 | 75 | for (i = 0; i < 6; i++) |
5c130f65 | 76 | stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); |
04f20795 | 77 | n = 0x6A; |
b8d3f5d1 | 78 | if (flags & 0x00000001) { |
04f20795 | 79 | for (i = 0; i < 6; i++) |
5c130f65 | 80 | stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]); |
04f20795 | 81 | } |
5c130f65 | 82 | stl_phys(bdloc + n, bd->bi_opbfreq); |
04f20795 JM |
83 | n += 4; |
84 | for (i = 0; i < 2; i++) { | |
5c130f65 | 85 | stl_phys(bdloc + n, bd->bi_iic_fast[i]); |
04f20795 JM |
86 | n += 4; |
87 | } | |
88 | ||
89 | return bdloc; | |
90 | } | |
91 | ||
8ecc7913 JM |
92 | /*****************************************************************************/ |
93 | /* Shared peripherals */ | |
94 | ||
8ecc7913 JM |
95 | /*****************************************************************************/ |
96 | /* Peripheral local bus arbitrer */ | |
97 | enum { | |
98 | PLB0_BESR = 0x084, | |
99 | PLB0_BEAR = 0x086, | |
100 | PLB0_ACR = 0x087, | |
101 | }; | |
102 | ||
103 | typedef struct ppc4xx_plb_t ppc4xx_plb_t; | |
104 | struct ppc4xx_plb_t { | |
105 | uint32_t acr; | |
106 | uint32_t bear; | |
107 | uint32_t besr; | |
108 | }; | |
109 | ||
110 | static target_ulong dcr_read_plb (void *opaque, int dcrn) | |
111 | { | |
112 | ppc4xx_plb_t *plb; | |
113 | target_ulong ret; | |
114 | ||
115 | plb = opaque; | |
116 | switch (dcrn) { | |
117 | case PLB0_ACR: | |
118 | ret = plb->acr; | |
119 | break; | |
120 | case PLB0_BEAR: | |
121 | ret = plb->bear; | |
122 | break; | |
123 | case PLB0_BESR: | |
124 | ret = plb->besr; | |
125 | break; | |
126 | default: | |
127 | /* Avoid gcc warning */ | |
128 | ret = 0; | |
129 | break; | |
130 | } | |
131 | ||
132 | return ret; | |
133 | } | |
134 | ||
135 | static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) | |
136 | { | |
137 | ppc4xx_plb_t *plb; | |
138 | ||
139 | plb = opaque; | |
140 | switch (dcrn) { | |
141 | case PLB0_ACR: | |
9c02f1a2 JM |
142 | /* We don't care about the actual parameters written as |
143 | * we don't manage any priorities on the bus | |
144 | */ | |
145 | plb->acr = val & 0xF8000000; | |
8ecc7913 JM |
146 | break; |
147 | case PLB0_BEAR: | |
148 | /* Read only */ | |
149 | break; | |
150 | case PLB0_BESR: | |
151 | /* Write-clear */ | |
152 | plb->besr &= ~val; | |
153 | break; | |
154 | } | |
155 | } | |
156 | ||
157 | static void ppc4xx_plb_reset (void *opaque) | |
158 | { | |
159 | ppc4xx_plb_t *plb; | |
160 | ||
161 | plb = opaque; | |
162 | plb->acr = 0x00000000; | |
163 | plb->bear = 0x00000000; | |
164 | plb->besr = 0x00000000; | |
165 | } | |
166 | ||
802670e6 | 167 | static void ppc4xx_plb_init(CPUState *env) |
8ecc7913 JM |
168 | { |
169 | ppc4xx_plb_t *plb; | |
170 | ||
171 | plb = qemu_mallocz(sizeof(ppc4xx_plb_t)); | |
487414f1 AL |
172 | ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
173 | ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); | |
174 | ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); | |
175 | ppc4xx_plb_reset(plb); | |
a08d4367 | 176 | qemu_register_reset(ppc4xx_plb_reset, plb); |
8ecc7913 JM |
177 | } |
178 | ||
179 | /*****************************************************************************/ | |
180 | /* PLB to OPB bridge */ | |
181 | enum { | |
182 | POB0_BESR0 = 0x0A0, | |
183 | POB0_BESR1 = 0x0A2, | |
184 | POB0_BEAR = 0x0A4, | |
185 | }; | |
186 | ||
187 | typedef struct ppc4xx_pob_t ppc4xx_pob_t; | |
188 | struct ppc4xx_pob_t { | |
189 | uint32_t bear; | |
190 | uint32_t besr[2]; | |
191 | }; | |
192 | ||
193 | static target_ulong dcr_read_pob (void *opaque, int dcrn) | |
194 | { | |
195 | ppc4xx_pob_t *pob; | |
196 | target_ulong ret; | |
197 | ||
198 | pob = opaque; | |
199 | switch (dcrn) { | |
200 | case POB0_BEAR: | |
201 | ret = pob->bear; | |
202 | break; | |
203 | case POB0_BESR0: | |
204 | case POB0_BESR1: | |
205 | ret = pob->besr[dcrn - POB0_BESR0]; | |
206 | break; | |
207 | default: | |
208 | /* Avoid gcc warning */ | |
209 | ret = 0; | |
210 | break; | |
211 | } | |
212 | ||
213 | return ret; | |
214 | } | |
215 | ||
216 | static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) | |
217 | { | |
218 | ppc4xx_pob_t *pob; | |
219 | ||
220 | pob = opaque; | |
221 | switch (dcrn) { | |
222 | case POB0_BEAR: | |
223 | /* Read only */ | |
224 | break; | |
225 | case POB0_BESR0: | |
226 | case POB0_BESR1: | |
227 | /* Write-clear */ | |
228 | pob->besr[dcrn - POB0_BESR0] &= ~val; | |
229 | break; | |
230 | } | |
231 | } | |
232 | ||
233 | static void ppc4xx_pob_reset (void *opaque) | |
234 | { | |
235 | ppc4xx_pob_t *pob; | |
236 | ||
237 | pob = opaque; | |
238 | /* No error */ | |
239 | pob->bear = 0x00000000; | |
240 | pob->besr[0] = 0x0000000; | |
241 | pob->besr[1] = 0x0000000; | |
242 | } | |
243 | ||
802670e6 | 244 | static void ppc4xx_pob_init(CPUState *env) |
8ecc7913 JM |
245 | { |
246 | ppc4xx_pob_t *pob; | |
247 | ||
248 | pob = qemu_mallocz(sizeof(ppc4xx_pob_t)); | |
487414f1 AL |
249 | ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
250 | ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); | |
251 | ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); | |
a08d4367 | 252 | qemu_register_reset(ppc4xx_pob_reset, pob); |
802670e6 | 253 | ppc4xx_pob_reset(pob); |
8ecc7913 JM |
254 | } |
255 | ||
256 | /*****************************************************************************/ | |
257 | /* OPB arbitrer */ | |
258 | typedef struct ppc4xx_opba_t ppc4xx_opba_t; | |
259 | struct ppc4xx_opba_t { | |
8ecc7913 JM |
260 | uint8_t cr; |
261 | uint8_t pr; | |
262 | }; | |
263 | ||
264 | static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) | |
265 | { | |
266 | ppc4xx_opba_t *opba; | |
267 | uint32_t ret; | |
268 | ||
269 | #ifdef DEBUG_OPBA | |
270 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
271 | #endif | |
272 | opba = opaque; | |
802670e6 | 273 | switch (addr) { |
8ecc7913 JM |
274 | case 0x00: |
275 | ret = opba->cr; | |
276 | break; | |
277 | case 0x01: | |
278 | ret = opba->pr; | |
279 | break; | |
280 | default: | |
281 | ret = 0x00; | |
282 | break; | |
283 | } | |
284 | ||
285 | return ret; | |
286 | } | |
287 | ||
288 | static void opba_writeb (void *opaque, | |
289 | target_phys_addr_t addr, uint32_t value) | |
290 | { | |
291 | ppc4xx_opba_t *opba; | |
292 | ||
293 | #ifdef DEBUG_OPBA | |
aae9366a | 294 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
295 | #endif |
296 | opba = opaque; | |
802670e6 | 297 | switch (addr) { |
8ecc7913 JM |
298 | case 0x00: |
299 | opba->cr = value & 0xF8; | |
300 | break; | |
301 | case 0x01: | |
302 | opba->pr = value & 0xFF; | |
303 | break; | |
304 | default: | |
305 | break; | |
306 | } | |
307 | } | |
308 | ||
309 | static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) | |
310 | { | |
311 | uint32_t ret; | |
312 | ||
313 | #ifdef DEBUG_OPBA | |
314 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
315 | #endif | |
316 | ret = opba_readb(opaque, addr) << 8; | |
317 | ret |= opba_readb(opaque, addr + 1); | |
318 | ||
319 | return ret; | |
320 | } | |
321 | ||
322 | static void opba_writew (void *opaque, | |
323 | target_phys_addr_t addr, uint32_t value) | |
324 | { | |
325 | #ifdef DEBUG_OPBA | |
aae9366a | 326 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
327 | #endif |
328 | opba_writeb(opaque, addr, value >> 8); | |
329 | opba_writeb(opaque, addr + 1, value); | |
330 | } | |
331 | ||
332 | static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) | |
333 | { | |
334 | uint32_t ret; | |
335 | ||
336 | #ifdef DEBUG_OPBA | |
337 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
338 | #endif | |
339 | ret = opba_readb(opaque, addr) << 24; | |
340 | ret |= opba_readb(opaque, addr + 1) << 16; | |
341 | ||
342 | return ret; | |
343 | } | |
344 | ||
345 | static void opba_writel (void *opaque, | |
346 | target_phys_addr_t addr, uint32_t value) | |
347 | { | |
348 | #ifdef DEBUG_OPBA | |
aae9366a | 349 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
350 | #endif |
351 | opba_writeb(opaque, addr, value >> 24); | |
352 | opba_writeb(opaque, addr + 1, value >> 16); | |
353 | } | |
354 | ||
355 | static CPUReadMemoryFunc *opba_read[] = { | |
356 | &opba_readb, | |
357 | &opba_readw, | |
358 | &opba_readl, | |
359 | }; | |
360 | ||
361 | static CPUWriteMemoryFunc *opba_write[] = { | |
362 | &opba_writeb, | |
363 | &opba_writew, | |
364 | &opba_writel, | |
365 | }; | |
366 | ||
367 | static void ppc4xx_opba_reset (void *opaque) | |
368 | { | |
369 | ppc4xx_opba_t *opba; | |
370 | ||
371 | opba = opaque; | |
372 | opba->cr = 0x00; /* No dynamic priorities - park disabled */ | |
373 | opba->pr = 0x11; | |
374 | } | |
375 | ||
802670e6 | 376 | static void ppc4xx_opba_init(target_phys_addr_t base) |
8ecc7913 JM |
377 | { |
378 | ppc4xx_opba_t *opba; | |
802670e6 | 379 | int io; |
8ecc7913 JM |
380 | |
381 | opba = qemu_mallocz(sizeof(ppc4xx_opba_t)); | |
8ecc7913 | 382 | #ifdef DEBUG_OPBA |
802670e6 | 383 | printf("%s: offset " PADDRX "\n", __func__, base); |
8ecc7913 | 384 | #endif |
802670e6 BS |
385 | io = cpu_register_io_memory(opba_read, opba_write, opba); |
386 | cpu_register_physical_memory(base, 0x002, io); | |
487414f1 | 387 | ppc4xx_opba_reset(opba); |
802670e6 | 388 | qemu_register_reset(ppc4xx_opba_reset, opba); |
8ecc7913 JM |
389 | } |
390 | ||
8ecc7913 JM |
391 | /*****************************************************************************/ |
392 | /* Code decompression controller */ | |
393 | /* XXX: TODO */ | |
394 | ||
8ecc7913 JM |
395 | /*****************************************************************************/ |
396 | /* Peripheral controller */ | |
397 | typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; | |
398 | struct ppc4xx_ebc_t { | |
399 | uint32_t addr; | |
400 | uint32_t bcr[8]; | |
401 | uint32_t bap[8]; | |
402 | uint32_t bear; | |
403 | uint32_t besr0; | |
404 | uint32_t besr1; | |
405 | uint32_t cfg; | |
406 | }; | |
407 | ||
408 | enum { | |
409 | EBC0_CFGADDR = 0x012, | |
410 | EBC0_CFGDATA = 0x013, | |
411 | }; | |
412 | ||
413 | static target_ulong dcr_read_ebc (void *opaque, int dcrn) | |
414 | { | |
415 | ppc4xx_ebc_t *ebc; | |
416 | target_ulong ret; | |
417 | ||
418 | ebc = opaque; | |
419 | switch (dcrn) { | |
420 | case EBC0_CFGADDR: | |
421 | ret = ebc->addr; | |
422 | break; | |
423 | case EBC0_CFGDATA: | |
424 | switch (ebc->addr) { | |
425 | case 0x00: /* B0CR */ | |
426 | ret = ebc->bcr[0]; | |
427 | break; | |
428 | case 0x01: /* B1CR */ | |
429 | ret = ebc->bcr[1]; | |
430 | break; | |
431 | case 0x02: /* B2CR */ | |
432 | ret = ebc->bcr[2]; | |
433 | break; | |
434 | case 0x03: /* B3CR */ | |
435 | ret = ebc->bcr[3]; | |
436 | break; | |
437 | case 0x04: /* B4CR */ | |
438 | ret = ebc->bcr[4]; | |
439 | break; | |
440 | case 0x05: /* B5CR */ | |
441 | ret = ebc->bcr[5]; | |
442 | break; | |
443 | case 0x06: /* B6CR */ | |
444 | ret = ebc->bcr[6]; | |
445 | break; | |
446 | case 0x07: /* B7CR */ | |
447 | ret = ebc->bcr[7]; | |
448 | break; | |
449 | case 0x10: /* B0AP */ | |
450 | ret = ebc->bap[0]; | |
451 | break; | |
452 | case 0x11: /* B1AP */ | |
453 | ret = ebc->bap[1]; | |
454 | break; | |
455 | case 0x12: /* B2AP */ | |
456 | ret = ebc->bap[2]; | |
457 | break; | |
458 | case 0x13: /* B3AP */ | |
459 | ret = ebc->bap[3]; | |
460 | break; | |
461 | case 0x14: /* B4AP */ | |
462 | ret = ebc->bap[4]; | |
463 | break; | |
464 | case 0x15: /* B5AP */ | |
465 | ret = ebc->bap[5]; | |
466 | break; | |
467 | case 0x16: /* B6AP */ | |
468 | ret = ebc->bap[6]; | |
469 | break; | |
470 | case 0x17: /* B7AP */ | |
471 | ret = ebc->bap[7]; | |
472 | break; | |
473 | case 0x20: /* BEAR */ | |
474 | ret = ebc->bear; | |
475 | break; | |
476 | case 0x21: /* BESR0 */ | |
477 | ret = ebc->besr0; | |
478 | break; | |
479 | case 0x22: /* BESR1 */ | |
480 | ret = ebc->besr1; | |
481 | break; | |
482 | case 0x23: /* CFG */ | |
483 | ret = ebc->cfg; | |
484 | break; | |
485 | default: | |
486 | ret = 0x00000000; | |
487 | break; | |
488 | } | |
489 | default: | |
490 | ret = 0x00000000; | |
491 | break; | |
492 | } | |
493 | ||
494 | return ret; | |
495 | } | |
496 | ||
497 | static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) | |
498 | { | |
499 | ppc4xx_ebc_t *ebc; | |
500 | ||
501 | ebc = opaque; | |
502 | switch (dcrn) { | |
503 | case EBC0_CFGADDR: | |
504 | ebc->addr = val; | |
505 | break; | |
506 | case EBC0_CFGDATA: | |
507 | switch (ebc->addr) { | |
508 | case 0x00: /* B0CR */ | |
509 | break; | |
510 | case 0x01: /* B1CR */ | |
511 | break; | |
512 | case 0x02: /* B2CR */ | |
513 | break; | |
514 | case 0x03: /* B3CR */ | |
515 | break; | |
516 | case 0x04: /* B4CR */ | |
517 | break; | |
518 | case 0x05: /* B5CR */ | |
519 | break; | |
520 | case 0x06: /* B6CR */ | |
521 | break; | |
522 | case 0x07: /* B7CR */ | |
523 | break; | |
524 | case 0x10: /* B0AP */ | |
525 | break; | |
526 | case 0x11: /* B1AP */ | |
527 | break; | |
528 | case 0x12: /* B2AP */ | |
529 | break; | |
530 | case 0x13: /* B3AP */ | |
531 | break; | |
532 | case 0x14: /* B4AP */ | |
533 | break; | |
534 | case 0x15: /* B5AP */ | |
535 | break; | |
536 | case 0x16: /* B6AP */ | |
537 | break; | |
538 | case 0x17: /* B7AP */ | |
539 | break; | |
540 | case 0x20: /* BEAR */ | |
541 | break; | |
542 | case 0x21: /* BESR0 */ | |
543 | break; | |
544 | case 0x22: /* BESR1 */ | |
545 | break; | |
546 | case 0x23: /* CFG */ | |
547 | break; | |
548 | default: | |
549 | break; | |
550 | } | |
551 | break; | |
552 | default: | |
553 | break; | |
554 | } | |
555 | } | |
556 | ||
557 | static void ebc_reset (void *opaque) | |
558 | { | |
559 | ppc4xx_ebc_t *ebc; | |
560 | int i; | |
561 | ||
562 | ebc = opaque; | |
563 | ebc->addr = 0x00000000; | |
564 | ebc->bap[0] = 0x7F8FFE80; | |
565 | ebc->bcr[0] = 0xFFE28000; | |
566 | for (i = 0; i < 8; i++) { | |
567 | ebc->bap[i] = 0x00000000; | |
568 | ebc->bcr[i] = 0x00000000; | |
569 | } | |
570 | ebc->besr0 = 0x00000000; | |
571 | ebc->besr1 = 0x00000000; | |
9c02f1a2 | 572 | ebc->cfg = 0x80400000; |
8ecc7913 JM |
573 | } |
574 | ||
802670e6 | 575 | static void ppc405_ebc_init(CPUState *env) |
8ecc7913 JM |
576 | { |
577 | ppc4xx_ebc_t *ebc; | |
578 | ||
579 | ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t)); | |
487414f1 | 580 | ebc_reset(ebc); |
a08d4367 | 581 | qemu_register_reset(&ebc_reset, ebc); |
487414f1 AL |
582 | ppc_dcr_register(env, EBC0_CFGADDR, |
583 | ebc, &dcr_read_ebc, &dcr_write_ebc); | |
584 | ppc_dcr_register(env, EBC0_CFGDATA, | |
585 | ebc, &dcr_read_ebc, &dcr_write_ebc); | |
8ecc7913 JM |
586 | } |
587 | ||
588 | /*****************************************************************************/ | |
589 | /* DMA controller */ | |
590 | enum { | |
591 | DMA0_CR0 = 0x100, | |
592 | DMA0_CT0 = 0x101, | |
593 | DMA0_DA0 = 0x102, | |
594 | DMA0_SA0 = 0x103, | |
595 | DMA0_SG0 = 0x104, | |
596 | DMA0_CR1 = 0x108, | |
597 | DMA0_CT1 = 0x109, | |
598 | DMA0_DA1 = 0x10A, | |
599 | DMA0_SA1 = 0x10B, | |
600 | DMA0_SG1 = 0x10C, | |
601 | DMA0_CR2 = 0x110, | |
602 | DMA0_CT2 = 0x111, | |
603 | DMA0_DA2 = 0x112, | |
604 | DMA0_SA2 = 0x113, | |
605 | DMA0_SG2 = 0x114, | |
606 | DMA0_CR3 = 0x118, | |
607 | DMA0_CT3 = 0x119, | |
608 | DMA0_DA3 = 0x11A, | |
609 | DMA0_SA3 = 0x11B, | |
610 | DMA0_SG3 = 0x11C, | |
611 | DMA0_SR = 0x120, | |
612 | DMA0_SGC = 0x123, | |
613 | DMA0_SLP = 0x125, | |
614 | DMA0_POL = 0x126, | |
615 | }; | |
616 | ||
617 | typedef struct ppc405_dma_t ppc405_dma_t; | |
618 | struct ppc405_dma_t { | |
619 | qemu_irq irqs[4]; | |
620 | uint32_t cr[4]; | |
621 | uint32_t ct[4]; | |
622 | uint32_t da[4]; | |
623 | uint32_t sa[4]; | |
624 | uint32_t sg[4]; | |
625 | uint32_t sr; | |
626 | uint32_t sgc; | |
627 | uint32_t slp; | |
628 | uint32_t pol; | |
629 | }; | |
630 | ||
631 | static target_ulong dcr_read_dma (void *opaque, int dcrn) | |
632 | { | |
633 | ppc405_dma_t *dma; | |
634 | ||
635 | dma = opaque; | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) | |
641 | { | |
642 | ppc405_dma_t *dma; | |
643 | ||
644 | dma = opaque; | |
645 | } | |
646 | ||
647 | static void ppc405_dma_reset (void *opaque) | |
648 | { | |
649 | ppc405_dma_t *dma; | |
650 | int i; | |
651 | ||
652 | dma = opaque; | |
653 | for (i = 0; i < 4; i++) { | |
654 | dma->cr[i] = 0x00000000; | |
655 | dma->ct[i] = 0x00000000; | |
656 | dma->da[i] = 0x00000000; | |
657 | dma->sa[i] = 0x00000000; | |
658 | dma->sg[i] = 0x00000000; | |
659 | } | |
660 | dma->sr = 0x00000000; | |
661 | dma->sgc = 0x00000000; | |
662 | dma->slp = 0x7C000000; | |
663 | dma->pol = 0x00000000; | |
664 | } | |
665 | ||
802670e6 | 666 | static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) |
8ecc7913 JM |
667 | { |
668 | ppc405_dma_t *dma; | |
669 | ||
670 | dma = qemu_mallocz(sizeof(ppc405_dma_t)); | |
487414f1 AL |
671 | memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
672 | ppc405_dma_reset(dma); | |
a08d4367 | 673 | qemu_register_reset(&ppc405_dma_reset, dma); |
487414f1 AL |
674 | ppc_dcr_register(env, DMA0_CR0, |
675 | dma, &dcr_read_dma, &dcr_write_dma); | |
676 | ppc_dcr_register(env, DMA0_CT0, | |
677 | dma, &dcr_read_dma, &dcr_write_dma); | |
678 | ppc_dcr_register(env, DMA0_DA0, | |
679 | dma, &dcr_read_dma, &dcr_write_dma); | |
680 | ppc_dcr_register(env, DMA0_SA0, | |
681 | dma, &dcr_read_dma, &dcr_write_dma); | |
682 | ppc_dcr_register(env, DMA0_SG0, | |
683 | dma, &dcr_read_dma, &dcr_write_dma); | |
684 | ppc_dcr_register(env, DMA0_CR1, | |
685 | dma, &dcr_read_dma, &dcr_write_dma); | |
686 | ppc_dcr_register(env, DMA0_CT1, | |
687 | dma, &dcr_read_dma, &dcr_write_dma); | |
688 | ppc_dcr_register(env, DMA0_DA1, | |
689 | dma, &dcr_read_dma, &dcr_write_dma); | |
690 | ppc_dcr_register(env, DMA0_SA1, | |
691 | dma, &dcr_read_dma, &dcr_write_dma); | |
692 | ppc_dcr_register(env, DMA0_SG1, | |
693 | dma, &dcr_read_dma, &dcr_write_dma); | |
694 | ppc_dcr_register(env, DMA0_CR2, | |
695 | dma, &dcr_read_dma, &dcr_write_dma); | |
696 | ppc_dcr_register(env, DMA0_CT2, | |
697 | dma, &dcr_read_dma, &dcr_write_dma); | |
698 | ppc_dcr_register(env, DMA0_DA2, | |
699 | dma, &dcr_read_dma, &dcr_write_dma); | |
700 | ppc_dcr_register(env, DMA0_SA2, | |
701 | dma, &dcr_read_dma, &dcr_write_dma); | |
702 | ppc_dcr_register(env, DMA0_SG2, | |
703 | dma, &dcr_read_dma, &dcr_write_dma); | |
704 | ppc_dcr_register(env, DMA0_CR3, | |
705 | dma, &dcr_read_dma, &dcr_write_dma); | |
706 | ppc_dcr_register(env, DMA0_CT3, | |
707 | dma, &dcr_read_dma, &dcr_write_dma); | |
708 | ppc_dcr_register(env, DMA0_DA3, | |
709 | dma, &dcr_read_dma, &dcr_write_dma); | |
710 | ppc_dcr_register(env, DMA0_SA3, | |
711 | dma, &dcr_read_dma, &dcr_write_dma); | |
712 | ppc_dcr_register(env, DMA0_SG3, | |
713 | dma, &dcr_read_dma, &dcr_write_dma); | |
714 | ppc_dcr_register(env, DMA0_SR, | |
715 | dma, &dcr_read_dma, &dcr_write_dma); | |
716 | ppc_dcr_register(env, DMA0_SGC, | |
717 | dma, &dcr_read_dma, &dcr_write_dma); | |
718 | ppc_dcr_register(env, DMA0_SLP, | |
719 | dma, &dcr_read_dma, &dcr_write_dma); | |
720 | ppc_dcr_register(env, DMA0_POL, | |
721 | dma, &dcr_read_dma, &dcr_write_dma); | |
8ecc7913 JM |
722 | } |
723 | ||
724 | /*****************************************************************************/ | |
725 | /* GPIO */ | |
726 | typedef struct ppc405_gpio_t ppc405_gpio_t; | |
727 | struct ppc405_gpio_t { | |
8ecc7913 JM |
728 | uint32_t or; |
729 | uint32_t tcr; | |
730 | uint32_t osrh; | |
731 | uint32_t osrl; | |
732 | uint32_t tsrh; | |
733 | uint32_t tsrl; | |
734 | uint32_t odr; | |
735 | uint32_t ir; | |
736 | uint32_t rr1; | |
737 | uint32_t isr1h; | |
738 | uint32_t isr1l; | |
739 | }; | |
740 | ||
741 | static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) | |
742 | { | |
743 | ppc405_gpio_t *gpio; | |
744 | ||
745 | gpio = opaque; | |
746 | #ifdef DEBUG_GPIO | |
747 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
748 | #endif | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | static void ppc405_gpio_writeb (void *opaque, | |
754 | target_phys_addr_t addr, uint32_t value) | |
755 | { | |
756 | ppc405_gpio_t *gpio; | |
757 | ||
758 | gpio = opaque; | |
759 | #ifdef DEBUG_GPIO | |
aae9366a | 760 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
761 | #endif |
762 | } | |
763 | ||
764 | static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) | |
765 | { | |
766 | ppc405_gpio_t *gpio; | |
767 | ||
768 | gpio = opaque; | |
769 | #ifdef DEBUG_GPIO | |
770 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
771 | #endif | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static void ppc405_gpio_writew (void *opaque, | |
777 | target_phys_addr_t addr, uint32_t value) | |
778 | { | |
779 | ppc405_gpio_t *gpio; | |
780 | ||
781 | gpio = opaque; | |
782 | #ifdef DEBUG_GPIO | |
aae9366a | 783 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
784 | #endif |
785 | } | |
786 | ||
787 | static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) | |
788 | { | |
789 | ppc405_gpio_t *gpio; | |
790 | ||
791 | gpio = opaque; | |
792 | #ifdef DEBUG_GPIO | |
793 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
794 | #endif | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | static void ppc405_gpio_writel (void *opaque, | |
800 | target_phys_addr_t addr, uint32_t value) | |
801 | { | |
802 | ppc405_gpio_t *gpio; | |
803 | ||
804 | gpio = opaque; | |
805 | #ifdef DEBUG_GPIO | |
aae9366a | 806 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
807 | #endif |
808 | } | |
809 | ||
810 | static CPUReadMemoryFunc *ppc405_gpio_read[] = { | |
811 | &ppc405_gpio_readb, | |
812 | &ppc405_gpio_readw, | |
813 | &ppc405_gpio_readl, | |
814 | }; | |
815 | ||
816 | static CPUWriteMemoryFunc *ppc405_gpio_write[] = { | |
817 | &ppc405_gpio_writeb, | |
818 | &ppc405_gpio_writew, | |
819 | &ppc405_gpio_writel, | |
820 | }; | |
821 | ||
822 | static void ppc405_gpio_reset (void *opaque) | |
823 | { | |
824 | ppc405_gpio_t *gpio; | |
825 | ||
826 | gpio = opaque; | |
827 | } | |
828 | ||
802670e6 | 829 | static void ppc405_gpio_init(target_phys_addr_t base) |
8ecc7913 JM |
830 | { |
831 | ppc405_gpio_t *gpio; | |
802670e6 | 832 | int io; |
8ecc7913 JM |
833 | |
834 | gpio = qemu_mallocz(sizeof(ppc405_gpio_t)); | |
8ecc7913 | 835 | #ifdef DEBUG_GPIO |
802670e6 | 836 | printf("%s: offset " PADDRX "\n", __func__, base); |
8ecc7913 | 837 | #endif |
802670e6 BS |
838 | io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio); |
839 | cpu_register_physical_memory(base, 0x038, io); | |
840 | ppc405_gpio_reset(gpio); | |
841 | qemu_register_reset(&ppc405_gpio_reset, gpio); | |
8ecc7913 JM |
842 | } |
843 | ||
844 | /*****************************************************************************/ | |
845 | /* On Chip Memory */ | |
846 | enum { | |
847 | OCM0_ISARC = 0x018, | |
848 | OCM0_ISACNTL = 0x019, | |
849 | OCM0_DSARC = 0x01A, | |
850 | OCM0_DSACNTL = 0x01B, | |
851 | }; | |
852 | ||
853 | typedef struct ppc405_ocm_t ppc405_ocm_t; | |
854 | struct ppc405_ocm_t { | |
855 | target_ulong offset; | |
856 | uint32_t isarc; | |
857 | uint32_t isacntl; | |
858 | uint32_t dsarc; | |
859 | uint32_t dsacntl; | |
860 | }; | |
861 | ||
862 | static void ocm_update_mappings (ppc405_ocm_t *ocm, | |
863 | uint32_t isarc, uint32_t isacntl, | |
864 | uint32_t dsarc, uint32_t dsacntl) | |
865 | { | |
866 | #ifdef DEBUG_OCM | |
aae9366a JM |
867 | printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 |
868 | " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 | |
869 | " (%08" PRIx32 " %08" PRIx32 ")\n", | |
8ecc7913 JM |
870 | isarc, isacntl, dsarc, dsacntl, |
871 | ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); | |
872 | #endif | |
873 | if (ocm->isarc != isarc || | |
874 | (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { | |
875 | if (ocm->isacntl & 0x80000000) { | |
876 | /* Unmap previously assigned memory region */ | |
aae9366a | 877 | printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); |
8ecc7913 JM |
878 | cpu_register_physical_memory(ocm->isarc, 0x04000000, |
879 | IO_MEM_UNASSIGNED); | |
880 | } | |
881 | if (isacntl & 0x80000000) { | |
882 | /* Map new instruction memory region */ | |
883 | #ifdef DEBUG_OCM | |
aae9366a | 884 | printf("OCM map ISA %08" PRIx32 "\n", isarc); |
8ecc7913 JM |
885 | #endif |
886 | cpu_register_physical_memory(isarc, 0x04000000, | |
887 | ocm->offset | IO_MEM_RAM); | |
888 | } | |
889 | } | |
890 | if (ocm->dsarc != dsarc || | |
891 | (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { | |
892 | if (ocm->dsacntl & 0x80000000) { | |
893 | /* Beware not to unmap the region we just mapped */ | |
894 | if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { | |
895 | /* Unmap previously assigned memory region */ | |
896 | #ifdef DEBUG_OCM | |
aae9366a | 897 | printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); |
8ecc7913 JM |
898 | #endif |
899 | cpu_register_physical_memory(ocm->dsarc, 0x04000000, | |
900 | IO_MEM_UNASSIGNED); | |
901 | } | |
902 | } | |
903 | if (dsacntl & 0x80000000) { | |
904 | /* Beware not to remap the region we just mapped */ | |
905 | if (!(isacntl & 0x80000000) || dsarc != isarc) { | |
906 | /* Map new data memory region */ | |
907 | #ifdef DEBUG_OCM | |
aae9366a | 908 | printf("OCM map DSA %08" PRIx32 "\n", dsarc); |
8ecc7913 JM |
909 | #endif |
910 | cpu_register_physical_memory(dsarc, 0x04000000, | |
911 | ocm->offset | IO_MEM_RAM); | |
912 | } | |
913 | } | |
914 | } | |
915 | } | |
916 | ||
917 | static target_ulong dcr_read_ocm (void *opaque, int dcrn) | |
918 | { | |
919 | ppc405_ocm_t *ocm; | |
920 | target_ulong ret; | |
921 | ||
922 | ocm = opaque; | |
923 | switch (dcrn) { | |
924 | case OCM0_ISARC: | |
925 | ret = ocm->isarc; | |
926 | break; | |
927 | case OCM0_ISACNTL: | |
928 | ret = ocm->isacntl; | |
929 | break; | |
930 | case OCM0_DSARC: | |
931 | ret = ocm->dsarc; | |
932 | break; | |
933 | case OCM0_DSACNTL: | |
934 | ret = ocm->dsacntl; | |
935 | break; | |
936 | default: | |
937 | ret = 0; | |
938 | break; | |
939 | } | |
940 | ||
941 | return ret; | |
942 | } | |
943 | ||
944 | static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) | |
945 | { | |
946 | ppc405_ocm_t *ocm; | |
947 | uint32_t isarc, dsarc, isacntl, dsacntl; | |
948 | ||
949 | ocm = opaque; | |
950 | isarc = ocm->isarc; | |
951 | dsarc = ocm->dsarc; | |
952 | isacntl = ocm->isacntl; | |
953 | dsacntl = ocm->dsacntl; | |
954 | switch (dcrn) { | |
955 | case OCM0_ISARC: | |
956 | isarc = val & 0xFC000000; | |
957 | break; | |
958 | case OCM0_ISACNTL: | |
959 | isacntl = val & 0xC0000000; | |
960 | break; | |
961 | case OCM0_DSARC: | |
962 | isarc = val & 0xFC000000; | |
963 | break; | |
964 | case OCM0_DSACNTL: | |
965 | isacntl = val & 0xC0000000; | |
966 | break; | |
967 | } | |
968 | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); | |
969 | ocm->isarc = isarc; | |
970 | ocm->dsarc = dsarc; | |
971 | ocm->isacntl = isacntl; | |
972 | ocm->dsacntl = dsacntl; | |
973 | } | |
974 | ||
975 | static void ocm_reset (void *opaque) | |
976 | { | |
977 | ppc405_ocm_t *ocm; | |
978 | uint32_t isarc, dsarc, isacntl, dsacntl; | |
979 | ||
980 | ocm = opaque; | |
981 | isarc = 0x00000000; | |
982 | isacntl = 0x00000000; | |
983 | dsarc = 0x00000000; | |
984 | dsacntl = 0x00000000; | |
985 | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); | |
986 | ocm->isarc = isarc; | |
987 | ocm->dsarc = dsarc; | |
988 | ocm->isacntl = isacntl; | |
989 | ocm->dsacntl = dsacntl; | |
990 | } | |
991 | ||
802670e6 | 992 | static void ppc405_ocm_init(CPUState *env) |
8ecc7913 JM |
993 | { |
994 | ppc405_ocm_t *ocm; | |
995 | ||
996 | ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); | |
5c130f65 | 997 | ocm->offset = qemu_ram_alloc(4096); |
487414f1 | 998 | ocm_reset(ocm); |
a08d4367 | 999 | qemu_register_reset(&ocm_reset, ocm); |
487414f1 AL |
1000 | ppc_dcr_register(env, OCM0_ISARC, |
1001 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
1002 | ppc_dcr_register(env, OCM0_ISACNTL, | |
1003 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
1004 | ppc_dcr_register(env, OCM0_DSARC, | |
1005 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
1006 | ppc_dcr_register(env, OCM0_DSACNTL, | |
1007 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
8ecc7913 JM |
1008 | } |
1009 | ||
1010 | /*****************************************************************************/ | |
1011 | /* I2C controller */ | |
1012 | typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; | |
1013 | struct ppc4xx_i2c_t { | |
9c02f1a2 | 1014 | qemu_irq irq; |
8ecc7913 JM |
1015 | uint8_t mdata; |
1016 | uint8_t lmadr; | |
1017 | uint8_t hmadr; | |
1018 | uint8_t cntl; | |
1019 | uint8_t mdcntl; | |
1020 | uint8_t sts; | |
1021 | uint8_t extsts; | |
1022 | uint8_t sdata; | |
1023 | uint8_t lsadr; | |
1024 | uint8_t hsadr; | |
1025 | uint8_t clkdiv; | |
1026 | uint8_t intrmsk; | |
1027 | uint8_t xfrcnt; | |
1028 | uint8_t xtcntlss; | |
1029 | uint8_t directcntl; | |
1030 | }; | |
1031 | ||
1032 | static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) | |
1033 | { | |
1034 | ppc4xx_i2c_t *i2c; | |
1035 | uint32_t ret; | |
1036 | ||
1037 | #ifdef DEBUG_I2C | |
1038 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1039 | #endif | |
1040 | i2c = opaque; | |
802670e6 | 1041 | switch (addr) { |
8ecc7913 JM |
1042 | case 0x00: |
1043 | // i2c_readbyte(&i2c->mdata); | |
1044 | ret = i2c->mdata; | |
1045 | break; | |
1046 | case 0x02: | |
1047 | ret = i2c->sdata; | |
1048 | break; | |
1049 | case 0x04: | |
1050 | ret = i2c->lmadr; | |
1051 | break; | |
1052 | case 0x05: | |
1053 | ret = i2c->hmadr; | |
1054 | break; | |
1055 | case 0x06: | |
1056 | ret = i2c->cntl; | |
1057 | break; | |
1058 | case 0x07: | |
1059 | ret = i2c->mdcntl; | |
1060 | break; | |
1061 | case 0x08: | |
1062 | ret = i2c->sts; | |
1063 | break; | |
1064 | case 0x09: | |
1065 | ret = i2c->extsts; | |
1066 | break; | |
1067 | case 0x0A: | |
1068 | ret = i2c->lsadr; | |
1069 | break; | |
1070 | case 0x0B: | |
1071 | ret = i2c->hsadr; | |
1072 | break; | |
1073 | case 0x0C: | |
1074 | ret = i2c->clkdiv; | |
1075 | break; | |
1076 | case 0x0D: | |
1077 | ret = i2c->intrmsk; | |
1078 | break; | |
1079 | case 0x0E: | |
1080 | ret = i2c->xfrcnt; | |
1081 | break; | |
1082 | case 0x0F: | |
1083 | ret = i2c->xtcntlss; | |
1084 | break; | |
1085 | case 0x10: | |
1086 | ret = i2c->directcntl; | |
1087 | break; | |
1088 | default: | |
1089 | ret = 0x00; | |
1090 | break; | |
1091 | } | |
1092 | #ifdef DEBUG_I2C | |
aae9366a | 1093 | printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret); |
8ecc7913 JM |
1094 | #endif |
1095 | ||
1096 | return ret; | |
1097 | } | |
1098 | ||
1099 | static void ppc4xx_i2c_writeb (void *opaque, | |
1100 | target_phys_addr_t addr, uint32_t value) | |
1101 | { | |
1102 | ppc4xx_i2c_t *i2c; | |
1103 | ||
1104 | #ifdef DEBUG_I2C | |
aae9366a | 1105 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
1106 | #endif |
1107 | i2c = opaque; | |
802670e6 | 1108 | switch (addr) { |
8ecc7913 JM |
1109 | case 0x00: |
1110 | i2c->mdata = value; | |
1111 | // i2c_sendbyte(&i2c->mdata); | |
1112 | break; | |
1113 | case 0x02: | |
1114 | i2c->sdata = value; | |
1115 | break; | |
1116 | case 0x04: | |
1117 | i2c->lmadr = value; | |
1118 | break; | |
1119 | case 0x05: | |
1120 | i2c->hmadr = value; | |
1121 | break; | |
1122 | case 0x06: | |
1123 | i2c->cntl = value; | |
1124 | break; | |
1125 | case 0x07: | |
1126 | i2c->mdcntl = value & 0xDF; | |
1127 | break; | |
1128 | case 0x08: | |
1129 | i2c->sts &= ~(value & 0x0A); | |
1130 | break; | |
1131 | case 0x09: | |
1132 | i2c->extsts &= ~(value & 0x8F); | |
1133 | break; | |
1134 | case 0x0A: | |
1135 | i2c->lsadr = value; | |
1136 | break; | |
1137 | case 0x0B: | |
1138 | i2c->hsadr = value; | |
1139 | break; | |
1140 | case 0x0C: | |
1141 | i2c->clkdiv = value; | |
1142 | break; | |
1143 | case 0x0D: | |
1144 | i2c->intrmsk = value; | |
1145 | break; | |
1146 | case 0x0E: | |
1147 | i2c->xfrcnt = value & 0x77; | |
1148 | break; | |
1149 | case 0x0F: | |
1150 | i2c->xtcntlss = value; | |
1151 | break; | |
1152 | case 0x10: | |
1153 | i2c->directcntl = value & 0x7; | |
1154 | break; | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) | |
1159 | { | |
1160 | uint32_t ret; | |
1161 | ||
1162 | #ifdef DEBUG_I2C | |
1163 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1164 | #endif | |
1165 | ret = ppc4xx_i2c_readb(opaque, addr) << 8; | |
1166 | ret |= ppc4xx_i2c_readb(opaque, addr + 1); | |
1167 | ||
1168 | return ret; | |
1169 | } | |
1170 | ||
1171 | static void ppc4xx_i2c_writew (void *opaque, | |
1172 | target_phys_addr_t addr, uint32_t value) | |
1173 | { | |
1174 | #ifdef DEBUG_I2C | |
aae9366a | 1175 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
1176 | #endif |
1177 | ppc4xx_i2c_writeb(opaque, addr, value >> 8); | |
1178 | ppc4xx_i2c_writeb(opaque, addr + 1, value); | |
1179 | } | |
1180 | ||
1181 | static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) | |
1182 | { | |
1183 | uint32_t ret; | |
1184 | ||
1185 | #ifdef DEBUG_I2C | |
1186 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1187 | #endif | |
1188 | ret = ppc4xx_i2c_readb(opaque, addr) << 24; | |
1189 | ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; | |
1190 | ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; | |
1191 | ret |= ppc4xx_i2c_readb(opaque, addr + 3); | |
1192 | ||
1193 | return ret; | |
1194 | } | |
1195 | ||
1196 | static void ppc4xx_i2c_writel (void *opaque, | |
1197 | target_phys_addr_t addr, uint32_t value) | |
1198 | { | |
1199 | #ifdef DEBUG_I2C | |
aae9366a | 1200 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
8ecc7913 JM |
1201 | #endif |
1202 | ppc4xx_i2c_writeb(opaque, addr, value >> 24); | |
1203 | ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); | |
1204 | ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); | |
1205 | ppc4xx_i2c_writeb(opaque, addr + 3, value); | |
1206 | } | |
1207 | ||
1208 | static CPUReadMemoryFunc *i2c_read[] = { | |
1209 | &ppc4xx_i2c_readb, | |
1210 | &ppc4xx_i2c_readw, | |
1211 | &ppc4xx_i2c_readl, | |
1212 | }; | |
1213 | ||
1214 | static CPUWriteMemoryFunc *i2c_write[] = { | |
1215 | &ppc4xx_i2c_writeb, | |
1216 | &ppc4xx_i2c_writew, | |
1217 | &ppc4xx_i2c_writel, | |
1218 | }; | |
1219 | ||
1220 | static void ppc4xx_i2c_reset (void *opaque) | |
1221 | { | |
1222 | ppc4xx_i2c_t *i2c; | |
1223 | ||
1224 | i2c = opaque; | |
1225 | i2c->mdata = 0x00; | |
1226 | i2c->sdata = 0x00; | |
1227 | i2c->cntl = 0x00; | |
1228 | i2c->mdcntl = 0x00; | |
1229 | i2c->sts = 0x00; | |
1230 | i2c->extsts = 0x00; | |
1231 | i2c->clkdiv = 0x00; | |
1232 | i2c->xfrcnt = 0x00; | |
1233 | i2c->directcntl = 0x0F; | |
1234 | } | |
1235 | ||
802670e6 | 1236 | static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) |
8ecc7913 JM |
1237 | { |
1238 | ppc4xx_i2c_t *i2c; | |
802670e6 | 1239 | int io; |
8ecc7913 JM |
1240 | |
1241 | i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t)); | |
487414f1 | 1242 | i2c->irq = irq; |
8ecc7913 | 1243 | #ifdef DEBUG_I2C |
802670e6 | 1244 | printf("%s: offset " PADDRX "\n", __func__, base); |
8ecc7913 | 1245 | #endif |
802670e6 BS |
1246 | io = cpu_register_io_memory(i2c_read, i2c_write, i2c); |
1247 | cpu_register_physical_memory(base, 0x011, io); | |
1248 | ppc4xx_i2c_reset(i2c); | |
a08d4367 | 1249 | qemu_register_reset(ppc4xx_i2c_reset, i2c); |
8ecc7913 JM |
1250 | } |
1251 | ||
9c02f1a2 JM |
1252 | /*****************************************************************************/ |
1253 | /* General purpose timers */ | |
1254 | typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; | |
1255 | struct ppc4xx_gpt_t { | |
9c02f1a2 JM |
1256 | int64_t tb_offset; |
1257 | uint32_t tb_freq; | |
1258 | struct QEMUTimer *timer; | |
1259 | qemu_irq irqs[5]; | |
1260 | uint32_t oe; | |
1261 | uint32_t ol; | |
1262 | uint32_t im; | |
1263 | uint32_t is; | |
1264 | uint32_t ie; | |
1265 | uint32_t comp[5]; | |
1266 | uint32_t mask[5]; | |
1267 | }; | |
1268 | ||
1269 | static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) | |
1270 | { | |
1271 | #ifdef DEBUG_GPT | |
1272 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1273 | #endif | |
1274 | /* XXX: generate a bus fault */ | |
1275 | return -1; | |
1276 | } | |
1277 | ||
1278 | static void ppc4xx_gpt_writeb (void *opaque, | |
1279 | target_phys_addr_t addr, uint32_t value) | |
1280 | { | |
1281 | #ifdef DEBUG_I2C | |
aae9366a | 1282 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
9c02f1a2 JM |
1283 | #endif |
1284 | /* XXX: generate a bus fault */ | |
1285 | } | |
1286 | ||
1287 | static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) | |
1288 | { | |
1289 | #ifdef DEBUG_GPT | |
1290 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1291 | #endif | |
1292 | /* XXX: generate a bus fault */ | |
1293 | return -1; | |
1294 | } | |
1295 | ||
1296 | static void ppc4xx_gpt_writew (void *opaque, | |
1297 | target_phys_addr_t addr, uint32_t value) | |
1298 | { | |
1299 | #ifdef DEBUG_I2C | |
aae9366a | 1300 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
9c02f1a2 JM |
1301 | #endif |
1302 | /* XXX: generate a bus fault */ | |
1303 | } | |
1304 | ||
1305 | static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) | |
1306 | { | |
1307 | /* XXX: TODO */ | |
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) | |
1312 | { | |
1313 | /* XXX: TODO */ | |
1314 | } | |
1315 | ||
1316 | static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) | |
1317 | { | |
1318 | uint32_t mask; | |
1319 | int i; | |
1320 | ||
1321 | mask = 0x80000000; | |
1322 | for (i = 0; i < 5; i++) { | |
1323 | if (gpt->oe & mask) { | |
1324 | /* Output is enabled */ | |
1325 | if (ppc4xx_gpt_compare(gpt, i)) { | |
1326 | /* Comparison is OK */ | |
1327 | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); | |
1328 | } else { | |
1329 | /* Comparison is KO */ | |
1330 | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); | |
1331 | } | |
1332 | } | |
1333 | mask = mask >> 1; | |
1334 | } | |
9c02f1a2 JM |
1335 | } |
1336 | ||
1337 | static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) | |
1338 | { | |
1339 | uint32_t mask; | |
1340 | int i; | |
1341 | ||
1342 | mask = 0x00008000; | |
1343 | for (i = 0; i < 5; i++) { | |
1344 | if (gpt->is & gpt->im & mask) | |
1345 | qemu_irq_raise(gpt->irqs[i]); | |
1346 | else | |
1347 | qemu_irq_lower(gpt->irqs[i]); | |
1348 | mask = mask >> 1; | |
1349 | } | |
9c02f1a2 JM |
1350 | } |
1351 | ||
1352 | static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) | |
1353 | { | |
1354 | /* XXX: TODO */ | |
1355 | } | |
1356 | ||
1357 | static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) | |
1358 | { | |
1359 | ppc4xx_gpt_t *gpt; | |
1360 | uint32_t ret; | |
1361 | int idx; | |
1362 | ||
1363 | #ifdef DEBUG_GPT | |
1364 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1365 | #endif | |
1366 | gpt = opaque; | |
802670e6 | 1367 | switch (addr) { |
9c02f1a2 JM |
1368 | case 0x00: |
1369 | /* Time base counter */ | |
1370 | ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, | |
1371 | gpt->tb_freq, ticks_per_sec); | |
1372 | break; | |
1373 | case 0x10: | |
1374 | /* Output enable */ | |
1375 | ret = gpt->oe; | |
1376 | break; | |
1377 | case 0x14: | |
1378 | /* Output level */ | |
1379 | ret = gpt->ol; | |
1380 | break; | |
1381 | case 0x18: | |
1382 | /* Interrupt mask */ | |
1383 | ret = gpt->im; | |
1384 | break; | |
1385 | case 0x1C: | |
1386 | case 0x20: | |
1387 | /* Interrupt status */ | |
1388 | ret = gpt->is; | |
1389 | break; | |
1390 | case 0x24: | |
1391 | /* Interrupt enable */ | |
1392 | ret = gpt->ie; | |
1393 | break; | |
1394 | case 0x80 ... 0x90: | |
1395 | /* Compare timer */ | |
802670e6 | 1396 | idx = (addr - 0x80) >> 2; |
9c02f1a2 JM |
1397 | ret = gpt->comp[idx]; |
1398 | break; | |
1399 | case 0xC0 ... 0xD0: | |
1400 | /* Compare mask */ | |
802670e6 | 1401 | idx = (addr - 0xC0) >> 2; |
9c02f1a2 JM |
1402 | ret = gpt->mask[idx]; |
1403 | break; | |
1404 | default: | |
1405 | ret = -1; | |
1406 | break; | |
1407 | } | |
1408 | ||
1409 | return ret; | |
1410 | } | |
1411 | ||
1412 | static void ppc4xx_gpt_writel (void *opaque, | |
1413 | target_phys_addr_t addr, uint32_t value) | |
1414 | { | |
1415 | ppc4xx_gpt_t *gpt; | |
1416 | int idx; | |
1417 | ||
1418 | #ifdef DEBUG_I2C | |
aae9366a | 1419 | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
9c02f1a2 JM |
1420 | #endif |
1421 | gpt = opaque; | |
802670e6 | 1422 | switch (addr) { |
9c02f1a2 JM |
1423 | case 0x00: |
1424 | /* Time base counter */ | |
1425 | gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) | |
1426 | - qemu_get_clock(vm_clock); | |
1427 | ppc4xx_gpt_compute_timer(gpt); | |
1428 | break; | |
1429 | case 0x10: | |
1430 | /* Output enable */ | |
1431 | gpt->oe = value & 0xF8000000; | |
1432 | ppc4xx_gpt_set_outputs(gpt); | |
1433 | break; | |
1434 | case 0x14: | |
1435 | /* Output level */ | |
1436 | gpt->ol = value & 0xF8000000; | |
1437 | ppc4xx_gpt_set_outputs(gpt); | |
1438 | break; | |
1439 | case 0x18: | |
1440 | /* Interrupt mask */ | |
1441 | gpt->im = value & 0x0000F800; | |
1442 | break; | |
1443 | case 0x1C: | |
1444 | /* Interrupt status set */ | |
1445 | gpt->is |= value & 0x0000F800; | |
1446 | ppc4xx_gpt_set_irqs(gpt); | |
1447 | break; | |
1448 | case 0x20: | |
1449 | /* Interrupt status clear */ | |
1450 | gpt->is &= ~(value & 0x0000F800); | |
1451 | ppc4xx_gpt_set_irqs(gpt); | |
1452 | break; | |
1453 | case 0x24: | |
1454 | /* Interrupt enable */ | |
1455 | gpt->ie = value & 0x0000F800; | |
1456 | ppc4xx_gpt_set_irqs(gpt); | |
1457 | break; | |
1458 | case 0x80 ... 0x90: | |
1459 | /* Compare timer */ | |
802670e6 | 1460 | idx = (addr - 0x80) >> 2; |
9c02f1a2 JM |
1461 | gpt->comp[idx] = value & 0xF8000000; |
1462 | ppc4xx_gpt_compute_timer(gpt); | |
1463 | break; | |
1464 | case 0xC0 ... 0xD0: | |
1465 | /* Compare mask */ | |
802670e6 | 1466 | idx = (addr - 0xC0) >> 2; |
9c02f1a2 JM |
1467 | gpt->mask[idx] = value & 0xF8000000; |
1468 | ppc4xx_gpt_compute_timer(gpt); | |
1469 | break; | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | static CPUReadMemoryFunc *gpt_read[] = { | |
1474 | &ppc4xx_gpt_readb, | |
1475 | &ppc4xx_gpt_readw, | |
1476 | &ppc4xx_gpt_readl, | |
1477 | }; | |
1478 | ||
1479 | static CPUWriteMemoryFunc *gpt_write[] = { | |
1480 | &ppc4xx_gpt_writeb, | |
1481 | &ppc4xx_gpt_writew, | |
1482 | &ppc4xx_gpt_writel, | |
1483 | }; | |
1484 | ||
1485 | static void ppc4xx_gpt_cb (void *opaque) | |
1486 | { | |
1487 | ppc4xx_gpt_t *gpt; | |
1488 | ||
1489 | gpt = opaque; | |
1490 | ppc4xx_gpt_set_irqs(gpt); | |
1491 | ppc4xx_gpt_set_outputs(gpt); | |
1492 | ppc4xx_gpt_compute_timer(gpt); | |
1493 | } | |
1494 | ||
1495 | static void ppc4xx_gpt_reset (void *opaque) | |
1496 | { | |
1497 | ppc4xx_gpt_t *gpt; | |
1498 | int i; | |
1499 | ||
1500 | gpt = opaque; | |
1501 | qemu_del_timer(gpt->timer); | |
1502 | gpt->oe = 0x00000000; | |
1503 | gpt->ol = 0x00000000; | |
1504 | gpt->im = 0x00000000; | |
1505 | gpt->is = 0x00000000; | |
1506 | gpt->ie = 0x00000000; | |
1507 | for (i = 0; i < 5; i++) { | |
1508 | gpt->comp[i] = 0x00000000; | |
1509 | gpt->mask[i] = 0x00000000; | |
1510 | } | |
1511 | } | |
1512 | ||
802670e6 | 1513 | static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) |
9c02f1a2 JM |
1514 | { |
1515 | ppc4xx_gpt_t *gpt; | |
1516 | int i; | |
802670e6 | 1517 | int io; |
9c02f1a2 JM |
1518 | |
1519 | gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t)); | |
802670e6 | 1520 | for (i = 0; i < 5; i++) { |
487414f1 | 1521 | gpt->irqs[i] = irqs[i]; |
802670e6 | 1522 | } |
487414f1 | 1523 | gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
9c02f1a2 | 1524 | #ifdef DEBUG_GPT |
802670e6 | 1525 | printf("%s: offset " PADDRX "\n", __func__, base); |
9c02f1a2 | 1526 | #endif |
802670e6 BS |
1527 | io = cpu_register_io_memory(gpt_read, gpt_write, gpt); |
1528 | cpu_register_physical_memory(base, 0x0d4, io); | |
a08d4367 | 1529 | qemu_register_reset(ppc4xx_gpt_reset, gpt); |
802670e6 | 1530 | ppc4xx_gpt_reset(gpt); |
9c02f1a2 JM |
1531 | } |
1532 | ||
1533 | /*****************************************************************************/ | |
1534 | /* MAL */ | |
1535 | enum { | |
1536 | MAL0_CFG = 0x180, | |
1537 | MAL0_ESR = 0x181, | |
1538 | MAL0_IER = 0x182, | |
1539 | MAL0_TXCASR = 0x184, | |
1540 | MAL0_TXCARR = 0x185, | |
1541 | MAL0_TXEOBISR = 0x186, | |
1542 | MAL0_TXDEIR = 0x187, | |
1543 | MAL0_RXCASR = 0x190, | |
1544 | MAL0_RXCARR = 0x191, | |
1545 | MAL0_RXEOBISR = 0x192, | |
1546 | MAL0_RXDEIR = 0x193, | |
1547 | MAL0_TXCTP0R = 0x1A0, | |
1548 | MAL0_TXCTP1R = 0x1A1, | |
1549 | MAL0_TXCTP2R = 0x1A2, | |
1550 | MAL0_TXCTP3R = 0x1A3, | |
1551 | MAL0_RXCTP0R = 0x1C0, | |
1552 | MAL0_RXCTP1R = 0x1C1, | |
1553 | MAL0_RCBS0 = 0x1E0, | |
1554 | MAL0_RCBS1 = 0x1E1, | |
1555 | }; | |
1556 | ||
1557 | typedef struct ppc40x_mal_t ppc40x_mal_t; | |
1558 | struct ppc40x_mal_t { | |
1559 | qemu_irq irqs[4]; | |
1560 | uint32_t cfg; | |
1561 | uint32_t esr; | |
1562 | uint32_t ier; | |
1563 | uint32_t txcasr; | |
1564 | uint32_t txcarr; | |
1565 | uint32_t txeobisr; | |
1566 | uint32_t txdeir; | |
1567 | uint32_t rxcasr; | |
1568 | uint32_t rxcarr; | |
1569 | uint32_t rxeobisr; | |
1570 | uint32_t rxdeir; | |
1571 | uint32_t txctpr[4]; | |
1572 | uint32_t rxctpr[2]; | |
1573 | uint32_t rcbs[2]; | |
1574 | }; | |
1575 | ||
1576 | static void ppc40x_mal_reset (void *opaque); | |
1577 | ||
1578 | static target_ulong dcr_read_mal (void *opaque, int dcrn) | |
1579 | { | |
1580 | ppc40x_mal_t *mal; | |
1581 | target_ulong ret; | |
1582 | ||
1583 | mal = opaque; | |
1584 | switch (dcrn) { | |
1585 | case MAL0_CFG: | |
1586 | ret = mal->cfg; | |
1587 | break; | |
1588 | case MAL0_ESR: | |
1589 | ret = mal->esr; | |
1590 | break; | |
1591 | case MAL0_IER: | |
1592 | ret = mal->ier; | |
1593 | break; | |
1594 | case MAL0_TXCASR: | |
1595 | ret = mal->txcasr; | |
1596 | break; | |
1597 | case MAL0_TXCARR: | |
1598 | ret = mal->txcarr; | |
1599 | break; | |
1600 | case MAL0_TXEOBISR: | |
1601 | ret = mal->txeobisr; | |
1602 | break; | |
1603 | case MAL0_TXDEIR: | |
1604 | ret = mal->txdeir; | |
1605 | break; | |
1606 | case MAL0_RXCASR: | |
1607 | ret = mal->rxcasr; | |
1608 | break; | |
1609 | case MAL0_RXCARR: | |
1610 | ret = mal->rxcarr; | |
1611 | break; | |
1612 | case MAL0_RXEOBISR: | |
1613 | ret = mal->rxeobisr; | |
1614 | break; | |
1615 | case MAL0_RXDEIR: | |
1616 | ret = mal->rxdeir; | |
1617 | break; | |
1618 | case MAL0_TXCTP0R: | |
1619 | ret = mal->txctpr[0]; | |
1620 | break; | |
1621 | case MAL0_TXCTP1R: | |
1622 | ret = mal->txctpr[1]; | |
1623 | break; | |
1624 | case MAL0_TXCTP2R: | |
1625 | ret = mal->txctpr[2]; | |
1626 | break; | |
1627 | case MAL0_TXCTP3R: | |
1628 | ret = mal->txctpr[3]; | |
1629 | break; | |
1630 | case MAL0_RXCTP0R: | |
1631 | ret = mal->rxctpr[0]; | |
1632 | break; | |
1633 | case MAL0_RXCTP1R: | |
1634 | ret = mal->rxctpr[1]; | |
1635 | break; | |
1636 | case MAL0_RCBS0: | |
1637 | ret = mal->rcbs[0]; | |
1638 | break; | |
1639 | case MAL0_RCBS1: | |
1640 | ret = mal->rcbs[1]; | |
1641 | break; | |
1642 | default: | |
1643 | ret = 0; | |
1644 | break; | |
1645 | } | |
1646 | ||
1647 | return ret; | |
1648 | } | |
1649 | ||
1650 | static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) | |
1651 | { | |
1652 | ppc40x_mal_t *mal; | |
1653 | int idx; | |
1654 | ||
1655 | mal = opaque; | |
1656 | switch (dcrn) { | |
1657 | case MAL0_CFG: | |
1658 | if (val & 0x80000000) | |
1659 | ppc40x_mal_reset(mal); | |
1660 | mal->cfg = val & 0x00FFC087; | |
1661 | break; | |
1662 | case MAL0_ESR: | |
1663 | /* Read/clear */ | |
1664 | mal->esr &= ~val; | |
1665 | break; | |
1666 | case MAL0_IER: | |
1667 | mal->ier = val & 0x0000001F; | |
1668 | break; | |
1669 | case MAL0_TXCASR: | |
1670 | mal->txcasr = val & 0xF0000000; | |
1671 | break; | |
1672 | case MAL0_TXCARR: | |
1673 | mal->txcarr = val & 0xF0000000; | |
1674 | break; | |
1675 | case MAL0_TXEOBISR: | |
1676 | /* Read/clear */ | |
1677 | mal->txeobisr &= ~val; | |
1678 | break; | |
1679 | case MAL0_TXDEIR: | |
1680 | /* Read/clear */ | |
1681 | mal->txdeir &= ~val; | |
1682 | break; | |
1683 | case MAL0_RXCASR: | |
1684 | mal->rxcasr = val & 0xC0000000; | |
1685 | break; | |
1686 | case MAL0_RXCARR: | |
1687 | mal->rxcarr = val & 0xC0000000; | |
1688 | break; | |
1689 | case MAL0_RXEOBISR: | |
1690 | /* Read/clear */ | |
1691 | mal->rxeobisr &= ~val; | |
1692 | break; | |
1693 | case MAL0_RXDEIR: | |
1694 | /* Read/clear */ | |
1695 | mal->rxdeir &= ~val; | |
1696 | break; | |
1697 | case MAL0_TXCTP0R: | |
1698 | idx = 0; | |
1699 | goto update_tx_ptr; | |
1700 | case MAL0_TXCTP1R: | |
1701 | idx = 1; | |
1702 | goto update_tx_ptr; | |
1703 | case MAL0_TXCTP2R: | |
1704 | idx = 2; | |
1705 | goto update_tx_ptr; | |
1706 | case MAL0_TXCTP3R: | |
1707 | idx = 3; | |
1708 | update_tx_ptr: | |
1709 | mal->txctpr[idx] = val; | |
1710 | break; | |
1711 | case MAL0_RXCTP0R: | |
1712 | idx = 0; | |
1713 | goto update_rx_ptr; | |
1714 | case MAL0_RXCTP1R: | |
1715 | idx = 1; | |
1716 | update_rx_ptr: | |
1717 | mal->rxctpr[idx] = val; | |
1718 | break; | |
1719 | case MAL0_RCBS0: | |
1720 | idx = 0; | |
1721 | goto update_rx_size; | |
1722 | case MAL0_RCBS1: | |
1723 | idx = 1; | |
1724 | update_rx_size: | |
1725 | mal->rcbs[idx] = val & 0x000000FF; | |
1726 | break; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | static void ppc40x_mal_reset (void *opaque) | |
1731 | { | |
1732 | ppc40x_mal_t *mal; | |
1733 | ||
1734 | mal = opaque; | |
1735 | mal->cfg = 0x0007C000; | |
1736 | mal->esr = 0x00000000; | |
1737 | mal->ier = 0x00000000; | |
1738 | mal->rxcasr = 0x00000000; | |
1739 | mal->rxdeir = 0x00000000; | |
1740 | mal->rxeobisr = 0x00000000; | |
1741 | mal->txcasr = 0x00000000; | |
1742 | mal->txdeir = 0x00000000; | |
1743 | mal->txeobisr = 0x00000000; | |
1744 | } | |
1745 | ||
802670e6 | 1746 | static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) |
9c02f1a2 JM |
1747 | { |
1748 | ppc40x_mal_t *mal; | |
1749 | int i; | |
1750 | ||
1751 | mal = qemu_mallocz(sizeof(ppc40x_mal_t)); | |
487414f1 AL |
1752 | for (i = 0; i < 4; i++) |
1753 | mal->irqs[i] = irqs[i]; | |
1754 | ppc40x_mal_reset(mal); | |
a08d4367 | 1755 | qemu_register_reset(&ppc40x_mal_reset, mal); |
487414f1 AL |
1756 | ppc_dcr_register(env, MAL0_CFG, |
1757 | mal, &dcr_read_mal, &dcr_write_mal); | |
1758 | ppc_dcr_register(env, MAL0_ESR, | |
1759 | mal, &dcr_read_mal, &dcr_write_mal); | |
1760 | ppc_dcr_register(env, MAL0_IER, | |
1761 | mal, &dcr_read_mal, &dcr_write_mal); | |
1762 | ppc_dcr_register(env, MAL0_TXCASR, | |
1763 | mal, &dcr_read_mal, &dcr_write_mal); | |
1764 | ppc_dcr_register(env, MAL0_TXCARR, | |
1765 | mal, &dcr_read_mal, &dcr_write_mal); | |
1766 | ppc_dcr_register(env, MAL0_TXEOBISR, | |
1767 | mal, &dcr_read_mal, &dcr_write_mal); | |
1768 | ppc_dcr_register(env, MAL0_TXDEIR, | |
1769 | mal, &dcr_read_mal, &dcr_write_mal); | |
1770 | ppc_dcr_register(env, MAL0_RXCASR, | |
1771 | mal, &dcr_read_mal, &dcr_write_mal); | |
1772 | ppc_dcr_register(env, MAL0_RXCARR, | |
1773 | mal, &dcr_read_mal, &dcr_write_mal); | |
1774 | ppc_dcr_register(env, MAL0_RXEOBISR, | |
1775 | mal, &dcr_read_mal, &dcr_write_mal); | |
1776 | ppc_dcr_register(env, MAL0_RXDEIR, | |
1777 | mal, &dcr_read_mal, &dcr_write_mal); | |
1778 | ppc_dcr_register(env, MAL0_TXCTP0R, | |
1779 | mal, &dcr_read_mal, &dcr_write_mal); | |
1780 | ppc_dcr_register(env, MAL0_TXCTP1R, | |
1781 | mal, &dcr_read_mal, &dcr_write_mal); | |
1782 | ppc_dcr_register(env, MAL0_TXCTP2R, | |
1783 | mal, &dcr_read_mal, &dcr_write_mal); | |
1784 | ppc_dcr_register(env, MAL0_TXCTP3R, | |
1785 | mal, &dcr_read_mal, &dcr_write_mal); | |
1786 | ppc_dcr_register(env, MAL0_RXCTP0R, | |
1787 | mal, &dcr_read_mal, &dcr_write_mal); | |
1788 | ppc_dcr_register(env, MAL0_RXCTP1R, | |
1789 | mal, &dcr_read_mal, &dcr_write_mal); | |
1790 | ppc_dcr_register(env, MAL0_RCBS0, | |
1791 | mal, &dcr_read_mal, &dcr_write_mal); | |
1792 | ppc_dcr_register(env, MAL0_RCBS1, | |
1793 | mal, &dcr_read_mal, &dcr_write_mal); | |
9c02f1a2 JM |
1794 | } |
1795 | ||
8ecc7913 JM |
1796 | /*****************************************************************************/ |
1797 | /* SPR */ | |
1798 | void ppc40x_core_reset (CPUState *env) | |
1799 | { | |
1800 | target_ulong dbsr; | |
1801 | ||
1802 | printf("Reset PowerPC core\n"); | |
ef397e88 JM |
1803 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1804 | /* XXX: TOFIX */ | |
1805 | #if 0 | |
8ecc7913 | 1806 | cpu_ppc_reset(env); |
ef397e88 JM |
1807 | #else |
1808 | qemu_system_reset_request(); | |
1809 | #endif | |
8ecc7913 JM |
1810 | dbsr = env->spr[SPR_40x_DBSR]; |
1811 | dbsr &= ~0x00000300; | |
1812 | dbsr |= 0x00000100; | |
1813 | env->spr[SPR_40x_DBSR] = dbsr; | |
8ecc7913 JM |
1814 | } |
1815 | ||
1816 | void ppc40x_chip_reset (CPUState *env) | |
1817 | { | |
1818 | target_ulong dbsr; | |
1819 | ||
1820 | printf("Reset PowerPC chip\n"); | |
ef397e88 JM |
1821 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1822 | /* XXX: TOFIX */ | |
1823 | #if 0 | |
8ecc7913 | 1824 | cpu_ppc_reset(env); |
ef397e88 JM |
1825 | #else |
1826 | qemu_system_reset_request(); | |
1827 | #endif | |
8ecc7913 JM |
1828 | /* XXX: TODO reset all internal peripherals */ |
1829 | dbsr = env->spr[SPR_40x_DBSR]; | |
1830 | dbsr &= ~0x00000300; | |
04f20795 | 1831 | dbsr |= 0x00000200; |
8ecc7913 | 1832 | env->spr[SPR_40x_DBSR] = dbsr; |
8ecc7913 JM |
1833 | } |
1834 | ||
1835 | void ppc40x_system_reset (CPUState *env) | |
1836 | { | |
1837 | printf("Reset PowerPC system\n"); | |
1838 | qemu_system_reset_request(); | |
1839 | } | |
1840 | ||
1841 | void store_40x_dbcr0 (CPUState *env, uint32_t val) | |
1842 | { | |
1843 | switch ((val >> 28) & 0x3) { | |
1844 | case 0x0: | |
1845 | /* No action */ | |
1846 | break; | |
1847 | case 0x1: | |
1848 | /* Core reset */ | |
1849 | ppc40x_core_reset(env); | |
1850 | break; | |
1851 | case 0x2: | |
1852 | /* Chip reset */ | |
1853 | ppc40x_chip_reset(env); | |
1854 | break; | |
1855 | case 0x3: | |
1856 | /* System reset */ | |
1857 | ppc40x_system_reset(env); | |
1858 | break; | |
1859 | } | |
1860 | } | |
1861 | ||
1862 | /*****************************************************************************/ | |
1863 | /* PowerPC 405CR */ | |
1864 | enum { | |
1865 | PPC405CR_CPC0_PLLMR = 0x0B0, | |
1866 | PPC405CR_CPC0_CR0 = 0x0B1, | |
1867 | PPC405CR_CPC0_CR1 = 0x0B2, | |
1868 | PPC405CR_CPC0_PSR = 0x0B4, | |
1869 | PPC405CR_CPC0_JTAGID = 0x0B5, | |
1870 | PPC405CR_CPC0_ER = 0x0B9, | |
1871 | PPC405CR_CPC0_FR = 0x0BA, | |
1872 | PPC405CR_CPC0_SR = 0x0BB, | |
1873 | }; | |
1874 | ||
04f20795 JM |
1875 | enum { |
1876 | PPC405CR_CPU_CLK = 0, | |
1877 | PPC405CR_TMR_CLK = 1, | |
1878 | PPC405CR_PLB_CLK = 2, | |
1879 | PPC405CR_SDRAM_CLK = 3, | |
1880 | PPC405CR_OPB_CLK = 4, | |
1881 | PPC405CR_EXT_CLK = 5, | |
1882 | PPC405CR_UART_CLK = 6, | |
1883 | PPC405CR_CLK_NB = 7, | |
1884 | }; | |
1885 | ||
8ecc7913 JM |
1886 | typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
1887 | struct ppc405cr_cpc_t { | |
04f20795 | 1888 | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
8ecc7913 JM |
1889 | uint32_t sysclk; |
1890 | uint32_t psr; | |
1891 | uint32_t cr0; | |
1892 | uint32_t cr1; | |
1893 | uint32_t jtagid; | |
1894 | uint32_t pllmr; | |
1895 | uint32_t er; | |
1896 | uint32_t fr; | |
1897 | }; | |
1898 | ||
1899 | static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) | |
1900 | { | |
1901 | uint64_t VCO_out, PLL_out; | |
1902 | uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; | |
1903 | int M, D0, D1, D2; | |
1904 | ||
1905 | D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ | |
1906 | if (cpc->pllmr & 0x80000000) { | |
1907 | D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ | |
1908 | D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ | |
1909 | M = D0 * D1 * D2; | |
1910 | VCO_out = cpc->sysclk * M; | |
1911 | if (VCO_out < 400000000 || VCO_out > 800000000) { | |
1912 | /* PLL cannot lock */ | |
1913 | cpc->pllmr &= ~0x80000000; | |
1914 | goto bypass_pll; | |
1915 | } | |
1916 | PLL_out = VCO_out / D2; | |
1917 | } else { | |
1918 | /* Bypass PLL */ | |
1919 | bypass_pll: | |
1920 | M = D0; | |
1921 | PLL_out = cpc->sysclk * M; | |
1922 | } | |
1923 | CPU_clk = PLL_out; | |
1924 | if (cpc->cr1 & 0x00800000) | |
1925 | TMR_clk = cpc->sysclk; /* Should have a separate clock */ | |
1926 | else | |
1927 | TMR_clk = CPU_clk; | |
1928 | PLB_clk = CPU_clk / D0; | |
1929 | SDRAM_clk = PLB_clk; | |
1930 | D0 = ((cpc->pllmr >> 10) & 0x3) + 1; | |
1931 | OPB_clk = PLB_clk / D0; | |
1932 | D0 = ((cpc->pllmr >> 24) & 0x3) + 2; | |
1933 | EXT_clk = PLB_clk / D0; | |
1934 | D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; | |
1935 | UART_clk = CPU_clk / D0; | |
1936 | /* Setup CPU clocks */ | |
04f20795 | 1937 | clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
8ecc7913 | 1938 | /* Setup time-base clock */ |
04f20795 | 1939 | clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
8ecc7913 | 1940 | /* Setup PLB clock */ |
04f20795 | 1941 | clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
8ecc7913 | 1942 | /* Setup SDRAM clock */ |
04f20795 | 1943 | clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
8ecc7913 | 1944 | /* Setup OPB clock */ |
04f20795 | 1945 | clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
8ecc7913 | 1946 | /* Setup external clock */ |
04f20795 | 1947 | clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
8ecc7913 | 1948 | /* Setup UART clock */ |
04f20795 | 1949 | clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
8ecc7913 JM |
1950 | } |
1951 | ||
1952 | static target_ulong dcr_read_crcpc (void *opaque, int dcrn) | |
1953 | { | |
1954 | ppc405cr_cpc_t *cpc; | |
1955 | target_ulong ret; | |
1956 | ||
1957 | cpc = opaque; | |
1958 | switch (dcrn) { | |
1959 | case PPC405CR_CPC0_PLLMR: | |
1960 | ret = cpc->pllmr; | |
1961 | break; | |
1962 | case PPC405CR_CPC0_CR0: | |
1963 | ret = cpc->cr0; | |
1964 | break; | |
1965 | case PPC405CR_CPC0_CR1: | |
1966 | ret = cpc->cr1; | |
1967 | break; | |
1968 | case PPC405CR_CPC0_PSR: | |
1969 | ret = cpc->psr; | |
1970 | break; | |
1971 | case PPC405CR_CPC0_JTAGID: | |
1972 | ret = cpc->jtagid; | |
1973 | break; | |
1974 | case PPC405CR_CPC0_ER: | |
1975 | ret = cpc->er; | |
1976 | break; | |
1977 | case PPC405CR_CPC0_FR: | |
1978 | ret = cpc->fr; | |
1979 | break; | |
1980 | case PPC405CR_CPC0_SR: | |
1981 | ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; | |
1982 | break; | |
1983 | default: | |
1984 | /* Avoid gcc warning */ | |
1985 | ret = 0; | |
1986 | break; | |
1987 | } | |
1988 | ||
1989 | return ret; | |
1990 | } | |
1991 | ||
1992 | static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) | |
1993 | { | |
1994 | ppc405cr_cpc_t *cpc; | |
1995 | ||
1996 | cpc = opaque; | |
1997 | switch (dcrn) { | |
1998 | case PPC405CR_CPC0_PLLMR: | |
1999 | cpc->pllmr = val & 0xFFF77C3F; | |
2000 | break; | |
2001 | case PPC405CR_CPC0_CR0: | |
2002 | cpc->cr0 = val & 0x0FFFFFFE; | |
2003 | break; | |
2004 | case PPC405CR_CPC0_CR1: | |
2005 | cpc->cr1 = val & 0x00800000; | |
2006 | break; | |
2007 | case PPC405CR_CPC0_PSR: | |
2008 | /* Read-only */ | |
2009 | break; | |
2010 | case PPC405CR_CPC0_JTAGID: | |
2011 | /* Read-only */ | |
2012 | break; | |
2013 | case PPC405CR_CPC0_ER: | |
2014 | cpc->er = val & 0xBFFC0000; | |
2015 | break; | |
2016 | case PPC405CR_CPC0_FR: | |
2017 | cpc->fr = val & 0xBFFC0000; | |
2018 | break; | |
2019 | case PPC405CR_CPC0_SR: | |
2020 | /* Read-only */ | |
2021 | break; | |
2022 | } | |
2023 | } | |
2024 | ||
2025 | static void ppc405cr_cpc_reset (void *opaque) | |
2026 | { | |
2027 | ppc405cr_cpc_t *cpc; | |
2028 | int D; | |
2029 | ||
2030 | cpc = opaque; | |
2031 | /* Compute PLLMR value from PSR settings */ | |
2032 | cpc->pllmr = 0x80000000; | |
2033 | /* PFWD */ | |
2034 | switch ((cpc->psr >> 30) & 3) { | |
2035 | case 0: | |
2036 | /* Bypass */ | |
2037 | cpc->pllmr &= ~0x80000000; | |
2038 | break; | |
2039 | case 1: | |
2040 | /* Divide by 3 */ | |
2041 | cpc->pllmr |= 5 << 16; | |
2042 | break; | |
2043 | case 2: | |
2044 | /* Divide by 4 */ | |
2045 | cpc->pllmr |= 4 << 16; | |
2046 | break; | |
2047 | case 3: | |
2048 | /* Divide by 6 */ | |
2049 | cpc->pllmr |= 2 << 16; | |
2050 | break; | |
2051 | } | |
2052 | /* PFBD */ | |
2053 | D = (cpc->psr >> 28) & 3; | |
2054 | cpc->pllmr |= (D + 1) << 20; | |
2055 | /* PT */ | |
2056 | D = (cpc->psr >> 25) & 7; | |
2057 | switch (D) { | |
2058 | case 0x2: | |
2059 | cpc->pllmr |= 0x13; | |
2060 | break; | |
2061 | case 0x4: | |
2062 | cpc->pllmr |= 0x15; | |
2063 | break; | |
2064 | case 0x5: | |
2065 | cpc->pllmr |= 0x16; | |
2066 | break; | |
2067 | default: | |
2068 | break; | |
2069 | } | |
2070 | /* PDC */ | |
2071 | D = (cpc->psr >> 23) & 3; | |
2072 | cpc->pllmr |= D << 26; | |
2073 | /* ODP */ | |
2074 | D = (cpc->psr >> 21) & 3; | |
2075 | cpc->pllmr |= D << 10; | |
2076 | /* EBPD */ | |
2077 | D = (cpc->psr >> 17) & 3; | |
2078 | cpc->pllmr |= D << 24; | |
2079 | cpc->cr0 = 0x0000003C; | |
2080 | cpc->cr1 = 0x2B0D8800; | |
2081 | cpc->er = 0x00000000; | |
2082 | cpc->fr = 0x00000000; | |
2083 | ppc405cr_clk_setup(cpc); | |
2084 | } | |
2085 | ||
2086 | static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) | |
2087 | { | |
2088 | int D; | |
2089 | ||
2090 | /* XXX: this should be read from IO pins */ | |
2091 | cpc->psr = 0x00000000; /* 8 bits ROM */ | |
2092 | /* PFWD */ | |
2093 | D = 0x2; /* Divide by 4 */ | |
2094 | cpc->psr |= D << 30; | |
2095 | /* PFBD */ | |
2096 | D = 0x1; /* Divide by 2 */ | |
2097 | cpc->psr |= D << 28; | |
2098 | /* PDC */ | |
2099 | D = 0x1; /* Divide by 2 */ | |
2100 | cpc->psr |= D << 23; | |
2101 | /* PT */ | |
2102 | D = 0x5; /* M = 16 */ | |
2103 | cpc->psr |= D << 25; | |
2104 | /* ODP */ | |
2105 | D = 0x1; /* Divide by 2 */ | |
2106 | cpc->psr |= D << 21; | |
2107 | /* EBDP */ | |
2108 | D = 0x2; /* Divide by 4 */ | |
2109 | cpc->psr |= D << 17; | |
2110 | } | |
2111 | ||
2112 | static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], | |
2113 | uint32_t sysclk) | |
2114 | { | |
2115 | ppc405cr_cpc_t *cpc; | |
2116 | ||
2117 | cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t)); | |
487414f1 AL |
2118 | memcpy(cpc->clk_setup, clk_setup, |
2119 | PPC405CR_CLK_NB * sizeof(clk_setup_t)); | |
2120 | cpc->sysclk = sysclk; | |
2121 | cpc->jtagid = 0x42051049; | |
2122 | ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, | |
2123 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2124 | ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, | |
2125 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2126 | ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, | |
2127 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2128 | ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, | |
2129 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2130 | ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, | |
2131 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2132 | ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, | |
2133 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2134 | ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, | |
2135 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2136 | ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, | |
2137 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2138 | ppc405cr_clk_init(cpc); | |
a08d4367 | 2139 | qemu_register_reset(ppc405cr_cpc_reset, cpc); |
487414f1 | 2140 | ppc405cr_cpc_reset(cpc); |
8ecc7913 JM |
2141 | } |
2142 | ||
71db710f BS |
2143 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
2144 | target_phys_addr_t ram_sizes[4], | |
8ecc7913 | 2145 | uint32_t sysclk, qemu_irq **picp, |
5c130f65 | 2146 | int do_init) |
8ecc7913 | 2147 | { |
04f20795 | 2148 | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
8ecc7913 JM |
2149 | qemu_irq dma_irqs[4]; |
2150 | CPUState *env; | |
8ecc7913 | 2151 | qemu_irq *pic, *irqs; |
8ecc7913 JM |
2152 | |
2153 | memset(clk_setup, 0, sizeof(clk_setup)); | |
008ff9d7 | 2154 | env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK], |
04f20795 | 2155 | &clk_setup[PPC405CR_TMR_CLK], sysclk); |
8ecc7913 | 2156 | /* Memory mapped devices registers */ |
8ecc7913 JM |
2157 | /* PLB arbitrer */ |
2158 | ppc4xx_plb_init(env); | |
2159 | /* PLB to OPB bridge */ | |
2160 | ppc4xx_pob_init(env); | |
2161 | /* OBP arbitrer */ | |
802670e6 | 2162 | ppc4xx_opba_init(0xef600600); |
8ecc7913 JM |
2163 | /* Universal interrupt controller */ |
2164 | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); | |
2165 | irqs[PPCUIC_OUTPUT_INT] = | |
b48d7d69 | 2166 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
8ecc7913 | 2167 | irqs[PPCUIC_OUTPUT_CINT] = |
b48d7d69 | 2168 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
8ecc7913 JM |
2169 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2170 | *picp = pic; | |
2171 | /* SDRAM controller */ | |
80e8bd2b | 2172 | ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
8ecc7913 JM |
2173 | /* External bus controller */ |
2174 | ppc405_ebc_init(env); | |
2175 | /* DMA controller */ | |
04f20795 JM |
2176 | dma_irqs[0] = pic[26]; |
2177 | dma_irqs[1] = pic[25]; | |
2178 | dma_irqs[2] = pic[24]; | |
2179 | dma_irqs[3] = pic[23]; | |
8ecc7913 JM |
2180 | ppc405_dma_init(env, dma_irqs); |
2181 | /* Serial ports */ | |
2182 | if (serial_hds[0] != NULL) { | |
802670e6 BS |
2183 | serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, |
2184 | serial_hds[0], 1); | |
8ecc7913 JM |
2185 | } |
2186 | if (serial_hds[1] != NULL) { | |
802670e6 BS |
2187 | serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, |
2188 | serial_hds[1], 1); | |
8ecc7913 JM |
2189 | } |
2190 | /* IIC controller */ | |
802670e6 | 2191 | ppc405_i2c_init(0xef600500, pic[2]); |
8ecc7913 | 2192 | /* GPIO */ |
802670e6 | 2193 | ppc405_gpio_init(0xef600700); |
8ecc7913 JM |
2194 | /* CPU control */ |
2195 | ppc405cr_cpc_init(env, clk_setup, sysclk); | |
8ecc7913 JM |
2196 | |
2197 | return env; | |
2198 | } | |
2199 | ||
2200 | /*****************************************************************************/ | |
2201 | /* PowerPC 405EP */ | |
2202 | /* CPU control */ | |
2203 | enum { | |
2204 | PPC405EP_CPC0_PLLMR0 = 0x0F0, | |
2205 | PPC405EP_CPC0_BOOT = 0x0F1, | |
2206 | PPC405EP_CPC0_EPCTL = 0x0F3, | |
2207 | PPC405EP_CPC0_PLLMR1 = 0x0F4, | |
2208 | PPC405EP_CPC0_UCR = 0x0F5, | |
2209 | PPC405EP_CPC0_SRR = 0x0F6, | |
2210 | PPC405EP_CPC0_JTAGID = 0x0F7, | |
2211 | PPC405EP_CPC0_PCI = 0x0F9, | |
9c02f1a2 JM |
2212 | #if 0 |
2213 | PPC405EP_CPC0_ER = xxx, | |
2214 | PPC405EP_CPC0_FR = xxx, | |
2215 | PPC405EP_CPC0_SR = xxx, | |
2216 | #endif | |
8ecc7913 JM |
2217 | }; |
2218 | ||
04f20795 JM |
2219 | enum { |
2220 | PPC405EP_CPU_CLK = 0, | |
2221 | PPC405EP_PLB_CLK = 1, | |
2222 | PPC405EP_OPB_CLK = 2, | |
2223 | PPC405EP_EBC_CLK = 3, | |
2224 | PPC405EP_MAL_CLK = 4, | |
2225 | PPC405EP_PCI_CLK = 5, | |
2226 | PPC405EP_UART0_CLK = 6, | |
2227 | PPC405EP_UART1_CLK = 7, | |
2228 | PPC405EP_CLK_NB = 8, | |
2229 | }; | |
2230 | ||
8ecc7913 JM |
2231 | typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
2232 | struct ppc405ep_cpc_t { | |
2233 | uint32_t sysclk; | |
04f20795 | 2234 | clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
8ecc7913 JM |
2235 | uint32_t boot; |
2236 | uint32_t epctl; | |
2237 | uint32_t pllmr[2]; | |
2238 | uint32_t ucr; | |
2239 | uint32_t srr; | |
2240 | uint32_t jtagid; | |
2241 | uint32_t pci; | |
9c02f1a2 JM |
2242 | /* Clock and power management */ |
2243 | uint32_t er; | |
2244 | uint32_t fr; | |
2245 | uint32_t sr; | |
8ecc7913 JM |
2246 | }; |
2247 | ||
2248 | static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) | |
2249 | { | |
2250 | uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; | |
2251 | uint32_t UART0_clk, UART1_clk; | |
2252 | uint64_t VCO_out, PLL_out; | |
2253 | int M, D; | |
2254 | ||
2255 | VCO_out = 0; | |
2256 | if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { | |
2257 | M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ | |
aae9366a JM |
2258 | #ifdef DEBUG_CLOCKS_LL |
2259 | printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); | |
2260 | #endif | |
8ecc7913 | 2261 | D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
aae9366a JM |
2262 | #ifdef DEBUG_CLOCKS_LL |
2263 | printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); | |
2264 | #endif | |
8ecc7913 JM |
2265 | VCO_out = cpc->sysclk * M * D; |
2266 | if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { | |
2267 | /* Error - unlock the PLL */ | |
2268 | printf("VCO out of range %" PRIu64 "\n", VCO_out); | |
2269 | #if 0 | |
2270 | cpc->pllmr[1] &= ~0x80000000; | |
2271 | goto pll_bypass; | |
2272 | #endif | |
2273 | } | |
2274 | PLL_out = VCO_out / D; | |
9c02f1a2 JM |
2275 | /* Pretend the PLL is locked */ |
2276 | cpc->boot |= 0x00000001; | |
8ecc7913 JM |
2277 | } else { |
2278 | #if 0 | |
2279 | pll_bypass: | |
2280 | #endif | |
2281 | PLL_out = cpc->sysclk; | |
9c02f1a2 JM |
2282 | if (cpc->pllmr[1] & 0x40000000) { |
2283 | /* Pretend the PLL is not locked */ | |
2284 | cpc->boot &= ~0x00000001; | |
2285 | } | |
8ecc7913 JM |
2286 | } |
2287 | /* Now, compute all other clocks */ | |
2288 | D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ | |
aae9366a JM |
2289 | #ifdef DEBUG_CLOCKS_LL |
2290 | printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); | |
8ecc7913 JM |
2291 | #endif |
2292 | CPU_clk = PLL_out / D; | |
2293 | D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ | |
aae9366a JM |
2294 | #ifdef DEBUG_CLOCKS_LL |
2295 | printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); | |
8ecc7913 JM |
2296 | #endif |
2297 | PLB_clk = CPU_clk / D; | |
2298 | D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ | |
aae9366a JM |
2299 | #ifdef DEBUG_CLOCKS_LL |
2300 | printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); | |
8ecc7913 JM |
2301 | #endif |
2302 | OPB_clk = PLB_clk / D; | |
2303 | D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ | |
aae9366a JM |
2304 | #ifdef DEBUG_CLOCKS_LL |
2305 | printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); | |
8ecc7913 JM |
2306 | #endif |
2307 | EBC_clk = PLB_clk / D; | |
2308 | D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ | |
aae9366a JM |
2309 | #ifdef DEBUG_CLOCKS_LL |
2310 | printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); | |
8ecc7913 JM |
2311 | #endif |
2312 | MAL_clk = PLB_clk / D; | |
2313 | D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ | |
aae9366a JM |
2314 | #ifdef DEBUG_CLOCKS_LL |
2315 | printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); | |
8ecc7913 JM |
2316 | #endif |
2317 | PCI_clk = PLB_clk / D; | |
2318 | D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ | |
aae9366a JM |
2319 | #ifdef DEBUG_CLOCKS_LL |
2320 | printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); | |
8ecc7913 JM |
2321 | #endif |
2322 | UART0_clk = PLL_out / D; | |
2323 | D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ | |
aae9366a JM |
2324 | #ifdef DEBUG_CLOCKS_LL |
2325 | printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); | |
8ecc7913 JM |
2326 | #endif |
2327 | UART1_clk = PLL_out / D; | |
2328 | #ifdef DEBUG_CLOCKS | |
aae9366a | 2329 | printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 |
8ecc7913 | 2330 | " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
aae9366a JM |
2331 | printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 |
2332 | " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 | |
2333 | " UART1 %" PRIu32 "\n", | |
8ecc7913 JM |
2334 | CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
2335 | UART0_clk, UART1_clk); | |
2336 | #endif | |
2337 | /* Setup CPU clocks */ | |
04f20795 | 2338 | clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
8ecc7913 | 2339 | /* Setup PLB clock */ |
04f20795 | 2340 | clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
8ecc7913 | 2341 | /* Setup OPB clock */ |
04f20795 | 2342 | clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
8ecc7913 | 2343 | /* Setup external clock */ |
04f20795 | 2344 | clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
8ecc7913 | 2345 | /* Setup MAL clock */ |
04f20795 | 2346 | clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
8ecc7913 | 2347 | /* Setup PCI clock */ |
04f20795 | 2348 | clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
8ecc7913 | 2349 | /* Setup UART0 clock */ |
04f20795 | 2350 | clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
8ecc7913 | 2351 | /* Setup UART1 clock */ |
04f20795 | 2352 | clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
8ecc7913 JM |
2353 | } |
2354 | ||
2355 | static target_ulong dcr_read_epcpc (void *opaque, int dcrn) | |
2356 | { | |
2357 | ppc405ep_cpc_t *cpc; | |
2358 | target_ulong ret; | |
2359 | ||
2360 | cpc = opaque; | |
2361 | switch (dcrn) { | |
2362 | case PPC405EP_CPC0_BOOT: | |
2363 | ret = cpc->boot; | |
2364 | break; | |
2365 | case PPC405EP_CPC0_EPCTL: | |
2366 | ret = cpc->epctl; | |
2367 | break; | |
2368 | case PPC405EP_CPC0_PLLMR0: | |
2369 | ret = cpc->pllmr[0]; | |
2370 | break; | |
2371 | case PPC405EP_CPC0_PLLMR1: | |
2372 | ret = cpc->pllmr[1]; | |
2373 | break; | |
2374 | case PPC405EP_CPC0_UCR: | |
2375 | ret = cpc->ucr; | |
2376 | break; | |
2377 | case PPC405EP_CPC0_SRR: | |
2378 | ret = cpc->srr; | |
2379 | break; | |
2380 | case PPC405EP_CPC0_JTAGID: | |
2381 | ret = cpc->jtagid; | |
2382 | break; | |
2383 | case PPC405EP_CPC0_PCI: | |
2384 | ret = cpc->pci; | |
2385 | break; | |
2386 | default: | |
2387 | /* Avoid gcc warning */ | |
2388 | ret = 0; | |
2389 | break; | |
2390 | } | |
2391 | ||
2392 | return ret; | |
2393 | } | |
2394 | ||
2395 | static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) | |
2396 | { | |
2397 | ppc405ep_cpc_t *cpc; | |
2398 | ||
2399 | cpc = opaque; | |
2400 | switch (dcrn) { | |
2401 | case PPC405EP_CPC0_BOOT: | |
2402 | /* Read-only register */ | |
2403 | break; | |
2404 | case PPC405EP_CPC0_EPCTL: | |
2405 | /* Don't care for now */ | |
2406 | cpc->epctl = val & 0xC00000F3; | |
2407 | break; | |
2408 | case PPC405EP_CPC0_PLLMR0: | |
2409 | cpc->pllmr[0] = val & 0x00633333; | |
2410 | ppc405ep_compute_clocks(cpc); | |
2411 | break; | |
2412 | case PPC405EP_CPC0_PLLMR1: | |
2413 | cpc->pllmr[1] = val & 0xC0F73FFF; | |
2414 | ppc405ep_compute_clocks(cpc); | |
2415 | break; | |
2416 | case PPC405EP_CPC0_UCR: | |
2417 | /* UART control - don't care for now */ | |
2418 | cpc->ucr = val & 0x003F7F7F; | |
2419 | break; | |
2420 | case PPC405EP_CPC0_SRR: | |
2421 | cpc->srr = val; | |
2422 | break; | |
2423 | case PPC405EP_CPC0_JTAGID: | |
2424 | /* Read-only */ | |
2425 | break; | |
2426 | case PPC405EP_CPC0_PCI: | |
2427 | cpc->pci = val; | |
2428 | break; | |
2429 | } | |
2430 | } | |
2431 | ||
2432 | static void ppc405ep_cpc_reset (void *opaque) | |
2433 | { | |
2434 | ppc405ep_cpc_t *cpc = opaque; | |
2435 | ||
2436 | cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ | |
2437 | cpc->epctl = 0x00000000; | |
2438 | cpc->pllmr[0] = 0x00011010; | |
2439 | cpc->pllmr[1] = 0x40000000; | |
2440 | cpc->ucr = 0x00000000; | |
2441 | cpc->srr = 0x00040000; | |
2442 | cpc->pci = 0x00000000; | |
9c02f1a2 JM |
2443 | cpc->er = 0x00000000; |
2444 | cpc->fr = 0x00000000; | |
2445 | cpc->sr = 0x00000000; | |
8ecc7913 JM |
2446 | ppc405ep_compute_clocks(cpc); |
2447 | } | |
2448 | ||
2449 | /* XXX: sysclk should be between 25 and 100 MHz */ | |
2450 | static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], | |
2451 | uint32_t sysclk) | |
2452 | { | |
2453 | ppc405ep_cpc_t *cpc; | |
2454 | ||
2455 | cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t)); | |
487414f1 AL |
2456 | memcpy(cpc->clk_setup, clk_setup, |
2457 | PPC405EP_CLK_NB * sizeof(clk_setup_t)); | |
2458 | cpc->jtagid = 0x20267049; | |
2459 | cpc->sysclk = sysclk; | |
2460 | ppc405ep_cpc_reset(cpc); | |
a08d4367 | 2461 | qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
487414f1 AL |
2462 | ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
2463 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2464 | ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, | |
2465 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2466 | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, | |
2467 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2468 | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, | |
2469 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2470 | ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, | |
2471 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2472 | ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, | |
2473 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2474 | ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, | |
2475 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2476 | ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, | |
2477 | &dcr_read_epcpc, &dcr_write_epcpc); | |
9c02f1a2 | 2478 | #if 0 |
487414f1 AL |
2479 | ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, |
2480 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2481 | ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, | |
2482 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2483 | ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, | |
2484 | &dcr_read_epcpc, &dcr_write_epcpc); | |
9c02f1a2 | 2485 | #endif |
8ecc7913 JM |
2486 | } |
2487 | ||
71db710f BS |
2488 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
2489 | target_phys_addr_t ram_sizes[2], | |
8ecc7913 | 2490 | uint32_t sysclk, qemu_irq **picp, |
5c130f65 | 2491 | int do_init) |
8ecc7913 | 2492 | { |
9c02f1a2 JM |
2493 | clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
2494 | qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; | |
8ecc7913 | 2495 | CPUState *env; |
8ecc7913 | 2496 | qemu_irq *pic, *irqs; |
8ecc7913 JM |
2497 | |
2498 | memset(clk_setup, 0, sizeof(clk_setup)); | |
2499 | /* init CPUs */ | |
008ff9d7 | 2500 | env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK], |
9c02f1a2 JM |
2501 | &tlb_clk_setup, sysclk); |
2502 | clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; | |
2503 | clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; | |
8ecc7913 JM |
2504 | /* Internal devices init */ |
2505 | /* Memory mapped devices registers */ | |
8ecc7913 JM |
2506 | /* PLB arbitrer */ |
2507 | ppc4xx_plb_init(env); | |
2508 | /* PLB to OPB bridge */ | |
2509 | ppc4xx_pob_init(env); | |
2510 | /* OBP arbitrer */ | |
802670e6 | 2511 | ppc4xx_opba_init(0xef600600); |
8ecc7913 JM |
2512 | /* Universal interrupt controller */ |
2513 | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); | |
2514 | irqs[PPCUIC_OUTPUT_INT] = | |
b48d7d69 | 2515 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
8ecc7913 | 2516 | irqs[PPCUIC_OUTPUT_CINT] = |
b48d7d69 | 2517 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
8ecc7913 JM |
2518 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2519 | *picp = pic; | |
2520 | /* SDRAM controller */ | |
923e5e33 | 2521 | /* XXX 405EP has no ECC interrupt */ |
80e8bd2b | 2522 | ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
8ecc7913 JM |
2523 | /* External bus controller */ |
2524 | ppc405_ebc_init(env); | |
2525 | /* DMA controller */ | |
923e5e33 AJ |
2526 | dma_irqs[0] = pic[5]; |
2527 | dma_irqs[1] = pic[6]; | |
2528 | dma_irqs[2] = pic[7]; | |
2529 | dma_irqs[3] = pic[8]; | |
8ecc7913 JM |
2530 | ppc405_dma_init(env, dma_irqs); |
2531 | /* IIC controller */ | |
802670e6 | 2532 | ppc405_i2c_init(0xef600500, pic[2]); |
8ecc7913 | 2533 | /* GPIO */ |
802670e6 | 2534 | ppc405_gpio_init(0xef600700); |
8ecc7913 JM |
2535 | /* Serial ports */ |
2536 | if (serial_hds[0] != NULL) { | |
802670e6 BS |
2537 | serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, |
2538 | serial_hds[0], 1); | |
8ecc7913 JM |
2539 | } |
2540 | if (serial_hds[1] != NULL) { | |
802670e6 BS |
2541 | serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, |
2542 | serial_hds[1], 1); | |
8ecc7913 JM |
2543 | } |
2544 | /* OCM */ | |
5c130f65 | 2545 | ppc405_ocm_init(env); |
9c02f1a2 | 2546 | /* GPT */ |
923e5e33 AJ |
2547 | gpt_irqs[0] = pic[19]; |
2548 | gpt_irqs[1] = pic[20]; | |
2549 | gpt_irqs[2] = pic[21]; | |
2550 | gpt_irqs[3] = pic[22]; | |
2551 | gpt_irqs[4] = pic[23]; | |
802670e6 | 2552 | ppc4xx_gpt_init(0xef600000, gpt_irqs); |
8ecc7913 | 2553 | /* PCI */ |
923e5e33 | 2554 | /* Uses pic[3], pic[16], pic[18] */ |
9c02f1a2 | 2555 | /* MAL */ |
923e5e33 AJ |
2556 | mal_irqs[0] = pic[11]; |
2557 | mal_irqs[1] = pic[12]; | |
2558 | mal_irqs[2] = pic[13]; | |
2559 | mal_irqs[3] = pic[14]; | |
9c02f1a2 JM |
2560 | ppc405_mal_init(env, mal_irqs); |
2561 | /* Ethernet */ | |
923e5e33 | 2562 | /* Uses pic[9], pic[15], pic[17] */ |
8ecc7913 JM |
2563 | /* CPU control */ |
2564 | ppc405ep_cpc_init(env, clk_setup, sysclk); | |
8ecc7913 JM |
2565 | |
2566 | return env; | |
2567 | } |