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64201201 FB |
1 | /* |
2 | * QEMU PPC CHRP/PMAC hardware System Emulator | |
3 | * | |
47103572 | 4 | * Copyright (c) 2004-2007 Fabrice Bellard |
64201201 FB |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "vl.h" | |
25 | ||
e9df014c JM |
26 | /* SMP is not enabled, for now */ |
27 | #define MAX_CPUS 1 | |
28 | ||
64201201 | 29 | #define BIOS_FILENAME "ppc_rom.bin" |
d5295253 | 30 | #define VGABIOS_FILENAME "video.x" |
64201201 FB |
31 | #define NVRAM_SIZE 0x2000 |
32 | ||
b6b8bd18 FB |
33 | #define KERNEL_LOAD_ADDR 0x01000000 |
34 | #define INITRD_LOAD_ADDR 0x01800000 | |
35 | ||
267002cd | 36 | /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA, |
e5733356 | 37 | NVRAM */ |
267002cd FB |
38 | |
39 | static int dbdma_mem_index; | |
40 | static int cuda_mem_index; | |
0aa6a4a2 FB |
41 | static int ide0_mem_index = -1; |
42 | static int ide1_mem_index = -1; | |
43 | static int openpic_mem_index = -1; | |
44 | static int heathrow_pic_mem_index = -1; | |
e5733356 | 45 | static int macio_nvram_mem_index = -1; |
267002cd FB |
46 | |
47 | /* DBDMA: currently no op - should suffice right now */ | |
48 | ||
49 | static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) | |
50 | { | |
b6b8bd18 | 51 | printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value); |
267002cd FB |
52 | } |
53 | ||
54 | static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value) | |
55 | { | |
56 | } | |
57 | ||
58 | static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
59 | { | |
60 | } | |
61 | ||
62 | static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) | |
63 | { | |
b6b8bd18 | 64 | printf("%s: 0x%08x => 0x00000000\n", __func__, addr); |
267002cd FB |
65 | return 0; |
66 | } | |
67 | ||
68 | static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) | |
69 | { | |
70 | return 0; | |
71 | } | |
72 | ||
73 | static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) | |
74 | { | |
75 | return 0; | |
76 | } | |
77 | ||
78 | static CPUWriteMemoryFunc *dbdma_write[] = { | |
79 | &dbdma_writeb, | |
80 | &dbdma_writew, | |
81 | &dbdma_writel, | |
82 | }; | |
83 | ||
84 | static CPUReadMemoryFunc *dbdma_read[] = { | |
85 | &dbdma_readb, | |
86 | &dbdma_readw, | |
87 | &dbdma_readl, | |
88 | }; | |
89 | ||
e5733356 FB |
90 | /* macio style NVRAM device */ |
91 | typedef struct MacIONVRAMState { | |
92 | uint8_t data[0x2000]; | |
93 | } MacIONVRAMState; | |
94 | ||
95 | static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) | |
96 | { | |
97 | MacIONVRAMState *s = opaque; | |
98 | addr = (addr >> 4) & 0x1fff; | |
99 | s->data[addr] = value; | |
100 | // printf("macio_nvram_writeb %04x = %02x\n", addr, value); | |
101 | } | |
102 | ||
103 | static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) | |
104 | { | |
105 | MacIONVRAMState *s = opaque; | |
106 | uint32_t value; | |
107 | ||
108 | addr = (addr >> 4) & 0x1fff; | |
109 | value = s->data[addr]; | |
110 | // printf("macio_nvram_readb %04x = %02x\n", addr, value); | |
111 | return value; | |
112 | } | |
113 | ||
114 | static CPUWriteMemoryFunc *macio_nvram_write[] = { | |
115 | &macio_nvram_writeb, | |
116 | &macio_nvram_writeb, | |
117 | &macio_nvram_writeb, | |
118 | }; | |
119 | ||
120 | static CPUReadMemoryFunc *macio_nvram_read[] = { | |
121 | &macio_nvram_readb, | |
122 | &macio_nvram_readb, | |
123 | &macio_nvram_readb, | |
124 | }; | |
125 | ||
126 | static MacIONVRAMState *macio_nvram_init(void) | |
127 | { | |
128 | MacIONVRAMState *s; | |
129 | s = qemu_mallocz(sizeof(MacIONVRAMState)); | |
130 | if (!s) | |
131 | return NULL; | |
132 | macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read, | |
133 | macio_nvram_write, s); | |
134 | return s; | |
135 | } | |
136 | ||
267002cd FB |
137 | static void macio_map(PCIDevice *pci_dev, int region_num, |
138 | uint32_t addr, uint32_t size, int type) | |
139 | { | |
0aa6a4a2 FB |
140 | if (heathrow_pic_mem_index >= 0) { |
141 | cpu_register_physical_memory(addr + 0x00000, 0x1000, | |
142 | heathrow_pic_mem_index); | |
143 | } | |
267002cd FB |
144 | cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index); |
145 | cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index); | |
0aa6a4a2 FB |
146 | if (ide0_mem_index >= 0) |
147 | cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index); | |
148 | if (ide1_mem_index >= 0) | |
149 | cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index); | |
150 | if (openpic_mem_index >= 0) { | |
151 | cpu_register_physical_memory(addr + 0x40000, 0x40000, | |
152 | openpic_mem_index); | |
153 | } | |
e5733356 FB |
154 | if (macio_nvram_mem_index >= 0) |
155 | cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index); | |
267002cd FB |
156 | } |
157 | ||
e5733356 | 158 | static void macio_init(PCIBus *bus, int device_id) |
267002cd FB |
159 | { |
160 | PCIDevice *d; | |
161 | ||
46e50e9d FB |
162 | d = pci_register_device(bus, "macio", sizeof(PCIDevice), |
163 | -1, NULL, NULL); | |
267002cd FB |
164 | /* Note: this code is strongly inspirated from the corresponding code |
165 | in PearPC */ | |
166 | d->config[0x00] = 0x6b; // vendor_id | |
167 | d->config[0x01] = 0x10; | |
e5733356 FB |
168 | d->config[0x02] = device_id; |
169 | d->config[0x03] = device_id >> 8; | |
267002cd FB |
170 | |
171 | d->config[0x0a] = 0x00; // class_sub = pci2pci | |
172 | d->config[0x0b] = 0xff; // class_base = bridge | |
173 | d->config[0x0e] = 0x00; // header_type | |
174 | ||
175 | d->config[0x3d] = 0x01; // interrupt on pin 1 | |
176 | ||
177 | dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); | |
178 | ||
179 | pci_register_io_region(d, 0, 0x80000, | |
180 | PCI_ADDRESS_SPACE_MEM, macio_map); | |
181 | } | |
182 | ||
0aa6a4a2 FB |
183 | /* UniN device */ |
184 | static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
185 | { | |
186 | } | |
187 | ||
188 | static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) | |
189 | { | |
190 | return 0; | |
191 | } | |
192 | ||
193 | static CPUWriteMemoryFunc *unin_write[] = { | |
194 | &unin_writel, | |
195 | &unin_writel, | |
196 | &unin_writel, | |
197 | }; | |
198 | ||
199 | static CPUReadMemoryFunc *unin_read[] = { | |
200 | &unin_readl, | |
201 | &unin_readl, | |
202 | &unin_readl, | |
203 | }; | |
204 | ||
205 | /* temporary frame buffer OSI calls for the video.x driver. The right | |
206 | solution is to modify the driver to use VGA PCI I/Os */ | |
207 | static int vga_osi_call(CPUState *env) | |
208 | { | |
209 | static int vga_vbl_enabled; | |
210 | int linesize; | |
211 | ||
212 | // printf("osi_call R5=%d\n", env->gpr[5]); | |
213 | ||
214 | /* same handler as PearPC, coming from the original MOL video | |
215 | driver. */ | |
216 | switch(env->gpr[5]) { | |
217 | case 4: | |
218 | break; | |
219 | case 28: /* set_vmode */ | |
220 | if (env->gpr[6] != 1 || env->gpr[7] != 0) | |
221 | env->gpr[3] = 1; | |
222 | else | |
223 | env->gpr[3] = 0; | |
224 | break; | |
225 | case 29: /* get_vmode_info */ | |
226 | if (env->gpr[6] != 0) { | |
227 | if (env->gpr[6] != 1 || env->gpr[7] != 0) { | |
228 | env->gpr[3] = 1; | |
229 | break; | |
230 | } | |
231 | } | |
232 | env->gpr[3] = 0; | |
233 | env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ | |
234 | env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ | |
235 | env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ | |
236 | env->gpr[7] = 85 << 16; /* refresh rate */ | |
237 | env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ | |
238 | linesize = ((graphic_depth + 7) >> 3) * graphic_width; | |
239 | linesize = (linesize + 3) & ~3; | |
240 | env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ | |
241 | break; | |
242 | case 31: /* set_video power */ | |
243 | env->gpr[3] = 0; | |
244 | break; | |
245 | case 39: /* video_ctrl */ | |
246 | if (env->gpr[6] == 0 || env->gpr[6] == 1) | |
247 | vga_vbl_enabled = env->gpr[6]; | |
248 | env->gpr[3] = 0; | |
249 | break; | |
250 | case 47: | |
251 | break; | |
252 | case 59: /* set_color */ | |
253 | /* R6 = index, R7 = RGB */ | |
254 | env->gpr[3] = 0; | |
255 | break; | |
256 | case 64: /* get color */ | |
257 | /* R6 = index */ | |
258 | env->gpr[3] = 0; | |
259 | break; | |
260 | case 116: /* set hwcursor */ | |
261 | /* R6 = x, R7 = y, R8 = visible, R9 = data */ | |
262 | break; | |
263 | default: | |
264 | fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]); | |
265 | break; | |
266 | } | |
267 | return 1; /* osi_call handled */ | |
268 | } | |
269 | ||
e5733356 FB |
270 | static uint8_t nvram_chksum(const uint8_t *buf, int n) |
271 | { | |
272 | int sum, i; | |
273 | sum = 0; | |
274 | for(i = 0; i < n; i++) | |
275 | sum += buf[i]; | |
276 | return (sum & 0xff) + (sum >> 8); | |
277 | } | |
278 | ||
279 | /* set a free Mac OS NVRAM partition */ | |
280 | void pmac_format_nvram_partition(uint8_t *buf, int len) | |
281 | { | |
282 | char partition_name[12] = "wwwwwwwwwwww"; | |
283 | ||
284 | buf[0] = 0x7f; /* free partition magic */ | |
285 | buf[1] = 0; /* checksum */ | |
286 | buf[2] = len >> 8; | |
287 | buf[3] = len; | |
288 | memcpy(buf + 4, partition_name, 12); | |
289 | buf[1] = nvram_chksum(buf, 16); | |
290 | } | |
291 | ||
0aa6a4a2 | 292 | /* PowerPC CHRP hardware initialisation */ |
94fc95cd JM |
293 | static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, |
294 | DisplayState *ds, const char **fd_filename, | |
295 | int snapshot, | |
296 | const char *kernel_filename, | |
297 | const char *kernel_cmdline, | |
298 | const char *initrd_filename, | |
299 | const char *cpu_model, | |
300 | int is_heathrow) | |
64201201 | 301 | { |
e9df014c | 302 | CPUState *env, *envs[MAX_CPUS]; |
64201201 | 303 | char buf[1024]; |
e9df014c | 304 | qemu_irq *pic, **openpic_irqs; |
64201201 | 305 | m48t59_t *nvram; |
aef445bd | 306 | int unin_memory; |
d5295253 FB |
307 | int linux_boot, i; |
308 | unsigned long bios_offset, vga_bios_offset; | |
b6b8bd18 | 309 | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
3fc6c082 | 310 | ppc_def_t *def; |
46e50e9d | 311 | PCIBus *pci_bus; |
0aa6a4a2 | 312 | const char *arch_name; |
d5295253 | 313 | int vga_bios_size, bios_size; |
d537cf6c | 314 | qemu_irq *dummy_irq; |
46e50e9d | 315 | |
64201201 FB |
316 | linux_boot = (kernel_filename != NULL); |
317 | ||
c68ea704 FB |
318 | /* init CPUs */ |
319 | env = cpu_init(); | |
320 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | |
321 | ||
94fc95cd JM |
322 | /* Default CPU is a generic 74x/75x */ |
323 | if (cpu_model == NULL) | |
324 | cpu_model = "750"; | |
c68ea704 FB |
325 | /* XXX: CPU model (or PVR) should be provided on command line */ |
326 | // ppc_find_by_name("750gx", &def); // Linux boot OK | |
327 | // ppc_find_by_name("750fx", &def); // Linux boot OK | |
328 | /* Linux does not boot on 750cxe (and probably other 750cx based) | |
329 | * because it assumes it has 8 IBAT & DBAT pairs as it only have 4. | |
330 | */ | |
94fc95cd | 331 | ppc_find_by_name(cpu_model, &def); |
c68ea704 FB |
332 | if (def == NULL) { |
333 | cpu_abort(env, "Unable to find PowerPC CPU definition\n"); | |
334 | } | |
e9df014c JM |
335 | for (i = 0; i < smp_cpus; i++) { |
336 | cpu_ppc_register(env, def); | |
337 | /* Set time-base frequency to 100 Mhz */ | |
338 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
339 | env->osi_call = vga_osi_call; | |
340 | envs[i] = env; | |
341 | } | |
c68ea704 | 342 | |
64201201 FB |
343 | /* allocate RAM */ |
344 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
345 | ||
346 | /* allocate and load BIOS */ | |
347 | bios_offset = ram_size + vga_ram_size; | |
348 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
d5295253 FB |
349 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
350 | if (bios_size < 0 || bios_size > BIOS_SIZE) { | |
351 | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf); | |
64201201 FB |
352 | exit(1); |
353 | } | |
d5295253 FB |
354 | bios_size = (bios_size + 0xfff) & ~0xfff; |
355 | cpu_register_physical_memory((uint32_t)(-bios_size), | |
356 | bios_size, bios_offset | IO_MEM_ROM); | |
357 | ||
358 | /* allocate and load VGA BIOS */ | |
359 | vga_bios_offset = bios_offset + bios_size; | |
360 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); | |
361 | vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8); | |
362 | if (vga_bios_size < 0) { | |
363 | /* if no bios is present, we can still work */ | |
364 | fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf); | |
365 | vga_bios_size = 0; | |
366 | } else { | |
367 | /* set a specific header (XXX: find real Apple format for NDRV | |
368 | drivers) */ | |
369 | phys_ram_base[vga_bios_offset] = 'N'; | |
370 | phys_ram_base[vga_bios_offset + 1] = 'D'; | |
371 | phys_ram_base[vga_bios_offset + 2] = 'R'; | |
372 | phys_ram_base[vga_bios_offset + 3] = 'V'; | |
373 | cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), | |
374 | vga_bios_size); | |
375 | vga_bios_size += 8; | |
376 | } | |
377 | vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; | |
378 | ||
b6b8bd18 FB |
379 | if (linux_boot) { |
380 | kernel_base = KERNEL_LOAD_ADDR; | |
381 | /* now we can load the kernel */ | |
382 | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); | |
383 | if (kernel_size < 0) { | |
384 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
385 | kernel_filename); | |
386 | exit(1); | |
387 | } | |
388 | /* load initrd */ | |
389 | if (initrd_filename) { | |
390 | initrd_base = INITRD_LOAD_ADDR; | |
391 | initrd_size = load_image(initrd_filename, | |
392 | phys_ram_base + initrd_base); | |
393 | if (initrd_size < 0) { | |
394 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
395 | initrd_filename); | |
396 | exit(1); | |
397 | } | |
398 | } else { | |
399 | initrd_base = 0; | |
400 | initrd_size = 0; | |
401 | } | |
402 | boot_device = 'm'; | |
403 | } else { | |
404 | kernel_base = 0; | |
405 | kernel_size = 0; | |
406 | initrd_base = 0; | |
407 | initrd_size = 0; | |
408 | } | |
0aa6a4a2 FB |
409 | |
410 | if (is_heathrow) { | |
411 | isa_mem_base = 0x80000000; | |
0aa6a4a2 FB |
412 | |
413 | /* Register 2 MB of ISA IO space */ | |
aef445bd PB |
414 | isa_mmio_init(0xfe000000, 0x00200000); |
415 | ||
0aa6a4a2 | 416 | /* init basic PC hardware */ |
502a5395 | 417 | pic = heathrow_pic_init(&heathrow_pic_mem_index); |
502a5395 | 418 | pci_bus = pci_grackle_init(0xfec00000, pic); |
89b6b508 FB |
419 | pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
420 | ram_size, vga_ram_size, | |
421 | vga_bios_offset, vga_bios_size); | |
0aa6a4a2 FB |
422 | |
423 | /* XXX: suppress that */ | |
d537cf6c | 424 | dummy_irq = i8259_init(NULL); |
0aa6a4a2 FB |
425 | |
426 | /* XXX: use Mac Serial port */ | |
d537cf6c | 427 | serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
0aa6a4a2 FB |
428 | |
429 | for(i = 0; i < nb_nics; i++) { | |
a41b2ff2 PB |
430 | if (!nd_table[i].model) |
431 | nd_table[i].model = "ne2k_pci"; | |
abcebc7e | 432 | pci_nic_init(pci_bus, &nd_table[i], -1); |
0aa6a4a2 FB |
433 | } |
434 | ||
435 | pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); | |
436 | ||
437 | /* cuda also initialize ADB */ | |
d537cf6c | 438 | cuda_mem_index = cuda_init(pic[0x12]); |
0aa6a4a2 FB |
439 | |
440 | adb_kbd_init(&adb_bus); | |
441 | adb_mouse_init(&adb_bus); | |
442 | ||
e5733356 FB |
443 | { |
444 | MacIONVRAMState *nvr; | |
445 | nvr = macio_nvram_init(); | |
446 | pmac_format_nvram_partition(nvr->data, 0x2000); | |
447 | } | |
448 | ||
449 | macio_init(pci_bus, 0x0017); | |
47103572 | 450 | |
d537cf6c | 451 | nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
47103572 | 452 | |
0aa6a4a2 FB |
453 | arch_name = "HEATHROW"; |
454 | } else { | |
455 | isa_mem_base = 0x80000000; | |
47103572 | 456 | |
0aa6a4a2 | 457 | /* Register 8 MB of ISA IO space */ |
aef445bd | 458 | isa_mmio_init(0xf2000000, 0x00800000); |
47103572 | 459 | |
0aa6a4a2 FB |
460 | /* UniN init */ |
461 | unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); | |
462 | cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); | |
463 | ||
e9df014c JM |
464 | openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); |
465 | openpic_irqs[0] = | |
466 | qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
467 | for (i = 0; i < smp_cpus; i++) { | |
468 | /* Mac99 IRQ connection between OpenPIC outputs pins | |
469 | * and PowerPC input pins | |
470 | */ | |
471 | openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); | |
472 | openpic_irqs[i][OPENPIC_OUTPUT_INT] = | |
473 | ((qemu_irq *)env->irq_inputs)[PPC_INPUT_INT]; | |
474 | openpic_irqs[i][OPENPIC_OUTPUT_CINT] = | |
475 | ((qemu_irq *)env->irq_inputs)[PPC_INPUT_INT]; | |
476 | openpic_irqs[i][OPENPIC_OUTPUT_MCK] = | |
477 | ((qemu_irq *)env->irq_inputs)[PPC_INPUT_MCP]; | |
478 | openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Not connected ? */ | |
479 | openpic_irqs[i][OPENPIC_OUTPUT_RESET] = | |
480 | ((qemu_irq *)env->irq_inputs)[PPC_INPUT_HRESET]; /* Check this */ | |
481 | } | |
482 | pic = openpic_init(NULL, &openpic_mem_index, smp_cpus, | |
483 | openpic_irqs, NULL); | |
502a5395 | 484 | pci_bus = pci_pmac_init(pic); |
0aa6a4a2 | 485 | /* init basic PC hardware */ |
89b6b508 FB |
486 | pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
487 | ram_size, vga_ram_size, | |
488 | vga_bios_offset, vga_bios_size); | |
0aa6a4a2 FB |
489 | |
490 | /* XXX: suppress that */ | |
d537cf6c | 491 | dummy_irq = i8259_init(NULL); |
3079c59a | 492 | |
0aa6a4a2 | 493 | /* XXX: use Mac Serial port */ |
d537cf6c | 494 | serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
0aa6a4a2 | 495 | for(i = 0; i < nb_nics; i++) { |
3079c59a JM |
496 | if (!nd_table[i].model) |
497 | nd_table[i].model = "ne2k_pci"; | |
498 | pci_nic_init(pci_bus, &nd_table[i], -1); | |
0aa6a4a2 | 499 | } |
0aa6a4a2 | 500 | #if 1 |
d537cf6c PB |
501 | ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]); |
502 | ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]); | |
0aa6a4a2 FB |
503 | #else |
504 | pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); | |
505 | #endif | |
506 | /* cuda also initialize ADB */ | |
d537cf6c | 507 | cuda_mem_index = cuda_init(pic[0x19]); |
0aa6a4a2 FB |
508 | |
509 | adb_kbd_init(&adb_bus); | |
510 | adb_mouse_init(&adb_bus); | |
511 | ||
e5733356 | 512 | macio_init(pci_bus, 0x0022); |
0aa6a4a2 | 513 | |
d537cf6c | 514 | nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
0aa6a4a2 FB |
515 | |
516 | arch_name = "MAC99"; | |
64201201 | 517 | } |
0d92ed30 PB |
518 | |
519 | if (usb_enabled) { | |
e24ad6f1 | 520 | usb_ohci_init_pci(pci_bus, 3, -1); |
0d92ed30 PB |
521 | } |
522 | ||
b6b8bd18 FB |
523 | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
524 | graphic_depth = 15; | |
64201201 | 525 | |
0aa6a4a2 | 526 | PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device, |
b6b8bd18 FB |
527 | kernel_base, kernel_size, |
528 | kernel_cmdline, | |
529 | initrd_base, initrd_size, | |
64201201 | 530 | /* XXX: need an option to load a NVRAM image */ |
b6b8bd18 FB |
531 | 0, |
532 | graphic_width, graphic_height, graphic_depth); | |
533 | /* No PCI init: the BIOS will do it */ | |
0aa6a4a2 FB |
534 | |
535 | /* Special port to get debug messages from Open-Firmware */ | |
536 | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); | |
537 | } | |
538 | ||
94fc95cd JM |
539 | static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device, |
540 | DisplayState *ds, const char **fd_filename, | |
541 | int snapshot, | |
542 | const char *kernel_filename, | |
543 | const char *kernel_cmdline, | |
544 | const char *initrd_filename, | |
545 | const char *cpu_model) | |
0aa6a4a2 FB |
546 | { |
547 | ppc_chrp_init(ram_size, vga_ram_size, boot_device, | |
548 | ds, fd_filename, snapshot, | |
549 | kernel_filename, kernel_cmdline, | |
94fc95cd | 550 | initrd_filename, cpu_model, 0); |
64201201 | 551 | } |
0aa6a4a2 | 552 | |
94fc95cd JM |
553 | static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device, |
554 | DisplayState *ds, const char **fd_filename, | |
555 | int snapshot, | |
556 | const char *kernel_filename, | |
557 | const char *kernel_cmdline, | |
558 | const char *initrd_filename, | |
559 | const char *cpu_model) | |
0aa6a4a2 FB |
560 | { |
561 | ppc_chrp_init(ram_size, vga_ram_size, boot_device, | |
562 | ds, fd_filename, snapshot, | |
563 | kernel_filename, kernel_cmdline, | |
94fc95cd | 564 | initrd_filename, cpu_model, 1); |
0aa6a4a2 FB |
565 | } |
566 | ||
567 | QEMUMachine core99_machine = { | |
0289b2c1 FB |
568 | "mac99", |
569 | "Mac99 based PowerMAC", | |
0aa6a4a2 FB |
570 | ppc_core99_init, |
571 | }; | |
572 | ||
573 | QEMUMachine heathrow_machine = { | |
0289b2c1 | 574 | "g3bw", |
0aa6a4a2 FB |
575 | "Heathrow based PowerMAC", |
576 | ppc_heathrow_init, | |
577 | }; |