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Commit | Line | Data |
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64201201 | 1 | /* |
3cbee15b | 2 | * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2004-2007 Fabrice Bellard |
3cbee15b | 5 | * Copyright (c) 2007 Jocelyn Mayer |
5fafdf24 | 6 | * |
64201201 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
915cd3a9 AG |
24 | * |
25 | * PCI bus layout on a real G5 (U3 based): | |
26 | * | |
27 | * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] | |
28 | * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] | |
29 | * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] | |
30 | * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) | |
31 | * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) | |
32 | * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] | |
33 | * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] | |
34 | * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] | |
35 | * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] | |
36 | * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] | |
37 | * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) | |
38 | * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] | |
39 | * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] | |
40 | * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) | |
41 | * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) | |
42 | * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) | |
43 | * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] | |
44 | * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] | |
45 | * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] | |
46 | * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] | |
47 | * | |
64201201 | 48 | */ |
87ecb68b PB |
49 | #include "hw.h" |
50 | #include "ppc.h" | |
3cbee15b | 51 | #include "ppc_mac.h" |
28ce5ce6 | 52 | #include "mac_dbdma.h" |
87ecb68b PB |
53 | #include "nvram.h" |
54 | #include "pc.h" | |
55 | #include "pci.h" | |
18e08a55 | 56 | #include "usb-ohci.h" |
87ecb68b PB |
57 | #include "net.h" |
58 | #include "sysemu.h" | |
59 | #include "boards.h" | |
006f3a48 | 60 | #include "fw_cfg.h" |
7fa9ae1a | 61 | #include "escc.h" |
b7169916 | 62 | #include "openpic.h" |
977e1244 | 63 | #include "ide.h" |
ca20cf32 BS |
64 | #include "loader.h" |
65 | #include "elf.h" | |
dc702288 | 66 | #include "kvm.h" |
dc333cd6 | 67 | #include "kvm_ppc.h" |
267002cd | 68 | |
e4bcb14c | 69 | #define MAX_IDE_BUS 2 |
864c136a | 70 | #define VGA_BIOS_SIZE 65536 |
006f3a48 | 71 | #define CFG_ADDR 0xf0000510 |
e4bcb14c | 72 | |
f3902383 BS |
73 | /* debug UniNorth */ |
74 | //#define DEBUG_UNIN | |
75 | ||
76 | #ifdef DEBUG_UNIN | |
001faf32 BS |
77 | #define UNIN_DPRINTF(fmt, ...) \ |
78 | do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) | |
f3902383 | 79 | #else |
001faf32 | 80 | #define UNIN_DPRINTF(fmt, ...) |
f3902383 BS |
81 | #endif |
82 | ||
0aa6a4a2 | 83 | /* UniN device */ |
c227f099 | 84 | static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
0aa6a4a2 | 85 | { |
f3902383 | 86 | UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value); |
0aa6a4a2 FB |
87 | } |
88 | ||
c227f099 | 89 | static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) |
0aa6a4a2 | 90 | { |
f3902383 BS |
91 | uint32_t value; |
92 | ||
93 | value = 0; | |
94 | UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value); | |
95 | ||
96 | return value; | |
0aa6a4a2 FB |
97 | } |
98 | ||
d60efc6b | 99 | static CPUWriteMemoryFunc * const unin_write[] = { |
0aa6a4a2 FB |
100 | &unin_writel, |
101 | &unin_writel, | |
102 | &unin_writel, | |
103 | }; | |
104 | ||
d60efc6b | 105 | static CPUReadMemoryFunc * const unin_read[] = { |
0aa6a4a2 FB |
106 | &unin_readl, |
107 | &unin_readl, | |
108 | &unin_readl, | |
109 | }; | |
110 | ||
513f789f BS |
111 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
112 | { | |
113 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
114 | return 0; | |
115 | } | |
116 | ||
3cbee15b | 117 | /* PowerPC Mac99 hardware initialisation */ |
c227f099 | 118 | static void ppc_core99_init (ram_addr_t ram_size, |
3023f332 | 119 | const char *boot_device, |
3cbee15b JM |
120 | const char *kernel_filename, |
121 | const char *kernel_cmdline, | |
122 | const char *initrd_filename, | |
123 | const char *cpu_model) | |
64201201 | 124 | { |
aaed909a | 125 | CPUState *env = NULL, *envs[MAX_CPUS]; |
5cea8590 | 126 | char *filename; |
e9df014c | 127 | qemu_irq *pic, **openpic_irqs; |
aef445bd | 128 | int unin_memory; |
d5295253 | 129 | int linux_boot, i; |
c227f099 | 130 | ram_addr_t ram_offset, bios_offset, vga_bios_offset; |
b6b8bd18 | 131 | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
46e50e9d | 132 | PCIBus *pci_bus; |
3cbee15b JM |
133 | MacIONVRAMState *nvr; |
134 | int nvram_mem_index; | |
d5295253 | 135 | int vga_bios_size, bios_size; |
7fa9ae1a | 136 | int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index; |
28c5af54 | 137 | int ppc_boot_device; |
f455e98c | 138 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
006f3a48 | 139 | void *fw_cfg; |
28ce5ce6 | 140 | void *dbdma; |
44654490 | 141 | uint8_t *vga_bios_ptr; |
0f921197 | 142 | int machine_arch; |
46e50e9d | 143 | |
64201201 FB |
144 | linux_boot = (kernel_filename != NULL); |
145 | ||
c68ea704 | 146 | /* init CPUs */ |
94fc95cd | 147 | if (cpu_model == NULL) |
46214a27 AF |
148 | #ifdef TARGET_PPC64 |
149 | cpu_model = "970fx"; | |
150 | #else | |
e6bd862b | 151 | cpu_model = "G4"; |
46214a27 | 152 | #endif |
e9df014c | 153 | for (i = 0; i < smp_cpus; i++) { |
aaed909a FB |
154 | env = cpu_init(cpu_model); |
155 | if (!env) { | |
156 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
157 | exit(1); | |
158 | } | |
e9df014c JM |
159 | /* Set time-base frequency to 100 Mhz */ |
160 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
3cbee15b | 161 | #if 0 |
e9df014c | 162 | env->osi_call = vga_osi_call; |
3cbee15b | 163 | #endif |
d84bda46 | 164 | qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
e9df014c JM |
165 | envs[i] = env; |
166 | } | |
c68ea704 | 167 | |
dc702288 AG |
168 | /* Make sure all register sets take effect */ |
169 | cpu_synchronize_state(env); | |
170 | ||
64201201 | 171 | /* allocate RAM */ |
864c136a BS |
172 | ram_offset = qemu_ram_alloc(ram_size); |
173 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
174 | ||
64201201 | 175 | /* allocate and load BIOS */ |
864c136a | 176 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
1192dad8 | 177 | if (bios_name == NULL) |
006f3a48 | 178 | bios_name = PROM_FILENAME; |
5cea8590 | 179 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
006f3a48 BS |
180 | cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); |
181 | ||
182 | /* Load OpenBIOS (ELF) */ | |
5cea8590 | 183 | if (filename) { |
ca20cf32 BS |
184 | bios_size = load_elf(filename, 0, NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
185 | ||
5cea8590 PB |
186 | qemu_free(filename); |
187 | } else { | |
188 | bios_size = -1; | |
189 | } | |
d5295253 | 190 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 | 191 | hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); |
64201201 FB |
192 | exit(1); |
193 | } | |
3b46e624 | 194 | |
d5295253 | 195 | /* allocate and load VGA BIOS */ |
864c136a | 196 | vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE); |
44654490 | 197 | vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset); |
5cea8590 PB |
198 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME); |
199 | if (filename) { | |
200 | vga_bios_size = load_image(filename, vga_bios_ptr + 8); | |
201 | qemu_free(filename); | |
202 | } else { | |
203 | vga_bios_size = -1; | |
204 | } | |
d5295253 FB |
205 | if (vga_bios_size < 0) { |
206 | /* if no bios is present, we can still work */ | |
5cea8590 PB |
207 | fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", |
208 | VGABIOS_FILENAME); | |
d5295253 FB |
209 | vga_bios_size = 0; |
210 | } else { | |
211 | /* set a specific header (XXX: find real Apple format for NDRV | |
212 | drivers) */ | |
44654490 PB |
213 | vga_bios_ptr[0] = 'N'; |
214 | vga_bios_ptr[1] = 'D'; | |
215 | vga_bios_ptr[2] = 'R'; | |
216 | vga_bios_ptr[3] = 'V'; | |
217 | cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size); | |
d5295253 | 218 | vga_bios_size += 8; |
a7b022e0 AG |
219 | |
220 | /* Round to page boundary */ | |
221 | vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) & | |
222 | TARGET_PAGE_MASK; | |
d5295253 | 223 | } |
3b46e624 | 224 | |
b6b8bd18 | 225 | if (linux_boot) { |
513f789f | 226 | uint64_t lowaddr = 0; |
ca20cf32 BS |
227 | int bswap_needed; |
228 | ||
229 | #ifdef BSWAP_NEEDED | |
230 | bswap_needed = 1; | |
231 | #else | |
232 | bswap_needed = 0; | |
233 | #endif | |
b6b8bd18 | 234 | kernel_base = KERNEL_LOAD_ADDR; |
513f789f BS |
235 | |
236 | /* Now we can load the kernel. The first step tries to load the kernel | |
237 | supposing PhysAddr = 0x00000000. If that was wrong the kernel is | |
238 | loaded again, the new PhysAddr being computed from lowaddr. */ | |
ca20cf32 BS |
239 | kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL, |
240 | 1, ELF_MACHINE, 0); | |
513f789f BS |
241 | if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) { |
242 | kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr, | |
ca20cf32 | 243 | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
513f789f BS |
244 | } |
245 | if (kernel_size < 0) | |
246 | kernel_size = load_aout(kernel_filename, kernel_base, | |
ca20cf32 BS |
247 | ram_size - kernel_base, bswap_needed, |
248 | TARGET_PAGE_SIZE); | |
513f789f BS |
249 | if (kernel_size < 0) |
250 | kernel_size = load_image_targphys(kernel_filename, | |
251 | kernel_base, | |
252 | ram_size - kernel_base); | |
b6b8bd18 | 253 | if (kernel_size < 0) { |
2ac71179 | 254 | hw_error("qemu: could not load kernel '%s'\n", kernel_filename); |
b6b8bd18 FB |
255 | exit(1); |
256 | } | |
257 | /* load initrd */ | |
258 | if (initrd_filename) { | |
259 | initrd_base = INITRD_LOAD_ADDR; | |
44654490 PB |
260 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
261 | ram_size - initrd_base); | |
b6b8bd18 | 262 | if (initrd_size < 0) { |
2ac71179 PB |
263 | hw_error("qemu: could not load initial ram disk '%s'\n", |
264 | initrd_filename); | |
b6b8bd18 FB |
265 | exit(1); |
266 | } | |
267 | } else { | |
268 | initrd_base = 0; | |
269 | initrd_size = 0; | |
270 | } | |
6ac0e82d | 271 | ppc_boot_device = 'm'; |
b6b8bd18 FB |
272 | } else { |
273 | kernel_base = 0; | |
274 | kernel_size = 0; | |
275 | initrd_base = 0; | |
276 | initrd_size = 0; | |
28c5af54 JM |
277 | ppc_boot_device = '\0'; |
278 | /* We consider that NewWorld PowerMac never have any floppy drive | |
279 | * For now, OHW cannot boot from the network. | |
280 | */ | |
0d913fdb JM |
281 | for (i = 0; boot_device[i] != '\0'; i++) { |
282 | if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { | |
283 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 284 | break; |
0d913fdb | 285 | } |
28c5af54 JM |
286 | } |
287 | if (ppc_boot_device == '\0') { | |
288 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); | |
289 | exit(1); | |
290 | } | |
b6b8bd18 | 291 | } |
0aa6a4a2 | 292 | |
3cbee15b | 293 | isa_mem_base = 0x80000000; |
aef445bd | 294 | |
3cbee15b JM |
295 | /* Register 8 MB of ISA IO space */ |
296 | isa_mmio_init(0xf2000000, 0x00800000); | |
3b46e624 | 297 | |
3cbee15b | 298 | /* UniN init */ |
1eed09cb | 299 | unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL); |
3cbee15b | 300 | cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); |
47103572 | 301 | |
3cbee15b JM |
302 | openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); |
303 | openpic_irqs[0] = | |
304 | qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
305 | for (i = 0; i < smp_cpus; i++) { | |
306 | /* Mac99 IRQ connection between OpenPIC outputs pins | |
307 | * and PowerPC input pins | |
308 | */ | |
309 | switch (PPC_INPUT(env)) { | |
310 | case PPC_FLAGS_INPUT_6xx: | |
311 | openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); | |
312 | openpic_irqs[i][OPENPIC_OUTPUT_INT] = | |
313 | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; | |
314 | openpic_irqs[i][OPENPIC_OUTPUT_CINT] = | |
315 | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; | |
316 | openpic_irqs[i][OPENPIC_OUTPUT_MCK] = | |
317 | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; | |
318 | /* Not connected ? */ | |
319 | openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; | |
320 | /* Check this */ | |
321 | openpic_irqs[i][OPENPIC_OUTPUT_RESET] = | |
322 | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; | |
323 | break; | |
00af685f | 324 | #if defined(TARGET_PPC64) |
3cbee15b JM |
325 | case PPC_FLAGS_INPUT_970: |
326 | openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); | |
327 | openpic_irqs[i][OPENPIC_OUTPUT_INT] = | |
328 | ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; | |
329 | openpic_irqs[i][OPENPIC_OUTPUT_CINT] = | |
330 | ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; | |
331 | openpic_irqs[i][OPENPIC_OUTPUT_MCK] = | |
332 | ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; | |
333 | /* Not connected ? */ | |
334 | openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; | |
335 | /* Check this */ | |
336 | openpic_irqs[i][OPENPIC_OUTPUT_RESET] = | |
337 | ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; | |
338 | break; | |
00af685f | 339 | #endif /* defined(TARGET_PPC64) */ |
3cbee15b | 340 | default: |
2ac71179 | 341 | hw_error("Bus model not supported on mac99 machine\n"); |
3cbee15b | 342 | exit(1); |
0aa6a4a2 | 343 | } |
3cbee15b JM |
344 | } |
345 | pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); | |
0f921197 AG |
346 | if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { |
347 | /* 970 gets a U3 bus */ | |
348 | pci_bus = pci_pmac_u3_init(pic); | |
349 | machine_arch = ARCH_MAC99_U3; | |
350 | } else { | |
351 | pci_bus = pci_pmac_init(pic); | |
352 | machine_arch = ARCH_MAC99; | |
353 | } | |
3cbee15b | 354 | /* init basic PC hardware */ |
fbe1b595 | 355 | pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size); |
aae9366a | 356 | |
b4b784fe | 357 | escc_mem_index = escc_init(0x80013000, pic[0x25], pic[0x24], |
aeeb69c7 | 358 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); |
cb457d76 AL |
359 | |
360 | for(i = 0; i < nb_nics; i++) | |
07caea31 | 361 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
cb457d76 | 362 | |
e4bcb14c TS |
363 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
364 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
365 | exit(1); | |
366 | } | |
367 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 368 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
e4bcb14c | 369 | } |
28ce5ce6 | 370 | dbdma = DBDMA_init(&dbdma_mem_index); |
77f0435e BS |
371 | pci_cmd646_ide_init(pci_bus, hd, 0); |
372 | ||
3cbee15b JM |
373 | /* cuda also initialize ADB */ |
374 | cuda_init(&cuda_mem_index, pic[0x19]); | |
aae9366a | 375 | |
3cbee15b JM |
376 | adb_kbd_init(&adb_bus); |
377 | adb_mouse_init(&adb_bus); | |
3b46e624 | 378 | |
3b46e624 | 379 | |
4ebcf884 | 380 | macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index, |
77f0435e | 381 | dbdma_mem_index, cuda_mem_index, NULL, 0, NULL, |
4ebcf884 | 382 | escc_mem_index); |
0d92ed30 PB |
383 | |
384 | if (usb_enabled) { | |
5b19d9a2 | 385 | usb_ohci_init_pci(pci_bus, -1); |
0d92ed30 PB |
386 | } |
387 | ||
b6b8bd18 FB |
388 | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
389 | graphic_depth = 15; | |
4f3f238b | 390 | |
3cbee15b | 391 | /* The NewWorld NVRAM is not located in the MacIO device */ |
68af3f24 | 392 | nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1); |
3cbee15b | 393 | pmac_format_nvram_partition(nvr, 0x2000); |
74e91155 | 394 | macio_nvram_map(nvr, 0xFFF04000); |
b6b8bd18 | 395 | /* No PCI init: the BIOS will do it */ |
0aa6a4a2 | 396 | |
006f3a48 BS |
397 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
398 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
399 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
0f921197 | 400 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); |
513f789f BS |
401 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); |
402 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
403 | if (kernel_cmdline) { | |
404 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
3c178e72 | 405 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
513f789f BS |
406 | } else { |
407 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
408 | } | |
409 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); | |
410 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
411 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); | |
10696b4f BS |
412 | |
413 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); | |
414 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); | |
415 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); | |
416 | ||
dc333cd6 AG |
417 | if (kvm_enabled()) { |
418 | #ifdef CONFIG_KVM | |
419 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); | |
420 | #endif | |
421 | } else { | |
422 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); | |
423 | } | |
424 | ||
513f789f | 425 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
aae9366a | 426 | } |
0aa6a4a2 | 427 | |
f80f9ec9 | 428 | static QEMUMachine core99_machine = { |
4b32e168 AL |
429 | .name = "mac99", |
430 | .desc = "Mac99 based PowerMAC", | |
431 | .init = ppc_core99_init, | |
3d878caa | 432 | .max_cpus = MAX_CPUS, |
46214a27 AF |
433 | #ifdef TARGET_PPC64 |
434 | .is_default = 1, | |
435 | #endif | |
0aa6a4a2 | 436 | }; |
f80f9ec9 AL |
437 | |
438 | static void core99_machine_init(void) | |
439 | { | |
440 | qemu_register_machine(&core99_machine); | |
441 | } | |
442 | ||
443 | machine_init(core99_machine_init); |