[mirror_qemu.git] / hw / ppc_oldworld.c

/*
 * QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "ppc_mac.h"

/* temporary frame buffer OSI calls for the video.x driver. The right
   solution is to modify the driver to use VGA PCI I/Os */
/* XXX: to be removed. This is no way related to emulation */
static int vga_osi_call (CPUState *env)
{
    static int vga_vbl_enabled;
    int linesize;

    //    printf("osi_call R5=%d\n", env->gpr[5]);

    /* same handler as PearPC, coming from the original MOL video
       driver. */
    switch(env->gpr[5]) {
    case 4:
        break;
    case 28: /* set_vmode */
        if (env->gpr[6] != 1 || env->gpr[7] != 0)
            env->gpr[3] = 1;
        else
            env->gpr[3] = 0;
        break;
    case 29: /* get_vmode_info */
        if (env->gpr[6] != 0) {
            if (env->gpr[6] != 1 || env->gpr[7] != 0) {
                env->gpr[3] = 1;
                break;
            }
        }
        env->gpr[3] = 0;
        env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
        env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
        env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
        env->gpr[7] = 85 << 16; /* refresh rate */
        env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
        linesize = ((graphic_depth + 7) >> 3) * graphic_width;
        linesize = (linesize + 3) & ~3;
        env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
        break;
    case 31: /* set_video power */
        env->gpr[3] = 0;
        break;
    case 39: /* video_ctrl */
        if (env->gpr[6] == 0 || env->gpr[6] == 1)
            vga_vbl_enabled = env->gpr[6];
        env->gpr[3] = 0;
        break;
    case 47:
        break;
    case 59: /* set_color */
        /* R6 = index, R7 = RGB */
        env->gpr[3] = 0;
        break;
    case 64: /* get color */
        /* R6 = index */
        env->gpr[3] = 0;
        break;
    case 116: /* set hwcursor */
        /* R6 = x, R7 = y, R8 = visible, R9 = data */
        break;
    default:
        fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
        break;
    }

    return 1; /* osi_call handled */
}

static void ppc_heathrow_init (int ram_size, int vga_ram_size,
                               const char *boot_device, DisplayState *ds,
                               const char **fd_filename, int snapshot,
                               const char *kernel_filename,
                               const char *kernel_cmdline,
                               const char *initrd_filename,
                               const char *cpu_model)
{
    CPUState *env, *envs[MAX_CPUS];
    char buf[1024];
    qemu_irq *pic, **heathrow_irqs;
    nvram_t nvram;
    m48t59_t *m48t59;
    int linux_boot, i;
    unsigned long bios_offset, vga_bios_offset;
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
    ppc_def_t *def;
    PCIBus *pci_bus;
    MacIONVRAMState *nvr;
    int vga_bios_size, bios_size;
    qemu_irq *dummy_irq;
    int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
    int ppc_boot_device = boot_device[0];

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    env = cpu_init();
    if (cpu_model == NULL)
        cpu_model = "default";
    ppc_find_by_name(cpu_model, &def);
    if (def == NULL) {
        cpu_abort(env, "Unable to find PowerPC CPU definition\n");
    }
    for (i = 0; i < smp_cpus; i++) {
        cpu_ppc_register(env, def);
        cpu_ppc_reset(env);
        /* Set time-base frequency to 100 Mhz */
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
        env->osi_call = vga_osi_call;
        qemu_register_reset(&cpu_ppc_reset, env);
        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
        envs[i] = env;
    }
    if (env->nip < 0xFFF80000) {
        /* Special test for PowerPC 601:
         * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
         * But the NVRAM is located at 0xFFF04000...
         */
        cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
    }

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    /* allocate and load BIOS */
    bios_offset = ram_size + vga_ram_size;
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    bios_size = load_image(buf, phys_ram_base + bios_offset);
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
        exit(1);
    }
    bios_size = (bios_size + 0xfff) & ~0xfff;
    if (bios_size > 0x00080000) {
        /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
        cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
    }
    cpu_register_physical_memory((uint32_t)(-bios_size),
                                 bios_size, bios_offset | IO_MEM_ROM);

    /* allocate and load VGA BIOS */
    vga_bios_offset = bios_offset + bios_size;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
    if (vga_bios_size < 0) {
        /* if no bios is present, we can still work */
        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
        vga_bios_size = 0;
    } else {
        /* set a specific header (XXX: find real Apple format for NDRV
           drivers) */
        phys_ram_base[vga_bios_offset] = 'N';
        phys_ram_base[vga_bios_offset + 1] = 'D';
        phys_ram_base[vga_bios_offset + 2] = 'R';
        phys_ram_base[vga_bios_offset + 3] = 'V';
        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
                     vga_bios_size);
        vga_bios_size += 8;
    }
    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;

    if (linux_boot) {
        kernel_base = KERNEL_LOAD_ADDR;
        /* now we can load the kernel */
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
        if (kernel_size < 0) {
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
                      kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image(initrd_filename,
                                     phys_ram_base + initrd_base);
            if (initrd_size < 0) {
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
                          initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
        ppc_boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
    }

    isa_mem_base = 0x80000000;
    
    /* Register 2 MB of ISA IO space */
    isa_mmio_init(0xfe000000, 0x00200000);

    /* XXX: we register only 1 output pin for heathrow PIC */
    heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
    heathrow_irqs[0] =
        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
    /* Connect the heathrow PIC outputs to the 6xx bus */
    for (i = 0; i < smp_cpus; i++) {
        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_6xx:
            heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
            heathrow_irqs[i][0] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            break;
        default:
            cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
            exit(1);
        }
    }

    /* init basic PC hardware */
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
        cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
        exit(1);
    }
    pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
    pci_bus = pci_grackle_init(0xfec00000, pic);
    pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
                 ram_size, vga_ram_size,
                 vga_bios_offset, vga_bios_size);
    
    /* XXX: suppress that */
    dummy_irq = i8259_init(NULL);

    /* XXX: use Mac Serial port */
    serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
    
    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
        pci_nic_init(pci_bus, &nd_table[i], -1);
    }
    
    pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);

    /* cuda also initialize ADB */
    cuda_init(&cuda_mem_index, pic[0x12]);

    adb_kbd_init(&adb_bus);
    adb_mouse_init(&adb_bus);
    
    nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
    pmac_format_nvram_partition(nvr, 0x2000);

    dbdma_init(&dbdma_mem_index);
    
    macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
               cuda_mem_index, nvr, 0, NULL);

    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, 3, -1);
    }

    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
        graphic_depth = 15;

    m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
    nvram.opaque = m48t59;
    nvram.read_fn = &m48t59_read;
    nvram.write_fn = &m48t59_write;
    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
                         ppc_boot_device, kernel_base, kernel_size,
                         kernel_cmdline,
                         initrd_base, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);
    /* No PCI init: the BIOS will do it */

    /* Special port to get debug messages from Open-Firmware */
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
}

QEMUMachine heathrow_machine = {
    "g3bw",
    "Heathrow based PowerMAC",
    ppc_heathrow_init,
};
Commit	Line	Data
3cbee15b JM	1	/*
	2	* QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
	3	*
	4	* Copyright (c) 2004-2007 Fabrice Bellard
	5	* Copyright (c) 2007 Jocelyn Mayer
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "vl.h"
	26	#include "ppc_mac.h"
	27
	28	/* temporary frame buffer OSI calls for the video.x driver. The right
	29	solution is to modify the driver to use VGA PCI I/Os */
	30	/* XXX: to be removed. This is no way related to emulation */
	31	static int vga_osi_call (CPUState *env)
	32	{
	33	static int vga_vbl_enabled;
	34	int linesize;
	35
	36	// printf("osi_call R5=%d\n", env->gpr[5]);
	37
	38	/* same handler as PearPC, coming from the original MOL video
	39	driver. */
	40	switch(env->gpr[5]) {
	41	case 4:
	42	break;
	43	case 28: /* set_vmode */
	44	if (env->gpr[6] != 1 \|\| env->gpr[7] != 0)
	45	env->gpr[3] = 1;
	46	else
	47	env->gpr[3] = 0;
	48	break;
	49	case 29: /* get_vmode_info */
	50	if (env->gpr[6] != 0) {
	51	if (env->gpr[6] != 1 \|\| env->gpr[7] != 0) {
	52	env->gpr[3] = 1;
	53	break;
	54	}
	55	}
	56	env->gpr[3] = 0;
	57	env->gpr[4] = (1 << 16) \| 1; /* num_vmodes, cur_vmode */
	58	env->gpr[5] = (1 << 16) \| 0; /* num_depths, cur_depth_mode */
	59	env->gpr[6] = (graphic_width << 16) \| graphic_height; /* w, h */
	60	env->gpr[7] = 85 << 16; /* refresh rate */
	61	env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
	62	linesize = ((graphic_depth + 7) >> 3) * graphic_width;
	63	linesize = (linesize + 3) & ~3;
	64	env->gpr[9] = (linesize << 16) \| 0; /* row_bytes, offset */
65	break;
66	case 31: /* set_video power */
67	env->gpr[3] = 0;
68	break;
69	case 39: /* video_ctrl */
70	if (env->gpr[6] == 0 \|\| env->gpr[6] == 1)
71	vga_vbl_enabled = env->gpr[6];
72	env->gpr[3] = 0;
73	break;
74	case 47:
75	break;
76	case 59: /* set_color */
77	/* R6 = index, R7 = RGB */
78	env->gpr[3] = 0;
79	break;
80	case 64: /* get color */
81	/* R6 = index */
82	env->gpr[3] = 0;
83	break;
84	case 116: /* set hwcursor */
85	/* R6 = x, R7 = y, R8 = visible, R9 = data */
86	break;
87	default:
88	fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
89	break;
90	}
91
92	return 1; /* osi_call handled */
93	}
94
6ac0e82d AZ	95	static void ppc_heathrow_init (int ram_size, int vga_ram_size,
	96	const char boot_device, DisplayState ds,
	97	const char **fd_filename, int snapshot,
3cbee15b JM	98	const char *kernel_filename,
	99	const char *kernel_cmdline,
	100	const char *initrd_filename,
	101	const char *cpu_model)
	102	{
	103	CPUState env, envs[MAX_CPUS];
	104	char buf[1024];
	105	qemu_irq pic, *heathrow_irqs;
	106	nvram_t nvram;
	107	m48t59_t *m48t59;
	108	int linux_boot, i;
	109	unsigned long bios_offset, vga_bios_offset;
	110	uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
	111	ppc_def_t *def;
	112	PCIBus *pci_bus;
	113	MacIONVRAMState *nvr;
	114	int vga_bios_size, bios_size;
	115	qemu_irq *dummy_irq;
	116	int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
6ac0e82d	117	int ppc_boot_device = boot_device[0];
3cbee15b JM	118
	119	linux_boot = (kernel_filename != NULL);
	120
	121	/* init CPUs */
	122	env = cpu_init();
	123	if (cpu_model == NULL)
	124	cpu_model = "default";
	125	ppc_find_by_name(cpu_model, &def);
	126	if (def == NULL) {
	127	cpu_abort(env, "Unable to find PowerPC CPU definition\n");
	128	}
	129	for (i = 0; i < smp_cpus; i++) {
	130	cpu_ppc_register(env, def);
	131	cpu_ppc_reset(env);
	132	/* Set time-base frequency to 100 Mhz */
	133	cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
	134	env->osi_call = vga_osi_call;
	135	qemu_register_reset(&cpu_ppc_reset, env);
	136	register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
	137	envs[i] = env;
	138	}
4c823cff JM	139	if (env->nip < 0xFFF80000) {
	140	/* Special test for PowerPC 601:
	141	* the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
	142	* But the NVRAM is located at 0xFFF04000...
	143	*/
	144	cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
	145	}
3cbee15b JM	146
	147	/* allocate RAM */
	148	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
	149
	150	/* allocate and load BIOS */
	151	bios_offset = ram_size + vga_ram_size;
	152	if (bios_name == NULL)
	153	bios_name = BIOS_FILENAME;
	154	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
	155	bios_size = load_image(buf, phys_ram_base + bios_offset);
	156	if (bios_size < 0 \|\| bios_size > BIOS_SIZE) {
	157	cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
	158	exit(1);
	159	}
	160	bios_size = (bios_size + 0xfff) & ~0xfff;
4c823cff JM	161	if (bios_size > 0x00080000) {
	162	/* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
	163	cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
	164	}
3cbee15b JM	165	cpu_register_physical_memory((uint32_t)(-bios_size),
	166	bios_size, bios_offset \| IO_MEM_ROM);
	167
	168	/* allocate and load VGA BIOS */
	169	vga_bios_offset = bios_offset + bios_size;
	170	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
	171	vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
	172	if (vga_bios_size < 0) {
	173	/* if no bios is present, we can still work */
	174	fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
	175	vga_bios_size = 0;
	176	} else {
	177	/* set a specific header (XXX: find real Apple format for NDRV
	178	drivers) */
	179	phys_ram_base[vga_bios_offset] = 'N';
	180	phys_ram_base[vga_bios_offset + 1] = 'D';
	181	phys_ram_base[vga_bios_offset + 2] = 'R';
	182	phys_ram_base[vga_bios_offset + 3] = 'V';
	183	cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
	184	vga_bios_size);
	185	vga_bios_size += 8;
	186	}
	187	vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
	188
	189	if (linux_boot) {
	190	kernel_base = KERNEL_LOAD_ADDR;
	191	/* now we can load the kernel */
	192	kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
	193	if (kernel_size < 0) {
	194	cpu_abort(env, "qemu: could not load kernel '%s'\n",
	195	kernel_filename);
	196	exit(1);
	197	}
	198	/* load initrd */
	199	if (initrd_filename) {
	200	initrd_base = INITRD_LOAD_ADDR;
	201	initrd_size = load_image(initrd_filename,
	202	phys_ram_base + initrd_base);
	203	if (initrd_size < 0) {
	204	cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
	205	initrd_filename);
	206	exit(1);
	207	}
	208	} else {
	209	initrd_base = 0;
	210	initrd_size = 0;
	211	}
6ac0e82d	212	ppc_boot_device = 'm';
3cbee15b JM	213	} else {
	214	kernel_base = 0;
	215	kernel_size = 0;
	216	initrd_base = 0;
	217	initrd_size = 0;
	218	}
	219
	220	isa_mem_base = 0x80000000;
	221
	222	/* Register 2 MB of ISA IO space */
	223	isa_mmio_init(0xfe000000, 0x00200000);
	224
	225	/* XXX: we register only 1 output pin for heathrow PIC */
	226	heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
	227	heathrow_irqs[0] =
	228	qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
	229	/* Connect the heathrow PIC outputs to the 6xx bus */
	230	for (i = 0; i < smp_cpus; i++) {
	231	switch (PPC_INPUT(env)) {
	232	case PPC_FLAGS_INPUT_6xx:
	233	heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
	234	heathrow_irqs[i][0] =
	235	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	236	break;
	237	default:
	238	cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
	239	exit(1);
	240	}
	241	}
	242
	243	/* init basic PC hardware */
	244	if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
	245	cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
	246	exit(1);
	247	}
	248	pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
	249	pci_bus = pci_grackle_init(0xfec00000, pic);
	250	pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
	251	ram_size, vga_ram_size,
	252	vga_bios_offset, vga_bios_size);
	253
	254	/* XXX: suppress that */
	255	dummy_irq = i8259_init(NULL);
	256
	257	/* XXX: use Mac Serial port */
	258	serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
	259
	260	for(i = 0; i < nb_nics; i++) {
	261	if (!nd_table[i].model)
	262	nd_table[i].model = "ne2k_pci";
	263	pci_nic_init(pci_bus, &nd_table[i], -1);
	264	}
	265
	266	pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
	267
	268	/* cuda also initialize ADB */
	269	cuda_init(&cuda_mem_index, pic[0x12]);
	270
	271	adb_kbd_init(&adb_bus);
	272	adb_mouse_init(&adb_bus);
	273
74e91155	274	nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
3cbee15b JM	275	pmac_format_nvram_partition(nvr, 0x2000);
	276
	277	dbdma_init(&dbdma_mem_index);
	278
	279	macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
74e91155	280	cuda_mem_index, nvr, 0, NULL);
3cbee15b JM	281
	282	if (usb_enabled) {
	283	usb_ohci_init_pci(pci_bus, 3, -1);
	284	}
	285
	286	if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
	287	graphic_depth = 15;
	288
	289	m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
	290	nvram.opaque = m48t59;
	291	nvram.read_fn = &m48t59_read;
	292	nvram.write_fn = &m48t59_write;
6ac0e82d AZ	293	PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
6ac0e82d AZ	294	ppc_boot_device, kernel_base, kernel_size,
3cbee15b JM	295	kernel_cmdline,
	296	initrd_base, initrd_size,
	297	/* XXX: need an option to load a NVRAM image */
	298	0,
	299	graphic_width, graphic_height, graphic_depth);
	300	/* No PCI init: the BIOS will do it */
	301
	302	/* Special port to get debug messages from Open-Firmware */
	303	register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
	304	}
	305
	306	QEMUMachine heathrow_machine = {
	307	"g3bw",
	308	"Heathrow based PowerMAC",
	309	ppc_heathrow_init,
	310	};