[mirror_qemu.git] / hw / ppc_oldworld.c

/*
 * QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc.h"
#include "ppc_mac.h"
#include "nvram.h"
#include "pc.h"
#include "sysemu.h"
#include "net.h"
#include "isa.h"
#include "pci.h"
#include "boards.h"

#define MAX_IDE_BUS 2

/* temporary frame buffer OSI calls for the video.x driver. The right
   solution is to modify the driver to use VGA PCI I/Os */
/* XXX: to be removed. This is no way related to emulation */
static int vga_osi_call (CPUState *env)
{
    static int vga_vbl_enabled;
    int linesize;

    //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));

    /* same handler as PearPC, coming from the original MOL video
       driver. */
    switch(env->gpr[5]) {
    case 4:
        break;
    case 28: /* set_vmode */
        if (env->gpr[6] != 1 || env->gpr[7] != 0)
            env->gpr[3] = 1;
        else
            env->gpr[3] = 0;
        break;
    case 29: /* get_vmode_info */
        if (env->gpr[6] != 0) {
            if (env->gpr[6] != 1 || env->gpr[7] != 0) {
                env->gpr[3] = 1;
                break;
            }
        }
        env->gpr[3] = 0;
        env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
        env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
        env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
        env->gpr[7] = 85 << 16; /* refresh rate */
        env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
        linesize = ((graphic_depth + 7) >> 3) * graphic_width;
        linesize = (linesize + 3) & ~3;
        env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
        break;
    case 31: /* set_video power */
        env->gpr[3] = 0;
        break;
    case 39: /* video_ctrl */
        if (env->gpr[6] == 0 || env->gpr[6] == 1)
            vga_vbl_enabled = env->gpr[6];
        env->gpr[3] = 0;
        break;
    case 47:
        break;
    case 59: /* set_color */
        /* R6 = index, R7 = RGB */
        env->gpr[3] = 0;
        break;
    case 64: /* get color */
        /* R6 = index */
        env->gpr[3] = 0;
        break;
    case 116: /* set hwcursor */
        /* R6 = x, R7 = y, R8 = visible, R9 = data */
        break;
    default:
        fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
                ppc_dump_gpr(env, 5));
        break;
    }

    return 1; /* osi_call handled */
}

static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
                               const char *boot_device, DisplayState *ds,
                               const char *kernel_filename,
                               const char *kernel_cmdline,
                               const char *initrd_filename,
                               const char *cpu_model)
{
    CPUState *env = NULL, *envs[MAX_CPUS];
    char buf[1024];
    qemu_irq *pic, **heathrow_irqs;
    nvram_t nvram;
    m48t59_t *m48t59;
    int linux_boot, i;
    unsigned long bios_offset, vga_bios_offset;
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
    PCIBus *pci_bus;
    MacIONVRAMState *nvr;
    int vga_bios_size, bios_size;
    qemu_irq *dummy_irq;
    int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
    int ide_mem_index[2];
    int ppc_boot_device;
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    int index;

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (cpu_model == NULL)
        cpu_model = "G3";
    for (i = 0; i < smp_cpus; i++) {
        env = cpu_init(cpu_model);
        if (!env) {
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
            exit(1);
        }
        /* Set time-base frequency to 100 Mhz */
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
        env->osi_call = vga_osi_call;
        qemu_register_reset(&cpu_ppc_reset, env);
        envs[i] = env;
    }
    if (env->nip < 0xFFF80000) {
        /* Special test for PowerPC 601:
         * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
         * But the NVRAM is located at 0xFFF04000...
         */
        cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
    }

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    /* allocate and load BIOS */
    bios_offset = ram_size + vga_ram_size;
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    bios_size = load_image(buf, phys_ram_base + bios_offset);
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
        exit(1);
    }
    bios_size = (bios_size + 0xfff) & ~0xfff;
    if (bios_size > 0x00080000) {
        /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
        cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
    }
    cpu_register_physical_memory((uint32_t)(-bios_size),
                                 bios_size, bios_offset | IO_MEM_ROM);

    /* allocate and load VGA BIOS */
    vga_bios_offset = bios_offset + bios_size;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
    if (vga_bios_size < 0) {
        /* if no bios is present, we can still work */
        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
        vga_bios_size = 0;
    } else {
        /* set a specific header (XXX: find real Apple format for NDRV
           drivers) */
        phys_ram_base[vga_bios_offset] = 'N';
        phys_ram_base[vga_bios_offset + 1] = 'D';
        phys_ram_base[vga_bios_offset + 2] = 'R';
        phys_ram_base[vga_bios_offset + 3] = 'V';
        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
                     vga_bios_size);
        vga_bios_size += 8;
    }
    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;

    if (linux_boot) {
        kernel_base = KERNEL_LOAD_ADDR;
        /* now we can load the kernel */
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
        if (kernel_size < 0) {
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
                      kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image(initrd_filename,
                                     phys_ram_base + initrd_base);
            if (initrd_size < 0) {
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
                          initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
        ppc_boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
        ppc_boot_device = '\0';
        for (i = 0; boot_device[i] != '\0'; i++) {
            /* TOFIX: for now, the second IDE channel is not properly
             *        used by OHW. The Mac floppy disk are not emulated.
             *        For now, OHW cannot boot from the network.
             */
#if 0
            if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
                ppc_boot_device = boot_device[i];
                break;
            }
#else
            if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
                ppc_boot_device = boot_device[i];
                break;
            }
#endif
        }
        if (ppc_boot_device == '\0') {
            fprintf(stderr, "No valid boot device for Mac99 machine\n");
            exit(1);
        }
    }

    isa_mem_base = 0x80000000;

    /* Register 2 MB of ISA IO space */
    isa_mmio_init(0xfe000000, 0x00200000);

    /* XXX: we register only 1 output pin for heathrow PIC */
    heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
    heathrow_irqs[0] =
        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
    /* Connect the heathrow PIC outputs to the 6xx bus */
    for (i = 0; i < smp_cpus; i++) {
        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_6xx:
            heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
            heathrow_irqs[i][0] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            break;
        default:
            cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
            exit(1);
        }
    }

    /* init basic PC hardware */
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
        cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
        exit(1);
    }
    pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
    pci_bus = pci_grackle_init(0xfec00000, pic);
    pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
                 ram_size, vga_ram_size,
                 vga_bios_offset, vga_bios_size);

    /* XXX: suppress that */
    dummy_irq = i8259_init(NULL);

    /* XXX: use Mac Serial port */
    serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);

    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
        pci_nic_init(pci_bus, &nd_table[i], -1);
    }

    /* First IDE channel is a CMD646 on the PCI bus */

    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
        fprintf(stderr, "qemu: too many IDE bus\n");
        exit(1);
    }
    index = drive_get_index(IF_IDE, 0, 0);
    if (index == -1)
        hd[0] = NULL;
    else
        hd[0] =  drives_table[index].bdrv;
    index = drive_get_index(IF_IDE, 0, 1);
    if (index == -1)
        hd[1] = NULL;
    else
        hd[1] =  drives_table[index].bdrv;
    hd[3] = hd[2] = NULL;
    pci_cmd646_ide_init(pci_bus, hd, 0);

    /* Second IDE channel is a MAC IDE on the MacIO bus */
    index = drive_get_index(IF_IDE, 1, 0);
    if (index == -1)
        hd[0] = NULL;
    else
        hd[0] =  drives_table[index].bdrv;
    index = drive_get_index(IF_IDE, 1, 1);
    if (index == -1)
        hd[1] = NULL;
    else
        hd[1] =  drives_table[index].bdrv;
    ide_mem_index[0] = -1;
    ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);

    /* cuda also initialize ADB */
    cuda_init(&cuda_mem_index, pic[0x12]);

    adb_kbd_init(&adb_bus);
    adb_mouse_init(&adb_bus);

    nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
    pmac_format_nvram_partition(nvr, 0x2000);

    dbdma_init(&dbdma_mem_index);

    macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
               cuda_mem_index, nvr, 2, ide_mem_index);

    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, 3, -1);
    }

    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
        graphic_depth = 15;

    m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
    nvram.opaque = m48t59;
    nvram.read_fn = &m48t59_read;
    nvram.write_fn = &m48t59_write;
    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
                         ppc_boot_device, kernel_base, kernel_size,
                         kernel_cmdline,
                         initrd_base, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);
    /* No PCI init: the BIOS will do it */

    /* Special port to get debug messages from Open-Firmware */
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
}

QEMUMachine heathrow_machine = {
    .name = "g3bw",
    .desc = "Heathrow based PowerMAC",
    .init = ppc_heathrow_init,
    .ram_require = BIOS_SIZE + VGA_RAM_SIZE,
    .max_cpus = MAX_CPUS,
};
Commit	Line	Data
3cbee15b JM	1	/*
	2	* QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
	3	*
	4	* Copyright (c) 2004-2007 Fabrice Bellard
	5	* Copyright (c) 2007 Jocelyn Mayer
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
87ecb68b PB	25	#include "hw.h"
87ecb68b PB	26	#include "ppc.h"
3cbee15b	27	#include "ppc_mac.h"
87ecb68b PB	28	#include "nvram.h"
	29	#include "pc.h"
	30	#include "sysemu.h"
	31	#include "net.h"
	32	#include "isa.h"
	33	#include "pci.h"
	34	#include "boards.h"
3cbee15b	35
e4bcb14c TS	36	#define MAX_IDE_BUS 2
e4bcb14c TS	37
3cbee15b JM	38	/* temporary frame buffer OSI calls for the video.x driver. The right
	39	solution is to modify the driver to use VGA PCI I/Os */
	40	/* XXX: to be removed. This is no way related to emulation */
	41	static int vga_osi_call (CPUState *env)
	42	{
	43	static int vga_vbl_enabled;
	44	int linesize;
	45
aae9366a	46	// printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
3cbee15b JM	47
	48	/* same handler as PearPC, coming from the original MOL video
	49	driver. */
	50	switch(env->gpr[5]) {
	51	case 4:
	52	break;
	53	case 28: /* set_vmode */
	54	if (env->gpr[6] != 1 \|\| env->gpr[7] != 0)
	55	env->gpr[3] = 1;
	56	else
	57	env->gpr[3] = 0;
	58	break;
	59	case 29: /* get_vmode_info */
	60	if (env->gpr[6] != 0) {
	61	if (env->gpr[6] != 1 \|\| env->gpr[7] != 0) {
	62	env->gpr[3] = 1;
	63	break;
	64	}
	65	}
	66	env->gpr[3] = 0;
	67	env->gpr[4] = (1 << 16) \| 1; /* num_vmodes, cur_vmode */
	68	env->gpr[5] = (1 << 16) \| 0; /* num_depths, cur_depth_mode */
	69	env->gpr[6] = (graphic_width << 16) \| graphic_height; /* w, h */
	70	env->gpr[7] = 85 << 16; /* refresh rate */
	71	env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
	72	linesize = ((graphic_depth + 7) >> 3) * graphic_width;
	73	linesize = (linesize + 3) & ~3;
	74	env->gpr[9] = (linesize << 16) \| 0; /* row_bytes, offset */
	75	break;
	76	case 31: /* set_video power */
	77	env->gpr[3] = 0;
	78	break;
	79	case 39: /* video_ctrl */
	80	if (env->gpr[6] == 0 \|\| env->gpr[6] == 1)
	81	vga_vbl_enabled = env->gpr[6];
	82	env->gpr[3] = 0;
	83	break;
	84	case 47:
	85	break;
	86	case 59: /* set_color */
	87	/* R6 = index, R7 = RGB */
	88	env->gpr[3] = 0;
	89	break;
	90	case 64: /* get color */
	91	/* R6 = index */
	92	env->gpr[3] = 0;
	93	break;
	94	case 116: /* set hwcursor */
	95	/* R6 = x, R7 = y, R8 = visible, R9 = data */
	96	break;
	97	default:
aae9366a JM	98	fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
aae9366a JM	99	ppc_dump_gpr(env, 5));
3cbee15b JM	100	break;
	101	}
	102
	103	return 1; /* osi_call handled */
	104	}
	105
00f82b8a	106	static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
6ac0e82d	107	const char boot_device, DisplayState ds,
3cbee15b JM	108	const char *kernel_filename,
	109	const char *kernel_cmdline,
	110	const char *initrd_filename,
	111	const char *cpu_model)
	112	{
aaed909a	113	CPUState env = NULL, envs[MAX_CPUS];
3cbee15b JM	114	char buf[1024];
	115	qemu_irq pic, *heathrow_irqs;
	116	nvram_t nvram;
	117	m48t59_t *m48t59;
	118	int linux_boot, i;
	119	unsigned long bios_offset, vga_bios_offset;
	120	uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
3cbee15b JM	121	PCIBus *pci_bus;
	122	MacIONVRAMState *nvr;
	123	int vga_bios_size, bios_size;
	124	qemu_irq *dummy_irq;
	125	int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
0d913fdb	126	int ide_mem_index[2];
28c5af54	127	int ppc_boot_device;
e4bcb14c TS	128	BlockDriverState hd[MAX_IDE_BUS MAX_IDE_DEVS];
e4bcb14c TS	129	int index;
3cbee15b JM	130
	131	linux_boot = (kernel_filename != NULL);
	132
	133	/* init CPUs */
3cbee15b	134	if (cpu_model == NULL)
f2fde45a	135	cpu_model = "G3";
3cbee15b	136	for (i = 0; i < smp_cpus; i++) {
aaed909a FB	137	env = cpu_init(cpu_model);
	138	if (!env) {
	139	fprintf(stderr, "Unable to find PowerPC CPU definition\n");
	140	exit(1);
	141	}
3cbee15b JM	142	/* Set time-base frequency to 100 Mhz */
	143	cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
	144	env->osi_call = vga_osi_call;
	145	qemu_register_reset(&cpu_ppc_reset, env);
3cbee15b JM	146	envs[i] = env;
3cbee15b JM	147	}
4c823cff JM	148	if (env->nip < 0xFFF80000) {
	149	/* Special test for PowerPC 601:
	150	* the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
	151	* But the NVRAM is located at 0xFFF04000...
	152	*/
	153	cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
	154	}
3cbee15b JM	155
	156	/* allocate RAM */
	157	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
	158
	159	/* allocate and load BIOS */
	160	bios_offset = ram_size + vga_ram_size;
	161	if (bios_name == NULL)
	162	bios_name = BIOS_FILENAME;
	163	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
	164	bios_size = load_image(buf, phys_ram_base + bios_offset);
	165	if (bios_size < 0 \|\| bios_size > BIOS_SIZE) {
	166	cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
	167	exit(1);
	168	}
	169	bios_size = (bios_size + 0xfff) & ~0xfff;
4c823cff JM	170	if (bios_size > 0x00080000) {
	171	/* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
	172	cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
	173	}
3cbee15b JM	174	cpu_register_physical_memory((uint32_t)(-bios_size),
	175	bios_size, bios_offset \| IO_MEM_ROM);
	176
	177	/* allocate and load VGA BIOS */
	178	vga_bios_offset = bios_offset + bios_size;
	179	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
	180	vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
	181	if (vga_bios_size < 0) {
	182	/* if no bios is present, we can still work */
	183	fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
	184	vga_bios_size = 0;
	185	} else {
	186	/* set a specific header (XXX: find real Apple format for NDRV
	187	drivers) */
	188	phys_ram_base[vga_bios_offset] = 'N';
	189	phys_ram_base[vga_bios_offset + 1] = 'D';
	190	phys_ram_base[vga_bios_offset + 2] = 'R';
	191	phys_ram_base[vga_bios_offset + 3] = 'V';
	192	cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
	193	vga_bios_size);
	194	vga_bios_size += 8;
	195	}
	196	vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
	197
	198	if (linux_boot) {
	199	kernel_base = KERNEL_LOAD_ADDR;
	200	/* now we can load the kernel */
	201	kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
	202	if (kernel_size < 0) {
	203	cpu_abort(env, "qemu: could not load kernel '%s'\n",
	204	kernel_filename);
	205	exit(1);
	206	}
	207	/* load initrd */
	208	if (initrd_filename) {
	209	initrd_base = INITRD_LOAD_ADDR;
	210	initrd_size = load_image(initrd_filename,
	211	phys_ram_base + initrd_base);
	212	if (initrd_size < 0) {
	213	cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
	214	initrd_filename);
	215	exit(1);
	216	}
	217	} else {
	218	initrd_base = 0;
	219	initrd_size = 0;
	220	}
6ac0e82d	221	ppc_boot_device = 'm';
3cbee15b JM	222	} else {
	223	kernel_base = 0;
	224	kernel_size = 0;
	225	initrd_base = 0;
	226	initrd_size = 0;
28c5af54	227	ppc_boot_device = '\0';
0d913fdb	228	for (i = 0; boot_device[i] != '\0'; i++) {
28c5af54	229	/* TOFIX: for now, the second IDE channel is not properly
0d913fdb	230	* used by OHW. The Mac floppy disk are not emulated.
28c5af54 JM	231	* For now, OHW cannot boot from the network.
	232	*/
	233	#if 0
0d913fdb JM	234	if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
0d913fdb JM	235	ppc_boot_device = boot_device[i];
28c5af54	236	break;
0d913fdb	237	}
28c5af54	238	#else
0d913fdb JM	239	if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
0d913fdb JM	240	ppc_boot_device = boot_device[i];
28c5af54	241	break;
0d913fdb	242	}
28c5af54 JM	243	#endif
	244	}
	245	if (ppc_boot_device == '\0') {
	246	fprintf(stderr, "No valid boot device for Mac99 machine\n");
	247	exit(1);
	248	}
3cbee15b JM	249	}
	250
	251	isa_mem_base = 0x80000000;
aae9366a	252
3cbee15b JM	253	/* Register 2 MB of ISA IO space */
	254	isa_mmio_init(0xfe000000, 0x00200000);
	255
	256	/* XXX: we register only 1 output pin for heathrow PIC */
	257	heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
	258	heathrow_irqs[0] =
	259	qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
	260	/* Connect the heathrow PIC outputs to the 6xx bus */
	261	for (i = 0; i < smp_cpus; i++) {
	262	switch (PPC_INPUT(env)) {
	263	case PPC_FLAGS_INPUT_6xx:
	264	heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
	265	heathrow_irqs[i][0] =
	266	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	267	break;
	268	default:
	269	cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
	270	exit(1);
	271	}
	272	}
	273
	274	/* init basic PC hardware */
	275	if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
	276	cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
	277	exit(1);
	278	}
	279	pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
	280	pci_bus = pci_grackle_init(0xfec00000, pic);
	281	pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
	282	ram_size, vga_ram_size,
	283	vga_bios_offset, vga_bios_size);
aae9366a	284
3cbee15b JM	285	/* XXX: suppress that */
	286	dummy_irq = i8259_init(NULL);
	287
	288	/* XXX: use Mac Serial port */
b6cd0ea1	289	serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
aae9366a	290
3cbee15b JM	291	for(i = 0; i < nb_nics; i++) {
	292	if (!nd_table[i].model)
	293	nd_table[i].model = "ne2k_pci";
	294	pci_nic_init(pci_bus, &nd_table[i], -1);
	295	}
0d913fdb JM	296
0d913fdb JM	297	/* First IDE channel is a CMD646 on the PCI bus */
e4bcb14c TS	298
	299	if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
	300	fprintf(stderr, "qemu: too many IDE bus\n");
	301	exit(1);
	302	}
	303	index = drive_get_index(IF_IDE, 0, 0);
	304	if (index == -1)
	305	hd[0] = NULL;
	306	else
	307	hd[0] = drives_table[index].bdrv;
	308	index = drive_get_index(IF_IDE, 0, 1);
	309	if (index == -1)
	310	hd[1] = NULL;
	311	else
	312	hd[1] = drives_table[index].bdrv;
	313	hd[3] = hd[2] = NULL;
	314	pci_cmd646_ide_init(pci_bus, hd, 0);
	315
0d913fdb	316	/* Second IDE channel is a MAC IDE on the MacIO bus */
e4bcb14c TS	317	index = drive_get_index(IF_IDE, 1, 0);
	318	if (index == -1)
	319	hd[0] = NULL;
	320	else
	321	hd[0] = drives_table[index].bdrv;
	322	index = drive_get_index(IF_IDE, 1, 1);
	323	if (index == -1)
	324	hd[1] = NULL;
	325	else
	326	hd[1] = drives_table[index].bdrv;
0d913fdb	327	ide_mem_index[0] = -1;
e4bcb14c	328	ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
3cbee15b JM	329
	330	/* cuda also initialize ADB */
	331	cuda_init(&cuda_mem_index, pic[0x12]);
	332
	333	adb_kbd_init(&adb_bus);
	334	adb_mouse_init(&adb_bus);
aae9366a	335
74e91155	336	nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
3cbee15b JM	337	pmac_format_nvram_partition(nvr, 0x2000);
	338
	339	dbdma_init(&dbdma_mem_index);
28c5af54	340
3cbee15b	341	macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
0d913fdb	342	cuda_mem_index, nvr, 2, ide_mem_index);
3cbee15b JM	343
	344	if (usb_enabled) {
	345	usb_ohci_init_pci(pci_bus, 3, -1);
	346	}
	347
	348	if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
	349	graphic_depth = 15;
	350
	351	m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
	352	nvram.opaque = m48t59;
	353	nvram.read_fn = &m48t59_read;
	354	nvram.write_fn = &m48t59_write;
6ac0e82d AZ	355	PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
6ac0e82d AZ	356	ppc_boot_device, kernel_base, kernel_size,
3cbee15b JM	357	kernel_cmdline,
	358	initrd_base, initrd_size,
	359	/* XXX: need an option to load a NVRAM image */
	360	0,
	361	graphic_width, graphic_height, graphic_depth);
	362	/* No PCI init: the BIOS will do it */
	363
	364	/* Special port to get debug messages from Open-Firmware */
	365	register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
	366	}
	367
	368	QEMUMachine heathrow_machine = {
4b32e168 AL	369	.name = "g3bw",
	370	.desc = "Heathrow based PowerMAC",
	371	.init = ppc_heathrow_init,
	372	.ram_require = BIOS_SIZE + VGA_RAM_SIZE,
3d878caa	373	.max_cpus = MAX_CPUS,
3cbee15b	374	};