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Commit | Line | Data |
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1db09b84 | 1 | /* |
5cbdb3a3 | 2 | * QEMU PowerPC MPC8544DS board emulation |
1db09b84 AJ |
3 | * |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
1db09b84 AJ |
17 | #include "config.h" |
18 | #include "qemu-common.h" | |
19 | #include "net.h" | |
20 | #include "hw.h" | |
21 | #include "pc.h" | |
22 | #include "pci.h" | |
1db09b84 AJ |
23 | #include "boards.h" |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "kvm_ppc.h" | |
27 | #include "device_tree.h" | |
28 | #include "openpic.h" | |
3b989d49 | 29 | #include "ppc.h" |
ca20cf32 BS |
30 | #include "loader.h" |
31 | #include "elf.h" | |
be13cc7a | 32 | #include "sysbus.h" |
39186d8a | 33 | #include "exec-memory.h" |
cba2026a | 34 | #include "host-utils.h" |
1db09b84 AJ |
35 | |
36 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" | |
37 | #define UIMAGE_LOAD_BASE 0 | |
75bb6589 LY |
38 | #define DTC_LOAD_PAD 0x500000 |
39 | #define DTC_PAD_MASK 0xFFFFF | |
40 | #define INITRD_LOAD_PAD 0x2000000 | |
41 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 AJ |
42 | |
43 | #define RAM_SIZES_ALIGN (64UL << 20) | |
44 | ||
45 | #define MPC8544_CCSRBAR_BASE 0xE0000000 | |
5da96624 AG |
46 | #define MPC8544_CCSRBAR_REGSIZE 0x00001000 |
47 | #define MPC8544_CCSRBAR_SIZE 0x00100000 | |
1db09b84 AJ |
48 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) |
49 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) | |
50 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) | |
51 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) | |
52 | #define MPC8544_PCI_REGS_SIZE 0x1000 | |
53 | #define MPC8544_PCI_IO 0xE1000000 | |
54 | #define MPC8544_PCI_IOLEN 0x10000 | |
b0fb8423 | 55 | #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000) |
5c145dac | 56 | #define MPC8544_SPIN_BASE 0xEF000000 |
1db09b84 | 57 | |
3b989d49 AG |
58 | struct boot_info |
59 | { | |
60 | uint32_t dt_base; | |
cba2026a | 61 | uint32_t dt_size; |
3b989d49 AG |
62 | uint32_t entry; |
63 | }; | |
64 | ||
e2684c0b | 65 | static int mpc8544_load_device_tree(CPUPPCState *env, |
5de6b46d AG |
66 | target_phys_addr_t addr, |
67 | uint32_t ramsize, | |
68 | target_phys_addr_t initrd_base, | |
69 | target_phys_addr_t initrd_size, | |
70 | const char *kernel_cmdline) | |
1db09b84 | 71 | { |
dbf916d8 | 72 | int ret = -1; |
3b989d49 | 73 | uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)}; |
5cea8590 | 74 | char *filename; |
7ec632b4 | 75 | int fdt_size; |
dbf916d8 | 76 | void *fdt; |
5de6b46d | 77 | uint8_t hypercall[16]; |
911d6e7a AG |
78 | uint32_t clock_freq = 400000000; |
79 | uint32_t tb_freq = 400000000; | |
621d05e3 | 80 | int i; |
51b852b7 AG |
81 | char compatible[] = "MPC8544DS\0MPC85xxDS"; |
82 | char model[] = "MPC8544DS"; | |
5da96624 | 83 | char soc[128]; |
0cfc6e8d AG |
84 | char ser0[128]; |
85 | char ser1[128]; | |
1db09b84 | 86 | |
5cea8590 PB |
87 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
88 | if (!filename) { | |
1db09b84 | 89 | goto out; |
5cea8590 PB |
90 | } |
91 | fdt = load_device_tree(filename, &fdt_size); | |
7267c094 | 92 | g_free(filename); |
5cea8590 PB |
93 | if (fdt == NULL) { |
94 | goto out; | |
95 | } | |
1db09b84 AJ |
96 | |
97 | /* Manipulate device tree in memory. */ | |
51b852b7 AG |
98 | qemu_devtree_setprop_string(fdt, "/", "model", model); |
99 | qemu_devtree_setprop(fdt, "/", "compatible", compatible, | |
100 | sizeof(compatible)); | |
101 | qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1); | |
102 | qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1); | |
103 | ||
dd0bcfca AG |
104 | qemu_devtree_add_subnode(fdt, "/memory"); |
105 | qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); | |
106 | qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
107 | sizeof(mem_reg_property)); | |
1db09b84 | 108 | |
f5231aaf | 109 | qemu_devtree_add_subnode(fdt, "/chosen"); |
3b989d49 AG |
110 | if (initrd_size) { |
111 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
112 | initrd_base); | |
113 | if (ret < 0) { | |
114 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
115 | } | |
1db09b84 | 116 | |
3b989d49 AG |
117 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
118 | (initrd_base + initrd_size)); | |
119 | if (ret < 0) { | |
120 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
121 | } | |
122 | } | |
1db09b84 AJ |
123 | |
124 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
125 | kernel_cmdline); | |
126 | if (ret < 0) | |
127 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
128 | ||
129 | if (kvm_enabled()) { | |
911d6e7a AG |
130 | /* Read out host's frequencies */ |
131 | clock_freq = kvmppc_get_clockfreq(); | |
132 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
133 | |
134 | /* indicate KVM hypercall interface */ | |
d50f71a5 | 135 | qemu_devtree_add_subnode(fdt, "/hypervisor"); |
5de6b46d AG |
136 | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", |
137 | "linux,kvm"); | |
138 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); | |
139 | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", | |
140 | hypercall, sizeof(hypercall)); | |
1db09b84 | 141 | } |
3b989d49 | 142 | |
625e665b AG |
143 | /* Create CPU nodes */ |
144 | qemu_devtree_add_subnode(fdt, "/cpus"); | |
145 | qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
146 | qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
147 | ||
1e3debf0 AG |
148 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
149 | the first node as boot node and be happy */ | |
150 | for (i = smp_cpus - 1; i >= 0; i--) { | |
621d05e3 | 151 | char cpu_name[128]; |
1e3debf0 | 152 | uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20)); |
10f25a46 | 153 | |
1e3debf0 AG |
154 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
155 | if (env->cpu_index == i) { | |
156 | break; | |
157 | } | |
158 | } | |
159 | ||
160 | if (!env) { | |
161 | continue; | |
162 | } | |
163 | ||
164 | snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); | |
165 | qemu_devtree_add_subnode(fdt, cpu_name); | |
621d05e3 AG |
166 | qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); |
167 | qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
1e3debf0 AG |
168 | qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
169 | qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index); | |
170 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", | |
171 | env->dcache_line_size); | |
172 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
173 | env->icache_line_size); | |
174 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
175 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
176 | qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
177 | if (env->cpu_index) { | |
178 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); | |
179 | qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); | |
180 | qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr", | |
181 | &cpu_release_addr, sizeof(cpu_release_addr)); | |
182 | } else { | |
183 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); | |
184 | } | |
1db09b84 AJ |
185 | } |
186 | ||
0cfc6e8d | 187 | qemu_devtree_add_subnode(fdt, "/aliases"); |
5da96624 AG |
188 | /* XXX These should go into their respective devices' code */ |
189 | snprintf(soc, sizeof(soc), "/soc8544@%x", MPC8544_CCSRBAR_BASE); | |
190 | qemu_devtree_add_subnode(fdt, soc); | |
191 | qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); | |
192 | qemu_devtree_setprop_string(fdt, soc, "compatible", "simple-bus"); | |
193 | qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); | |
194 | qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); | |
195 | qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE, | |
196 | MPC8544_CCSRBAR_SIZE); | |
197 | qemu_devtree_setprop_cells(fdt, soc, "reg", MPC8544_CCSRBAR_BASE, | |
198 | MPC8544_CCSRBAR_REGSIZE); | |
199 | /* XXX should contain a reasonable value */ | |
200 | qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); | |
201 | ||
0cfc6e8d AG |
202 | /* |
203 | * We have to generate ser1 first, because Linux takes the first | |
204 | * device it finds in the dt as serial output device. And we generate | |
205 | * devices in reverse order to the dt. | |
206 | */ | |
207 | snprintf(ser1, sizeof(ser1), "%s/serial@%x", soc, | |
208 | MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE); | |
209 | qemu_devtree_add_subnode(fdt, ser1); | |
210 | qemu_devtree_setprop_string(fdt, ser1, "device_type", "serial"); | |
211 | qemu_devtree_setprop_string(fdt, ser1, "compatible", "ns16550"); | |
212 | qemu_devtree_setprop_cells(fdt, ser1, "reg", MPC8544_SERIAL1_REGS_BASE - | |
213 | MPC8544_CCSRBAR_BASE, 0x100); | |
214 | qemu_devtree_setprop_cell(fdt, ser1, "cell-index", 1); | |
215 | qemu_devtree_setprop_cell(fdt, ser1, "clock-frequency", 0); | |
216 | qemu_devtree_setprop_cells(fdt, ser1, "interrupts", 42, 2); | |
217 | qemu_devtree_setprop_phandle(fdt, ser1, "interrupt-parent", mpic); | |
218 | qemu_devtree_setprop_string(fdt, "/aliases", "serial1", ser1); | |
219 | ||
220 | snprintf(ser0, sizeof(ser0), "%s/serial@%x", soc, | |
221 | MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE); | |
222 | qemu_devtree_add_subnode(fdt, ser0); | |
223 | qemu_devtree_setprop_string(fdt, ser0, "device_type", "serial"); | |
224 | qemu_devtree_setprop_string(fdt, ser0, "compatible", "ns16550"); | |
225 | qemu_devtree_setprop_cells(fdt, ser0, "reg", MPC8544_SERIAL0_REGS_BASE - | |
226 | MPC8544_CCSRBAR_BASE, 0x100); | |
227 | qemu_devtree_setprop_cell(fdt, ser0, "cell-index", 0); | |
228 | qemu_devtree_setprop_cell(fdt, ser0, "clock-frequency", 0); | |
229 | qemu_devtree_setprop_cells(fdt, ser0, "interrupts", 42, 2); | |
230 | qemu_devtree_setprop_phandle(fdt, ser0, "interrupt-parent", mpic); | |
231 | qemu_devtree_setprop_string(fdt, "/aliases", "serial0", ser0); | |
232 | qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser0); | |
233 | ||
04088adb | 234 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
cba2026a AG |
235 | if (ret < 0) { |
236 | goto out; | |
237 | } | |
7267c094 | 238 | g_free(fdt); |
cba2026a | 239 | ret = fdt_size; |
7ec632b4 | 240 | |
1db09b84 | 241 | out: |
1db09b84 | 242 | |
04088adb | 243 | return ret; |
1db09b84 AJ |
244 | } |
245 | ||
cba2026a | 246 | /* Create -kernel TLB entries for BookE. */ |
d1e256fe AG |
247 | static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) |
248 | { | |
cba2026a | 249 | return 63 - clz64(size >> 10); |
d1e256fe AG |
250 | } |
251 | ||
cba2026a | 252 | static void mmubooke_create_initial_mapping(CPUPPCState *env) |
3b989d49 | 253 | { |
cba2026a | 254 | struct boot_info *bi = env->load_info; |
d1e256fe | 255 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
cba2026a AG |
256 | target_phys_addr_t size, dt_end; |
257 | int ps; | |
258 | ||
259 | /* Our initial TLB entry needs to cover everything from 0 to | |
260 | the device tree top */ | |
261 | dt_end = bi->dt_base + bi->dt_size; | |
262 | ps = booke206_page_size_to_tlb(dt_end) + 1; | |
263 | size = (ps << MAS1_TSIZE_SHIFT); | |
d1e256fe | 264 | tlb->mas1 = MAS1_VALID | size; |
cba2026a AG |
265 | tlb->mas2 = 0; |
266 | tlb->mas7_3 = 0; | |
d1e256fe | 267 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
93dd5e85 SW |
268 | |
269 | env->tlb_dirty = true; | |
3b989d49 AG |
270 | } |
271 | ||
5c145dac AG |
272 | static void mpc8544ds_cpu_reset_sec(void *opaque) |
273 | { | |
38f92da6 AF |
274 | PowerPCCPU *cpu = opaque; |
275 | CPUPPCState *env = &cpu->env; | |
5c145dac | 276 | |
38f92da6 | 277 | cpu_reset(CPU(cpu)); |
5c145dac AG |
278 | |
279 | /* Secondary CPU starts in halted state for now. Needs to change when | |
280 | implementing non-kernel boot. */ | |
281 | env->halted = 1; | |
282 | env->exception_index = EXCP_HLT; | |
3b989d49 AG |
283 | } |
284 | ||
285 | static void mpc8544ds_cpu_reset(void *opaque) | |
286 | { | |
38f92da6 AF |
287 | PowerPCCPU *cpu = opaque; |
288 | CPUPPCState *env = &cpu->env; | |
3b989d49 AG |
289 | struct boot_info *bi = env->load_info; |
290 | ||
38f92da6 | 291 | cpu_reset(CPU(cpu)); |
3b989d49 AG |
292 | |
293 | /* Set initial guest state. */ | |
5c145dac | 294 | env->halted = 0; |
3b989d49 AG |
295 | env->gpr[1] = (16<<20) - 8; |
296 | env->gpr[3] = bi->dt_base; | |
297 | env->nip = bi->entry; | |
cba2026a | 298 | mmubooke_create_initial_mapping(env); |
3b989d49 AG |
299 | } |
300 | ||
c227f099 | 301 | static void mpc8544ds_init(ram_addr_t ram_size, |
1db09b84 AJ |
302 | const char *boot_device, |
303 | const char *kernel_filename, | |
304 | const char *kernel_cmdline, | |
305 | const char *initrd_filename, | |
306 | const char *cpu_model) | |
307 | { | |
39186d8a | 308 | MemoryRegion *address_space_mem = get_system_memory(); |
2646c133 | 309 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
1db09b84 | 310 | PCIBus *pci_bus; |
e2684c0b | 311 | CPUPPCState *env = NULL; |
1db09b84 AJ |
312 | uint64_t elf_entry; |
313 | uint64_t elf_lowaddr; | |
c227f099 AL |
314 | target_phys_addr_t entry=0; |
315 | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 | 316 | target_long kernel_size=0; |
75bb6589 LY |
317 | target_ulong dt_base = 0; |
318 | target_ulong initrd_base = 0; | |
1db09b84 | 319 | target_long initrd_size=0; |
1db09b84 AJ |
320 | int i=0; |
321 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; | |
a915249f | 322 | qemu_irq **irqs, *mpic; |
be13cc7a | 323 | DeviceState *dev; |
e2684c0b | 324 | CPUPPCState *firstenv = NULL; |
1db09b84 | 325 | |
e61c36d5 | 326 | /* Setup CPUs */ |
ef250db6 AG |
327 | if (cpu_model == NULL) { |
328 | cpu_model = "e500v2_v30"; | |
329 | } | |
330 | ||
a915249f AG |
331 | irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); |
332 | irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
e61c36d5 | 333 | for (i = 0; i < smp_cpus; i++) { |
397b457d | 334 | PowerPCCPU *cpu; |
e61c36d5 | 335 | qemu_irq *input; |
397b457d AF |
336 | |
337 | cpu = cpu_ppc_init(cpu_model); | |
338 | if (cpu == NULL) { | |
e61c36d5 AG |
339 | fprintf(stderr, "Unable to initialize CPU!\n"); |
340 | exit(1); | |
341 | } | |
397b457d | 342 | env = &cpu->env; |
1db09b84 | 343 | |
e61c36d5 AG |
344 | if (!firstenv) { |
345 | firstenv = env; | |
346 | } | |
1db09b84 | 347 | |
a915249f AG |
348 | irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); |
349 | input = (qemu_irq *)env->irq_inputs; | |
350 | irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; | |
351 | irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
e61c36d5 | 352 | env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; |
3b989d49 | 353 | |
ddd1055b | 354 | ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); |
e61c36d5 AG |
355 | |
356 | /* Register reset handler */ | |
5c145dac AG |
357 | if (!i) { |
358 | /* Primary CPU */ | |
359 | struct boot_info *boot_info; | |
360 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
38f92da6 | 361 | qemu_register_reset(mpc8544ds_cpu_reset, cpu); |
5c145dac AG |
362 | env->load_info = boot_info; |
363 | } else { | |
364 | /* Secondary CPUs */ | |
38f92da6 | 365 | qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu); |
5c145dac | 366 | } |
e61c36d5 | 367 | } |
3b989d49 | 368 | |
e61c36d5 | 369 | env = firstenv; |
3b989d49 | 370 | |
1db09b84 AJ |
371 | /* Fixup Memory size on a alignment boundary */ |
372 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
373 | ||
374 | /* Register Memory */ | |
c5705a77 AK |
375 | memory_region_init_ram(ram, "mpc8544ds.ram", ram_size); |
376 | vmstate_register_ram_global(ram); | |
2646c133 | 377 | memory_region_add_subregion(address_space_mem, 0, ram); |
1db09b84 AJ |
378 | |
379 | /* MPIC */ | |
df2921d3 AK |
380 | mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, |
381 | smp_cpus, irqs, NULL); | |
a915249f AG |
382 | |
383 | if (!mpic) { | |
384 | cpu_abort(env, "MPIC failed to initialize\n"); | |
385 | } | |
1db09b84 AJ |
386 | |
387 | /* Serial */ | |
2d48377a | 388 | if (serial_hds[0]) { |
39186d8a | 389 | serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE, |
49a2942d | 390 | 0, mpic[12+26], 399193, |
2ff0c7c3 | 391 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 392 | } |
1db09b84 | 393 | |
2d48377a | 394 | if (serial_hds[1]) { |
39186d8a | 395 | serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE, |
49a2942d | 396 | 0, mpic[12+26], 399193, |
2ff0c7c3 | 397 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 398 | } |
1db09b84 | 399 | |
b0fb8423 AG |
400 | /* General Utility device */ |
401 | sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); | |
402 | ||
1db09b84 | 403 | /* PCI */ |
be13cc7a AG |
404 | dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE, |
405 | mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], | |
406 | mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], | |
407 | NULL); | |
d461e3b9 | 408 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
409 | if (!pci_bus) |
410 | printf("couldn't create PCI controller!\n"); | |
411 | ||
968d683c | 412 | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
1db09b84 AJ |
413 | |
414 | if (pci_bus) { | |
1db09b84 AJ |
415 | /* Register network interfaces. */ |
416 | for (i = 0; i < nb_nics; i++) { | |
07caea31 | 417 | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
1db09b84 AJ |
418 | } |
419 | } | |
420 | ||
5c145dac AG |
421 | /* Register spinning region */ |
422 | sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); | |
423 | ||
1db09b84 AJ |
424 | /* Load kernel. */ |
425 | if (kernel_filename) { | |
426 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL); | |
427 | if (kernel_size < 0) { | |
409dbce5 AJ |
428 | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
429 | &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); | |
1db09b84 AJ |
430 | entry = elf_entry; |
431 | loadaddr = elf_lowaddr; | |
432 | } | |
433 | /* XXX try again as binary */ | |
434 | if (kernel_size < 0) { | |
435 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
436 | kernel_filename); | |
437 | exit(1); | |
438 | } | |
439 | } | |
440 | ||
441 | /* Load initrd. */ | |
442 | if (initrd_filename) { | |
75bb6589 | 443 | initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
d7585251 PB |
444 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
445 | ram_size - initrd_base); | |
1db09b84 AJ |
446 | |
447 | if (initrd_size < 0) { | |
448 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
449 | initrd_filename); | |
450 | exit(1); | |
451 | } | |
452 | } | |
453 | ||
454 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
455 | if (kernel_filename) { | |
5c145dac | 456 | struct boot_info *boot_info; |
cba2026a | 457 | int dt_size; |
5c145dac | 458 | |
cba2026a AG |
459 | dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
460 | dt_size = mpc8544_load_device_tree(env, dt_base, ram_size, initrd_base, | |
461 | initrd_size, kernel_cmdline); | |
462 | if (dt_size < 0) { | |
1db09b84 AJ |
463 | fprintf(stderr, "couldn't load device tree\n"); |
464 | exit(1); | |
465 | } | |
466 | ||
e61c36d5 | 467 | boot_info = env->load_info; |
3b989d49 AG |
468 | boot_info->entry = entry; |
469 | boot_info->dt_base = dt_base; | |
cba2026a | 470 | boot_info->dt_size = dt_size; |
1db09b84 AJ |
471 | } |
472 | ||
3b989d49 | 473 | if (kvm_enabled()) { |
1db09b84 | 474 | kvmppc_init(); |
3b989d49 | 475 | } |
1db09b84 AJ |
476 | } |
477 | ||
f80f9ec9 | 478 | static QEMUMachine mpc8544ds_machine = { |
1db09b84 AJ |
479 | .name = "mpc8544ds", |
480 | .desc = "mpc8544ds", | |
481 | .init = mpc8544ds_init, | |
a2a67420 | 482 | .max_cpus = 15, |
1db09b84 | 483 | }; |
f80f9ec9 AL |
484 | |
485 | static void mpc8544ds_machine_init(void) | |
486 | { | |
487 | qemu_register_machine(&mpc8544ds_machine); | |
488 | } | |
489 | ||
490 | machine_init(mpc8544ds_machine_init); |