]>
Commit | Line | Data |
---|---|---|
1db09b84 AJ |
1 | /* |
2 | * Qemu PowerPC MPC8544DS board emualtion | |
3 | * | |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
1db09b84 AJ |
17 | #include "config.h" |
18 | #include "qemu-common.h" | |
19 | #include "net.h" | |
20 | #include "hw.h" | |
21 | #include "pc.h" | |
22 | #include "pci.h" | |
1db09b84 AJ |
23 | #include "boards.h" |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "kvm_ppc.h" | |
27 | #include "device_tree.h" | |
28 | #include "openpic.h" | |
3b989d49 | 29 | #include "ppc.h" |
ca20cf32 BS |
30 | #include "loader.h" |
31 | #include "elf.h" | |
be13cc7a | 32 | #include "sysbus.h" |
1db09b84 AJ |
33 | |
34 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" | |
35 | #define UIMAGE_LOAD_BASE 0 | |
75bb6589 LY |
36 | #define DTC_LOAD_PAD 0x500000 |
37 | #define DTC_PAD_MASK 0xFFFFF | |
38 | #define INITRD_LOAD_PAD 0x2000000 | |
39 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 AJ |
40 | |
41 | #define RAM_SIZES_ALIGN (64UL << 20) | |
42 | ||
43 | #define MPC8544_CCSRBAR_BASE 0xE0000000 | |
44 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) | |
45 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) | |
46 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) | |
47 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) | |
48 | #define MPC8544_PCI_REGS_SIZE 0x1000 | |
49 | #define MPC8544_PCI_IO 0xE1000000 | |
50 | #define MPC8544_PCI_IOLEN 0x10000 | |
b0fb8423 | 51 | #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000) |
5c145dac | 52 | #define MPC8544_SPIN_BASE 0xEF000000 |
1db09b84 | 53 | |
3b989d49 AG |
54 | struct boot_info |
55 | { | |
56 | uint32_t dt_base; | |
57 | uint32_t entry; | |
58 | }; | |
59 | ||
5de6b46d AG |
60 | static int mpc8544_load_device_tree(CPUState *env, |
61 | target_phys_addr_t addr, | |
62 | uint32_t ramsize, | |
63 | target_phys_addr_t initrd_base, | |
64 | target_phys_addr_t initrd_size, | |
65 | const char *kernel_cmdline) | |
1db09b84 | 66 | { |
dbf916d8 | 67 | int ret = -1; |
3f0855b1 | 68 | #ifdef CONFIG_FDT |
3b989d49 | 69 | uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)}; |
5cea8590 | 70 | char *filename; |
7ec632b4 | 71 | int fdt_size; |
dbf916d8 | 72 | void *fdt; |
5de6b46d | 73 | uint8_t hypercall[16]; |
911d6e7a AG |
74 | uint32_t clock_freq = 400000000; |
75 | uint32_t tb_freq = 400000000; | |
621d05e3 | 76 | int i; |
1db09b84 | 77 | |
5cea8590 PB |
78 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
79 | if (!filename) { | |
1db09b84 | 80 | goto out; |
5cea8590 PB |
81 | } |
82 | fdt = load_device_tree(filename, &fdt_size); | |
7267c094 | 83 | g_free(filename); |
5cea8590 PB |
84 | if (fdt == NULL) { |
85 | goto out; | |
86 | } | |
1db09b84 AJ |
87 | |
88 | /* Manipulate device tree in memory. */ | |
89 | ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
90 | sizeof(mem_reg_property)); | |
91 | if (ret < 0) | |
92 | fprintf(stderr, "couldn't set /memory/reg\n"); | |
93 | ||
3b989d49 AG |
94 | if (initrd_size) { |
95 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
96 | initrd_base); | |
97 | if (ret < 0) { | |
98 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
99 | } | |
1db09b84 | 100 | |
3b989d49 AG |
101 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
102 | (initrd_base + initrd_size)); | |
103 | if (ret < 0) { | |
104 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
105 | } | |
106 | } | |
1db09b84 AJ |
107 | |
108 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
109 | kernel_cmdline); | |
110 | if (ret < 0) | |
111 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
112 | ||
113 | if (kvm_enabled()) { | |
911d6e7a AG |
114 | /* Read out host's frequencies */ |
115 | clock_freq = kvmppc_get_clockfreq(); | |
116 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
117 | |
118 | /* indicate KVM hypercall interface */ | |
119 | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", | |
120 | "linux,kvm"); | |
121 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); | |
122 | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", | |
123 | hypercall, sizeof(hypercall)); | |
1db09b84 AJ |
124 | } |
125 | ||
1e3debf0 AG |
126 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
127 | the first node as boot node and be happy */ | |
128 | for (i = smp_cpus - 1; i >= 0; i--) { | |
621d05e3 | 129 | char cpu_name[128]; |
1e3debf0 | 130 | uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20)); |
10f25a46 | 131 | |
1e3debf0 AG |
132 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
133 | if (env->cpu_index == i) { | |
134 | break; | |
135 | } | |
136 | } | |
137 | ||
138 | if (!env) { | |
139 | continue; | |
140 | } | |
141 | ||
142 | snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); | |
143 | qemu_devtree_add_subnode(fdt, cpu_name); | |
621d05e3 AG |
144 | qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); |
145 | qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
1e3debf0 AG |
146 | qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
147 | qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index); | |
148 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", | |
149 | env->dcache_line_size); | |
150 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
151 | env->icache_line_size); | |
152 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
153 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
154 | qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
155 | if (env->cpu_index) { | |
156 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); | |
157 | qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); | |
158 | qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr", | |
159 | &cpu_release_addr, sizeof(cpu_release_addr)); | |
160 | } else { | |
161 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); | |
162 | } | |
66bc7e00 AG |
163 | } |
164 | ||
04088adb | 165 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
7267c094 | 166 | g_free(fdt); |
7ec632b4 | 167 | |
1db09b84 AJ |
168 | out: |
169 | #endif | |
170 | ||
04088adb | 171 | return ret; |
1db09b84 AJ |
172 | } |
173 | ||
3b989d49 | 174 | /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */ |
d1e256fe AG |
175 | static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) |
176 | { | |
177 | return (ffs(size >> 10) - 1) >> 1; | |
178 | } | |
179 | ||
3b989d49 AG |
180 | static void mmubooke_create_initial_mapping(CPUState *env, |
181 | target_ulong va, | |
182 | target_phys_addr_t pa) | |
183 | { | |
d1e256fe AG |
184 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
185 | target_phys_addr_t size; | |
186 | ||
187 | size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT); | |
188 | tlb->mas1 = MAS1_VALID | size; | |
189 | tlb->mas2 = va & TARGET_PAGE_MASK; | |
190 | tlb->mas7_3 = pa & TARGET_PAGE_MASK; | |
191 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; | |
3b989d49 AG |
192 | } |
193 | ||
5c145dac AG |
194 | static void mpc8544ds_cpu_reset_sec(void *opaque) |
195 | { | |
196 | CPUState *env = opaque; | |
197 | ||
198 | cpu_reset(env); | |
199 | ||
200 | /* Secondary CPU starts in halted state for now. Needs to change when | |
201 | implementing non-kernel boot. */ | |
202 | env->halted = 1; | |
203 | env->exception_index = EXCP_HLT; | |
204 | } | |
205 | ||
3b989d49 AG |
206 | static void mpc8544ds_cpu_reset(void *opaque) |
207 | { | |
208 | CPUState *env = opaque; | |
209 | struct boot_info *bi = env->load_info; | |
210 | ||
211 | cpu_reset(env); | |
212 | ||
213 | /* Set initial guest state. */ | |
5c145dac | 214 | env->halted = 0; |
3b989d49 AG |
215 | env->gpr[1] = (16<<20) - 8; |
216 | env->gpr[3] = bi->dt_base; | |
217 | env->nip = bi->entry; | |
218 | mmubooke_create_initial_mapping(env, 0, 0); | |
219 | } | |
220 | ||
c227f099 | 221 | static void mpc8544ds_init(ram_addr_t ram_size, |
1db09b84 AJ |
222 | const char *boot_device, |
223 | const char *kernel_filename, | |
224 | const char *kernel_cmdline, | |
225 | const char *initrd_filename, | |
226 | const char *cpu_model) | |
227 | { | |
228 | PCIBus *pci_bus; | |
e61c36d5 | 229 | CPUState *env = NULL; |
1db09b84 AJ |
230 | uint64_t elf_entry; |
231 | uint64_t elf_lowaddr; | |
c227f099 AL |
232 | target_phys_addr_t entry=0; |
233 | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 | 234 | target_long kernel_size=0; |
75bb6589 LY |
235 | target_ulong dt_base = 0; |
236 | target_ulong initrd_base = 0; | |
1db09b84 | 237 | target_long initrd_size=0; |
1db09b84 AJ |
238 | int i=0; |
239 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; | |
a915249f | 240 | qemu_irq **irqs, *mpic; |
be13cc7a | 241 | DeviceState *dev; |
e61c36d5 | 242 | CPUState *firstenv = NULL; |
1db09b84 | 243 | |
e61c36d5 | 244 | /* Setup CPUs */ |
ef250db6 AG |
245 | if (cpu_model == NULL) { |
246 | cpu_model = "e500v2_v30"; | |
247 | } | |
248 | ||
a915249f AG |
249 | irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); |
250 | irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
e61c36d5 AG |
251 | for (i = 0; i < smp_cpus; i++) { |
252 | qemu_irq *input; | |
253 | env = cpu_ppc_init(cpu_model); | |
254 | if (!env) { | |
255 | fprintf(stderr, "Unable to initialize CPU!\n"); | |
256 | exit(1); | |
257 | } | |
258 | ||
259 | if (!firstenv) { | |
260 | firstenv = env; | |
261 | } | |
1db09b84 | 262 | |
a915249f AG |
263 | irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); |
264 | input = (qemu_irq *)env->irq_inputs; | |
265 | irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; | |
266 | irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
e61c36d5 | 267 | env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; |
3b989d49 | 268 | |
e61c36d5 AG |
269 | /* XXX register timer? */ |
270 | ppc_emb_timers_init(env, 400000000, PPC_INTERRUPT_DECR); | |
271 | ppc_dcr_init(env, NULL, NULL); | |
272 | /* XXX Enable DEC interrupts - probably wrong in the backend */ | |
273 | env->spr[SPR_40x_TCR] = 1 << 26; | |
274 | ||
275 | /* Register reset handler */ | |
5c145dac AG |
276 | if (!i) { |
277 | /* Primary CPU */ | |
278 | struct boot_info *boot_info; | |
279 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
280 | qemu_register_reset(mpc8544ds_cpu_reset, env); | |
281 | env->load_info = boot_info; | |
282 | } else { | |
283 | /* Secondary CPUs */ | |
284 | qemu_register_reset(mpc8544ds_cpu_reset_sec, env); | |
285 | } | |
e61c36d5 AG |
286 | } |
287 | ||
288 | env = firstenv; | |
3b989d49 | 289 | |
1db09b84 AJ |
290 | /* Fixup Memory size on a alignment boundary */ |
291 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
292 | ||
293 | /* Register Memory */ | |
1724f049 AW |
294 | cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL, |
295 | "mpc8544ds.ram", ram_size)); | |
1db09b84 AJ |
296 | |
297 | /* MPIC */ | |
a915249f AG |
298 | mpic = mpic_init(MPC8544_MPIC_REGS_BASE, smp_cpus, irqs, NULL); |
299 | ||
300 | if (!mpic) { | |
301 | cpu_abort(env, "MPIC failed to initialize\n"); | |
302 | } | |
1db09b84 AJ |
303 | |
304 | /* Serial */ | |
2d48377a | 305 | if (serial_hds[0]) { |
49a2942d BS |
306 | serial_mm_init(MPC8544_SERIAL0_REGS_BASE, |
307 | 0, mpic[12+26], 399193, | |
308 | serial_hds[0], 1, 1); | |
2d48377a | 309 | } |
1db09b84 | 310 | |
2d48377a | 311 | if (serial_hds[1]) { |
49a2942d BS |
312 | serial_mm_init(MPC8544_SERIAL1_REGS_BASE, |
313 | 0, mpic[12+26], 399193, | |
314 | serial_hds[0], 1, 1); | |
2d48377a | 315 | } |
1db09b84 | 316 | |
b0fb8423 AG |
317 | /* General Utility device */ |
318 | sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); | |
319 | ||
1db09b84 | 320 | /* PCI */ |
be13cc7a AG |
321 | dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE, |
322 | mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], | |
323 | mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], | |
324 | NULL); | |
d461e3b9 | 325 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
326 | if (!pci_bus) |
327 | printf("couldn't create PCI controller!\n"); | |
328 | ||
968d683c | 329 | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
1db09b84 AJ |
330 | |
331 | if (pci_bus) { | |
1db09b84 AJ |
332 | /* Register network interfaces. */ |
333 | for (i = 0; i < nb_nics; i++) { | |
07caea31 | 334 | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
1db09b84 AJ |
335 | } |
336 | } | |
337 | ||
5c145dac AG |
338 | /* Register spinning region */ |
339 | sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); | |
340 | ||
1db09b84 AJ |
341 | /* Load kernel. */ |
342 | if (kernel_filename) { | |
343 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL); | |
344 | if (kernel_size < 0) { | |
409dbce5 AJ |
345 | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
346 | &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); | |
1db09b84 AJ |
347 | entry = elf_entry; |
348 | loadaddr = elf_lowaddr; | |
349 | } | |
350 | /* XXX try again as binary */ | |
351 | if (kernel_size < 0) { | |
352 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
353 | kernel_filename); | |
354 | exit(1); | |
355 | } | |
356 | } | |
357 | ||
358 | /* Load initrd. */ | |
359 | if (initrd_filename) { | |
75bb6589 | 360 | initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
d7585251 PB |
361 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
362 | ram_size - initrd_base); | |
1db09b84 AJ |
363 | |
364 | if (initrd_size < 0) { | |
365 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
366 | initrd_filename); | |
367 | exit(1); | |
368 | } | |
369 | } | |
370 | ||
371 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
372 | if (kernel_filename) { | |
5c145dac AG |
373 | struct boot_info *boot_info; |
374 | ||
3b989d49 AG |
375 | #ifndef CONFIG_FDT |
376 | cpu_abort(env, "Compiled without FDT support - can't load kernel\n"); | |
377 | #endif | |
75bb6589 | 378 | dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
5de6b46d | 379 | if (mpc8544_load_device_tree(env, dt_base, ram_size, |
04088adb | 380 | initrd_base, initrd_size, kernel_cmdline) < 0) { |
1db09b84 AJ |
381 | fprintf(stderr, "couldn't load device tree\n"); |
382 | exit(1); | |
383 | } | |
384 | ||
e61c36d5 | 385 | boot_info = env->load_info; |
3b989d49 AG |
386 | boot_info->entry = entry; |
387 | boot_info->dt_base = dt_base; | |
1db09b84 AJ |
388 | } |
389 | ||
3b989d49 | 390 | if (kvm_enabled()) { |
1db09b84 | 391 | kvmppc_init(); |
3b989d49 | 392 | } |
1db09b84 AJ |
393 | } |
394 | ||
f80f9ec9 | 395 | static QEMUMachine mpc8544ds_machine = { |
1db09b84 AJ |
396 | .name = "mpc8544ds", |
397 | .desc = "mpc8544ds", | |
398 | .init = mpc8544ds_init, | |
a2a67420 | 399 | .max_cpus = 15, |
1db09b84 | 400 | }; |
f80f9ec9 AL |
401 | |
402 | static void mpc8544ds_machine_init(void) | |
403 | { | |
404 | qemu_register_machine(&mpc8544ds_machine); | |
405 | } | |
406 | ||
407 | machine_init(mpc8544ds_machine_init); |