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Commit | Line | Data |
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1db09b84 | 1 | /* |
5cbdb3a3 | 2 | * QEMU PowerPC MPC8544DS board emulation |
1db09b84 AJ |
3 | * |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
1db09b84 AJ |
17 | #include "config.h" |
18 | #include "qemu-common.h" | |
19 | #include "net.h" | |
20 | #include "hw.h" | |
21 | #include "pc.h" | |
22 | #include "pci.h" | |
1db09b84 AJ |
23 | #include "boards.h" |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "kvm_ppc.h" | |
27 | #include "device_tree.h" | |
28 | #include "openpic.h" | |
3b989d49 | 29 | #include "ppc.h" |
ca20cf32 BS |
30 | #include "loader.h" |
31 | #include "elf.h" | |
be13cc7a | 32 | #include "sysbus.h" |
39186d8a | 33 | #include "exec-memory.h" |
cba2026a | 34 | #include "host-utils.h" |
1db09b84 AJ |
35 | |
36 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" | |
37 | #define UIMAGE_LOAD_BASE 0 | |
75bb6589 LY |
38 | #define DTC_LOAD_PAD 0x500000 |
39 | #define DTC_PAD_MASK 0xFFFFF | |
40 | #define INITRD_LOAD_PAD 0x2000000 | |
41 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 AJ |
42 | |
43 | #define RAM_SIZES_ALIGN (64UL << 20) | |
44 | ||
45 | #define MPC8544_CCSRBAR_BASE 0xE0000000 | |
46 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) | |
47 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) | |
48 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) | |
49 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) | |
50 | #define MPC8544_PCI_REGS_SIZE 0x1000 | |
51 | #define MPC8544_PCI_IO 0xE1000000 | |
52 | #define MPC8544_PCI_IOLEN 0x10000 | |
b0fb8423 | 53 | #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000) |
5c145dac | 54 | #define MPC8544_SPIN_BASE 0xEF000000 |
1db09b84 | 55 | |
3b989d49 AG |
56 | struct boot_info |
57 | { | |
58 | uint32_t dt_base; | |
cba2026a | 59 | uint32_t dt_size; |
3b989d49 AG |
60 | uint32_t entry; |
61 | }; | |
62 | ||
e2684c0b | 63 | static int mpc8544_load_device_tree(CPUPPCState *env, |
5de6b46d AG |
64 | target_phys_addr_t addr, |
65 | uint32_t ramsize, | |
66 | target_phys_addr_t initrd_base, | |
67 | target_phys_addr_t initrd_size, | |
68 | const char *kernel_cmdline) | |
1db09b84 | 69 | { |
dbf916d8 | 70 | int ret = -1; |
3b989d49 | 71 | uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)}; |
5cea8590 | 72 | char *filename; |
7ec632b4 | 73 | int fdt_size; |
dbf916d8 | 74 | void *fdt; |
5de6b46d | 75 | uint8_t hypercall[16]; |
911d6e7a AG |
76 | uint32_t clock_freq = 400000000; |
77 | uint32_t tb_freq = 400000000; | |
621d05e3 | 78 | int i; |
51b852b7 AG |
79 | char compatible[] = "MPC8544DS\0MPC85xxDS"; |
80 | char model[] = "MPC8544DS"; | |
1db09b84 | 81 | |
5cea8590 PB |
82 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
83 | if (!filename) { | |
1db09b84 | 84 | goto out; |
5cea8590 PB |
85 | } |
86 | fdt = load_device_tree(filename, &fdt_size); | |
7267c094 | 87 | g_free(filename); |
5cea8590 PB |
88 | if (fdt == NULL) { |
89 | goto out; | |
90 | } | |
1db09b84 AJ |
91 | |
92 | /* Manipulate device tree in memory. */ | |
51b852b7 AG |
93 | qemu_devtree_setprop_string(fdt, "/", "model", model); |
94 | qemu_devtree_setprop(fdt, "/", "compatible", compatible, | |
95 | sizeof(compatible)); | |
96 | qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1); | |
97 | qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1); | |
98 | ||
dd0bcfca AG |
99 | qemu_devtree_add_subnode(fdt, "/memory"); |
100 | qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); | |
101 | qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
102 | sizeof(mem_reg_property)); | |
1db09b84 | 103 | |
f5231aaf | 104 | qemu_devtree_add_subnode(fdt, "/chosen"); |
3b989d49 AG |
105 | if (initrd_size) { |
106 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
107 | initrd_base); | |
108 | if (ret < 0) { | |
109 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
110 | } | |
1db09b84 | 111 | |
3b989d49 AG |
112 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
113 | (initrd_base + initrd_size)); | |
114 | if (ret < 0) { | |
115 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
116 | } | |
117 | } | |
1db09b84 AJ |
118 | |
119 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
120 | kernel_cmdline); | |
121 | if (ret < 0) | |
122 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
123 | ||
124 | if (kvm_enabled()) { | |
911d6e7a AG |
125 | /* Read out host's frequencies */ |
126 | clock_freq = kvmppc_get_clockfreq(); | |
127 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
128 | |
129 | /* indicate KVM hypercall interface */ | |
d50f71a5 | 130 | qemu_devtree_add_subnode(fdt, "/hypervisor"); |
5de6b46d AG |
131 | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", |
132 | "linux,kvm"); | |
133 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); | |
134 | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", | |
135 | hypercall, sizeof(hypercall)); | |
1db09b84 | 136 | } |
3b989d49 | 137 | |
625e665b AG |
138 | /* Create CPU nodes */ |
139 | qemu_devtree_add_subnode(fdt, "/cpus"); | |
140 | qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
141 | qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
142 | ||
1e3debf0 AG |
143 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
144 | the first node as boot node and be happy */ | |
145 | for (i = smp_cpus - 1; i >= 0; i--) { | |
621d05e3 | 146 | char cpu_name[128]; |
1e3debf0 | 147 | uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20)); |
10f25a46 | 148 | |
1e3debf0 AG |
149 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
150 | if (env->cpu_index == i) { | |
151 | break; | |
152 | } | |
153 | } | |
154 | ||
155 | if (!env) { | |
156 | continue; | |
157 | } | |
158 | ||
159 | snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); | |
160 | qemu_devtree_add_subnode(fdt, cpu_name); | |
621d05e3 AG |
161 | qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); |
162 | qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
1e3debf0 AG |
163 | qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
164 | qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index); | |
165 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", | |
166 | env->dcache_line_size); | |
167 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
168 | env->icache_line_size); | |
169 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
170 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
171 | qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
172 | if (env->cpu_index) { | |
173 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); | |
174 | qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); | |
175 | qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr", | |
176 | &cpu_release_addr, sizeof(cpu_release_addr)); | |
177 | } else { | |
178 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); | |
179 | } | |
1db09b84 AJ |
180 | } |
181 | ||
04088adb | 182 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
cba2026a AG |
183 | if (ret < 0) { |
184 | goto out; | |
185 | } | |
7267c094 | 186 | g_free(fdt); |
cba2026a | 187 | ret = fdt_size; |
7ec632b4 | 188 | |
1db09b84 | 189 | out: |
1db09b84 | 190 | |
04088adb | 191 | return ret; |
1db09b84 AJ |
192 | } |
193 | ||
cba2026a | 194 | /* Create -kernel TLB entries for BookE. */ |
d1e256fe AG |
195 | static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) |
196 | { | |
cba2026a | 197 | return 63 - clz64(size >> 10); |
d1e256fe AG |
198 | } |
199 | ||
cba2026a | 200 | static void mmubooke_create_initial_mapping(CPUPPCState *env) |
3b989d49 | 201 | { |
cba2026a | 202 | struct boot_info *bi = env->load_info; |
d1e256fe | 203 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
cba2026a AG |
204 | target_phys_addr_t size, dt_end; |
205 | int ps; | |
206 | ||
207 | /* Our initial TLB entry needs to cover everything from 0 to | |
208 | the device tree top */ | |
209 | dt_end = bi->dt_base + bi->dt_size; | |
210 | ps = booke206_page_size_to_tlb(dt_end) + 1; | |
211 | size = (ps << MAS1_TSIZE_SHIFT); | |
d1e256fe | 212 | tlb->mas1 = MAS1_VALID | size; |
cba2026a AG |
213 | tlb->mas2 = 0; |
214 | tlb->mas7_3 = 0; | |
d1e256fe | 215 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
93dd5e85 SW |
216 | |
217 | env->tlb_dirty = true; | |
3b989d49 AG |
218 | } |
219 | ||
5c145dac AG |
220 | static void mpc8544ds_cpu_reset_sec(void *opaque) |
221 | { | |
38f92da6 AF |
222 | PowerPCCPU *cpu = opaque; |
223 | CPUPPCState *env = &cpu->env; | |
5c145dac | 224 | |
38f92da6 | 225 | cpu_reset(CPU(cpu)); |
5c145dac AG |
226 | |
227 | /* Secondary CPU starts in halted state for now. Needs to change when | |
228 | implementing non-kernel boot. */ | |
229 | env->halted = 1; | |
230 | env->exception_index = EXCP_HLT; | |
3b989d49 AG |
231 | } |
232 | ||
233 | static void mpc8544ds_cpu_reset(void *opaque) | |
234 | { | |
38f92da6 AF |
235 | PowerPCCPU *cpu = opaque; |
236 | CPUPPCState *env = &cpu->env; | |
3b989d49 AG |
237 | struct boot_info *bi = env->load_info; |
238 | ||
38f92da6 | 239 | cpu_reset(CPU(cpu)); |
3b989d49 AG |
240 | |
241 | /* Set initial guest state. */ | |
5c145dac | 242 | env->halted = 0; |
3b989d49 AG |
243 | env->gpr[1] = (16<<20) - 8; |
244 | env->gpr[3] = bi->dt_base; | |
245 | env->nip = bi->entry; | |
cba2026a | 246 | mmubooke_create_initial_mapping(env); |
3b989d49 AG |
247 | } |
248 | ||
c227f099 | 249 | static void mpc8544ds_init(ram_addr_t ram_size, |
1db09b84 AJ |
250 | const char *boot_device, |
251 | const char *kernel_filename, | |
252 | const char *kernel_cmdline, | |
253 | const char *initrd_filename, | |
254 | const char *cpu_model) | |
255 | { | |
39186d8a | 256 | MemoryRegion *address_space_mem = get_system_memory(); |
2646c133 | 257 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
1db09b84 | 258 | PCIBus *pci_bus; |
e2684c0b | 259 | CPUPPCState *env = NULL; |
1db09b84 AJ |
260 | uint64_t elf_entry; |
261 | uint64_t elf_lowaddr; | |
c227f099 AL |
262 | target_phys_addr_t entry=0; |
263 | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 | 264 | target_long kernel_size=0; |
75bb6589 LY |
265 | target_ulong dt_base = 0; |
266 | target_ulong initrd_base = 0; | |
1db09b84 | 267 | target_long initrd_size=0; |
1db09b84 AJ |
268 | int i=0; |
269 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; | |
a915249f | 270 | qemu_irq **irqs, *mpic; |
be13cc7a | 271 | DeviceState *dev; |
e2684c0b | 272 | CPUPPCState *firstenv = NULL; |
1db09b84 | 273 | |
e61c36d5 | 274 | /* Setup CPUs */ |
ef250db6 AG |
275 | if (cpu_model == NULL) { |
276 | cpu_model = "e500v2_v30"; | |
277 | } | |
278 | ||
a915249f AG |
279 | irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); |
280 | irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
e61c36d5 | 281 | for (i = 0; i < smp_cpus; i++) { |
397b457d | 282 | PowerPCCPU *cpu; |
e61c36d5 | 283 | qemu_irq *input; |
397b457d AF |
284 | |
285 | cpu = cpu_ppc_init(cpu_model); | |
286 | if (cpu == NULL) { | |
e61c36d5 AG |
287 | fprintf(stderr, "Unable to initialize CPU!\n"); |
288 | exit(1); | |
289 | } | |
397b457d | 290 | env = &cpu->env; |
1db09b84 | 291 | |
e61c36d5 AG |
292 | if (!firstenv) { |
293 | firstenv = env; | |
294 | } | |
1db09b84 | 295 | |
a915249f AG |
296 | irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); |
297 | input = (qemu_irq *)env->irq_inputs; | |
298 | irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; | |
299 | irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
e61c36d5 | 300 | env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; |
3b989d49 | 301 | |
ddd1055b | 302 | ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); |
e61c36d5 AG |
303 | |
304 | /* Register reset handler */ | |
5c145dac AG |
305 | if (!i) { |
306 | /* Primary CPU */ | |
307 | struct boot_info *boot_info; | |
308 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
38f92da6 | 309 | qemu_register_reset(mpc8544ds_cpu_reset, cpu); |
5c145dac AG |
310 | env->load_info = boot_info; |
311 | } else { | |
312 | /* Secondary CPUs */ | |
38f92da6 | 313 | qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu); |
5c145dac | 314 | } |
e61c36d5 | 315 | } |
3b989d49 | 316 | |
e61c36d5 | 317 | env = firstenv; |
3b989d49 | 318 | |
1db09b84 AJ |
319 | /* Fixup Memory size on a alignment boundary */ |
320 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
321 | ||
322 | /* Register Memory */ | |
c5705a77 AK |
323 | memory_region_init_ram(ram, "mpc8544ds.ram", ram_size); |
324 | vmstate_register_ram_global(ram); | |
2646c133 | 325 | memory_region_add_subregion(address_space_mem, 0, ram); |
1db09b84 AJ |
326 | |
327 | /* MPIC */ | |
df2921d3 AK |
328 | mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, |
329 | smp_cpus, irqs, NULL); | |
a915249f AG |
330 | |
331 | if (!mpic) { | |
332 | cpu_abort(env, "MPIC failed to initialize\n"); | |
333 | } | |
1db09b84 AJ |
334 | |
335 | /* Serial */ | |
2d48377a | 336 | if (serial_hds[0]) { |
39186d8a | 337 | serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE, |
49a2942d | 338 | 0, mpic[12+26], 399193, |
2ff0c7c3 | 339 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 340 | } |
1db09b84 | 341 | |
2d48377a | 342 | if (serial_hds[1]) { |
39186d8a | 343 | serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE, |
49a2942d | 344 | 0, mpic[12+26], 399193, |
2ff0c7c3 | 345 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 346 | } |
1db09b84 | 347 | |
b0fb8423 AG |
348 | /* General Utility device */ |
349 | sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); | |
350 | ||
1db09b84 | 351 | /* PCI */ |
be13cc7a AG |
352 | dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE, |
353 | mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], | |
354 | mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], | |
355 | NULL); | |
d461e3b9 | 356 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
357 | if (!pci_bus) |
358 | printf("couldn't create PCI controller!\n"); | |
359 | ||
968d683c | 360 | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
1db09b84 AJ |
361 | |
362 | if (pci_bus) { | |
1db09b84 AJ |
363 | /* Register network interfaces. */ |
364 | for (i = 0; i < nb_nics; i++) { | |
07caea31 | 365 | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
1db09b84 AJ |
366 | } |
367 | } | |
368 | ||
5c145dac AG |
369 | /* Register spinning region */ |
370 | sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); | |
371 | ||
1db09b84 AJ |
372 | /* Load kernel. */ |
373 | if (kernel_filename) { | |
374 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL); | |
375 | if (kernel_size < 0) { | |
409dbce5 AJ |
376 | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
377 | &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); | |
1db09b84 AJ |
378 | entry = elf_entry; |
379 | loadaddr = elf_lowaddr; | |
380 | } | |
381 | /* XXX try again as binary */ | |
382 | if (kernel_size < 0) { | |
383 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
384 | kernel_filename); | |
385 | exit(1); | |
386 | } | |
387 | } | |
388 | ||
389 | /* Load initrd. */ | |
390 | if (initrd_filename) { | |
75bb6589 | 391 | initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
d7585251 PB |
392 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
393 | ram_size - initrd_base); | |
1db09b84 AJ |
394 | |
395 | if (initrd_size < 0) { | |
396 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
397 | initrd_filename); | |
398 | exit(1); | |
399 | } | |
400 | } | |
401 | ||
402 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
403 | if (kernel_filename) { | |
5c145dac | 404 | struct boot_info *boot_info; |
cba2026a | 405 | int dt_size; |
5c145dac | 406 | |
cba2026a AG |
407 | dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
408 | dt_size = mpc8544_load_device_tree(env, dt_base, ram_size, initrd_base, | |
409 | initrd_size, kernel_cmdline); | |
410 | if (dt_size < 0) { | |
1db09b84 AJ |
411 | fprintf(stderr, "couldn't load device tree\n"); |
412 | exit(1); | |
413 | } | |
414 | ||
e61c36d5 | 415 | boot_info = env->load_info; |
3b989d49 AG |
416 | boot_info->entry = entry; |
417 | boot_info->dt_base = dt_base; | |
cba2026a | 418 | boot_info->dt_size = dt_size; |
1db09b84 AJ |
419 | } |
420 | ||
3b989d49 | 421 | if (kvm_enabled()) { |
1db09b84 | 422 | kvmppc_init(); |
3b989d49 | 423 | } |
1db09b84 AJ |
424 | } |
425 | ||
f80f9ec9 | 426 | static QEMUMachine mpc8544ds_machine = { |
1db09b84 AJ |
427 | .name = "mpc8544ds", |
428 | .desc = "mpc8544ds", | |
429 | .init = mpc8544ds_init, | |
a2a67420 | 430 | .max_cpus = 15, |
1db09b84 | 431 | }; |
f80f9ec9 AL |
432 | |
433 | static void mpc8544ds_machine_init(void) | |
434 | { | |
435 | qemu_register_machine(&mpc8544ds_machine); | |
436 | } | |
437 | ||
438 | machine_init(mpc8544ds_machine_init); |