[mirror_qemu.git] / hw / ppce500_pci.c

/*
 * QEMU PowerPC E500 embedded processors pci controller emulation
 *
 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Yu Liu,     <yu.liu@freescale.com>
 *
 * This file is derived from hw/ppc4xx_pci.c,
 * the copyright for that material belongs to the original owners.
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of  the GNU General  Public License as published by
 * the Free Software Foundation;  either version 2 of the  License, or
 * (at your option) any later version.
 */

#include "hw.h"
#include "ppce500.h"
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"

#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#define pci_debug(fmt, ...)
#endif

#define PCIE500_CFGADDR       0x0
#define PCIE500_CFGDATA       0x4
#define PCIE500_REG_BASE      0xC00
#define PCIE500_REG_SIZE      (0x1000 - PCIE500_REG_BASE)

#define PPCE500_PCI_CONFIG_ADDR         0x0
#define PPCE500_PCI_CONFIG_DATA         0x4
#define PPCE500_PCI_INTACK              0x8

#define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)

#define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)

#define PCI_POTAR               0x0
#define PCI_POTEAR              0x4
#define PCI_POWBAR              0x8
#define PCI_POWAR               0x10

#define PCI_PITAR               0x0
#define PCI_PIWBAR              0x8
#define PCI_PIWBEAR             0xC
#define PCI_PIWAR               0x10

#define PPCE500_PCI_NR_POBS     5
#define PPCE500_PCI_NR_PIBS     3

struct  pci_outbound {
    uint32_t potar;
    uint32_t potear;
    uint32_t powbar;
    uint32_t powar;
};

struct pci_inbound {
    uint32_t pitar;
    uint32_t piwbar;
    uint32_t piwbear;
    uint32_t piwar;
};

struct PPCE500PCIState {
    struct pci_outbound pob[PPCE500_PCI_NR_POBS];
    struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
    uint32_t gasket_time;
    PCIHostState pci_state;
    PCIDevice *pci_dev;
};

typedef struct PPCE500PCIState PPCE500PCIState;

static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    uint32_t value = 0;

    win = addr & 0xfe0;

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        switch (addr & 0xC) {
        case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
        case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
        case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
        case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
        default: break;
        }
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        switch (addr & 0xC) {
        case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
        case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
        case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
        case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
        default: break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        value = pci->gasket_time;
        break;

    default:
        break;
    }

    pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
              win, addr, value);
    return value;
}

static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
    &pci_reg_read4,
    &pci_reg_read4,
    &pci_reg_read4,
};

static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
                               uint32_t value)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;

    win = addr & 0xfe0;

    pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
              __func__, value, win, addr);

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        switch (addr & 0xC) {
        case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
        case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
        case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
        case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
        default: break;
        };
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        switch (addr & 0xC) {
        case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
        case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
        case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
        case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
        default: break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        pci->gasket_time = value;
        break;

    default:
        break;
    };
}

static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
    &pci_reg_write4,
    &pci_reg_write4,
    &pci_reg_write4,
};

static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int devno = pci_dev->devfn >> 3, ret = 0;

    switch (devno) {
        /* Two PCI slot */
        case 0x11:
        case 0x12:
            ret = (irq_num + devno - 0x10) % 4;
            break;
        default:
            printf("Error:%s:unknown dev number\n", __func__);
    }

    pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
           pci_dev->devfn, irq_num, ret, devno);

    return ret;
}

static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);

    qemu_set_irq(pic[irq_num], level);
}

static const VMStateDescription vmstate_pci_outbound = {
    .name = "pci_outbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(potar, struct pci_outbound),
        VMSTATE_UINT32(potear, struct pci_outbound),
        VMSTATE_UINT32(powbar, struct pci_outbound),
        VMSTATE_UINT32(powar, struct pci_outbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_inbound = {
    .name = "pci_inbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(pitar, struct pci_inbound),
        VMSTATE_UINT32(piwbar, struct pci_inbound),
        VMSTATE_UINT32(piwbear, struct pci_inbound),
        VMSTATE_UINT32(piwar, struct pci_inbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppce500_pci = {
    .name = "ppce500_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPCE500PCIState),
        VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
                             vmstate_pci_outbound, struct pci_outbound),
        VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
                             vmstate_pci_outbound, struct pci_inbound),
        VMSTATE_UINT32(gasket_time, PPCE500PCIState),
        VMSTATE_END_OF_LIST()
    }
};

PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
{
    PPCE500PCIState *controller;
    PCIDevice *d;
    int index;
    static int ppce500_pci_id;

    controller = qemu_mallocz(sizeof(PPCE500PCIState));

    controller->pci_state.bus = pci_register_bus(NULL, "pci",
                                                 mpc85xx_pci_set_irq,
                                                 mpc85xx_pci_map_irq,
                                                 pci_irqs, PCI_DEVFN(0x11, 0),
                                                 4);
    d = pci_register_device(controller->pci_state.bus,
                            "host bridge", sizeof(PCIDevice),
                            0, NULL, NULL);

    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
    pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);

    controller->pci_dev = d;

    /* CFGADDR */
    index = pci_host_conf_register_mmio(&controller->pci_state,
                                        DEVICE_BIG_ENDIAN);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);

    /* CFGDATA */
    index = pci_host_data_register_mmio(&controller->pci_state,
                                        DEVICE_BIG_ENDIAN);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);

    index = cpu_register_io_memory(e500_pci_reg_read,
                                   e500_pci_reg_write, controller,
                                   DEVICE_NATIVE_ENDIAN);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers + PCIE500_REG_BASE,
                                   PCIE500_REG_SIZE, index);

    /* XXX load/save code not tested. */
    vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci,
                     controller);

    return controller->pci_state.bus;

free:
    printf("%s error\n", __func__);
    qemu_free(controller);
    return NULL;
}
Commit	Line	Data
74c62ba8 AJ	1	/*
	2	* QEMU PowerPC E500 embedded processors pci controller emulation
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
	5	*
	6	* Author: Yu Liu, <yu.liu@freescale.com>
	7	*
	8	* This file is derived from hw/ppc4xx_pci.c,
	9	* the copyright for that material belongs to the original owners.
	10	*
	11	* This is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include "hw.h"
74c62ba8	18	#include "ppce500.h"
74c62ba8 AJ	19	#include "pci.h"
	20	#include "pci_host.h"
	21	#include "bswap.h"
74c62ba8 AJ	22
74c62ba8 AJ	23	#ifdef DEBUG_PCI
001faf32	24	#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8	25	#else
001faf32	26	#define pci_debug(fmt, ...)
74c62ba8 AJ	27	#endif
	28
	29	#define PCIE500_CFGADDR 0x0
	30	#define PCIE500_CFGDATA 0x4
	31	#define PCIE500_REG_BASE 0xC00
	32	#define PCIE500_REG_SIZE (0x1000 - PCIE500_REG_BASE)
	33
	34	#define PPCE500_PCI_CONFIG_ADDR 0x0
	35	#define PPCE500_PCI_CONFIG_DATA 0x4
	36	#define PPCE500_PCI_INTACK 0x8
	37
	38	#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
	39	#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
	40	#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
	41	#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
	42	#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
	43	#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
	44	#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
	45
	46	#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
	47
	48	#define PCI_POTAR 0x0
	49	#define PCI_POTEAR 0x4
	50	#define PCI_POWBAR 0x8
	51	#define PCI_POWAR 0x10
	52
	53	#define PCI_PITAR 0x0
	54	#define PCI_PIWBAR 0x8
	55	#define PCI_PIWBEAR 0xC
	56	#define PCI_PIWAR 0x10
	57
	58	#define PPCE500_PCI_NR_POBS 5
	59	#define PPCE500_PCI_NR_PIBS 3
	60
	61	struct pci_outbound {
	62	uint32_t potar;
	63	uint32_t potear;
	64	uint32_t powbar;
	65	uint32_t powar;
	66	};
	67
	68	struct pci_inbound {
	69	uint32_t pitar;
	70	uint32_t piwbar;
	71	uint32_t piwbear;
	72	uint32_t piwar;
	73	};
	74
	75	struct PPCE500PCIState {
	76	struct pci_outbound pob[PPCE500_PCI_NR_POBS];
	77	struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
	78	uint32_t gasket_time;
b19159e8 AL	79	PCIHostState pci_state;
b19159e8 AL	80	PCIDevice *pci_dev;
74c62ba8 AJ	81	};
	82
	83	typedef struct PPCE500PCIState PPCE500PCIState;
	84
c227f099	85	static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
74c62ba8 AJ	86	{
	87	PPCE500PCIState *pci = opaque;
	88	unsigned long win;
	89	uint32_t value = 0;
	90
	91	win = addr & 0xfe0;
	92
	93	switch (win) {
	94	case PPCE500_PCI_OW1:
	95	case PPCE500_PCI_OW2:
	96	case PPCE500_PCI_OW3:
	97	case PPCE500_PCI_OW4:
	98	switch (addr & 0xC) {
	99	case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
	100	case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
	101	case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
	102	case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
	103	default: break;
	104	}
	105	break;
	106
	107	case PPCE500_PCI_IW3:
	108	case PPCE500_PCI_IW2:
	109	case PPCE500_PCI_IW1:
	110	switch (addr & 0xC) {
	111	case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
	112	case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
	113	case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
	114	case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
	115	default: break;
	116	};
	117	break;
	118
	119	case PPCE500_PCI_GASKET_TIMR:
	120	value = pci->gasket_time;
	121	break;
	122
	123	default:
	124	break;
	125	}
	126
c0a2a096 BS	127	pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
c0a2a096 BS	128	win, addr, value);
74c62ba8 AJ	129	return value;
	130	}
	131
d60efc6b	132	static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
74c62ba8 AJ	133	&pci_reg_read4,
	134	&pci_reg_read4,
	135	&pci_reg_read4,
	136	};
	137
c227f099	138	static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
74c62ba8 AJ	139	uint32_t value)
	140	{
	141	PPCE500PCIState *pci = opaque;
	142	unsigned long win;
	143
	144	win = addr & 0xfe0;
	145
c0a2a096 BS	146	pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
c0a2a096 BS	147	__func__, value, win, addr);
74c62ba8 AJ	148
	149	switch (win) {
	150	case PPCE500_PCI_OW1:
	151	case PPCE500_PCI_OW2:
	152	case PPCE500_PCI_OW3:
	153	case PPCE500_PCI_OW4:
	154	switch (addr & 0xC) {
	155	case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
	156	case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
	157	case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
	158	case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
	159	default: break;
	160	};
	161	break;
	162
	163	case PPCE500_PCI_IW3:
	164	case PPCE500_PCI_IW2:
	165	case PPCE500_PCI_IW1:
	166	switch (addr & 0xC) {
	167	case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
	168	case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
	169	case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
	170	case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
	171	default: break;
	172	};
	173	break;
	174
	175	case PPCE500_PCI_GASKET_TIMR:
	176	pci->gasket_time = value;
	177	break;
	178
	179	default:
	180	break;
	181	};
	182	}
	183
d60efc6b	184	static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
74c62ba8 AJ	185	&pci_reg_write4,
	186	&pci_reg_write4,
	187	&pci_reg_write4,
	188	};
	189
	190	static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	191	{
	192	int devno = pci_dev->devfn >> 3, ret = 0;
	193
	194	switch (devno) {
	195	/* Two PCI slot */
	196	case 0x11:
	197	case 0x12:
	198	ret = (irq_num + devno - 0x10) % 4;
	199	break;
	200	default:
72b310e9	201	printf("Error:%s:unknown dev number\n", __func__);
74c62ba8 AJ	202	}
	203
	204	pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
	205	pci_dev->devfn, irq_num, ret, devno);
	206
	207	return ret;
	208	}
	209
5d4e84c8	210	static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
74c62ba8	211	{
5d4e84c8 JQ	212	qemu_irq *pic = opaque;
5d4e84c8 JQ	213
74c62ba8 AJ	214	pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
	215
	216	qemu_set_irq(pic[irq_num], level);
	217	}
	218
e0433ecc JQ	219	static const VMStateDescription vmstate_pci_outbound = {
	220	.name = "pci_outbound",
	221	.version_id = 0,
	222	.minimum_version_id = 0,
	223	.minimum_version_id_old = 0,
	224	.fields = (VMStateField[]) {
	225	VMSTATE_UINT32(potar, struct pci_outbound),
	226	VMSTATE_UINT32(potear, struct pci_outbound),
	227	VMSTATE_UINT32(powbar, struct pci_outbound),
	228	VMSTATE_UINT32(powar, struct pci_outbound),
	229	VMSTATE_END_OF_LIST()
74c62ba8	230	}
e0433ecc	231	};
74c62ba8	232
e0433ecc JQ	233	static const VMStateDescription vmstate_pci_inbound = {
	234	.name = "pci_inbound",
	235	.version_id = 0,
	236	.minimum_version_id = 0,
	237	.minimum_version_id_old = 0,
	238	.fields = (VMStateField[]) {
	239	VMSTATE_UINT32(pitar, struct pci_inbound),
	240	VMSTATE_UINT32(piwbar, struct pci_inbound),
	241	VMSTATE_UINT32(piwbear, struct pci_inbound),
	242	VMSTATE_UINT32(piwar, struct pci_inbound),
	243	VMSTATE_END_OF_LIST()
74c62ba8	244	}
e0433ecc	245	};
74c62ba8	246
e0433ecc JQ	247	static const VMStateDescription vmstate_ppce500_pci = {
	248	.name = "ppce500_pci",
	249	.version_id = 1,
	250	.minimum_version_id = 1,
	251	.minimum_version_id_old = 1,
	252	.fields = (VMStateField[]) {
	253	VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPCE500PCIState),
	254	VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
	255	vmstate_pci_outbound, struct pci_outbound),
	256	VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
	257	vmstate_pci_outbound, struct pci_inbound),
	258	VMSTATE_UINT32(gasket_time, PPCE500PCIState),
	259	VMSTATE_END_OF_LIST()
74c62ba8	260	}
e0433ecc	261	};
74c62ba8	262
c227f099	263	PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
74c62ba8	264	{
b19159e8	265	PPCE500PCIState *controller;
74c62ba8	266	PCIDevice *d;
b19159e8	267	int index;
74c62ba8 AJ	268	static int ppce500_pci_id;
74c62ba8 AJ	269
b19159e8	270	controller = qemu_mallocz(sizeof(PPCE500PCIState));
74c62ba8	271
b19159e8 AL	272	controller->pci_state.bus = pci_register_bus(NULL, "pci",
	273	mpc85xx_pci_set_irq,
	274	mpc85xx_pci_map_irq,
	275	pci_irqs, PCI_DEVFN(0x11, 0),
	276	4);
	277	d = pci_register_device(controller->pci_state.bus,
	278	"host bridge", sizeof(PCIDevice),
	279	0, NULL, NULL);
74c62ba8	280
b19159e8 AL	281	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
	282	pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
	283	pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);
74c62ba8	284
b19159e8	285	controller->pci_dev = d;
74c62ba8 AJ	286
74c62ba8 AJ	287	/* CFGADDR */
6ebf5905 AG	288	index = pci_host_conf_register_mmio(&controller->pci_state,
6ebf5905 AG	289	DEVICE_BIG_ENDIAN);
74c62ba8	290	if (index < 0)
b19159e8	291	goto free;
74c62ba8 AJ	292	cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
	293
	294	/* CFGDATA */
6ebf5905 AG	295	index = pci_host_data_register_mmio(&controller->pci_state,
6ebf5905 AG	296	DEVICE_BIG_ENDIAN);
74c62ba8	297	if (index < 0)
b19159e8	298	goto free;
74c62ba8 AJ	299	cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
74c62ba8 AJ	300
1eed09cb	301	index = cpu_register_io_memory(e500_pci_reg_read,
2507c12a AG	302	e500_pci_reg_write, controller,
2507c12a AG	303	DEVICE_NATIVE_ENDIAN);
74c62ba8	304	if (index < 0)
b19159e8	305	goto free;
74c62ba8 AJ	306	cpu_register_physical_memory(registers + PCIE500_REG_BASE,
74c62ba8 AJ	307	PCIE500_REG_SIZE, index);
13b7fdef	308
b19159e8	309	/* XXX load/save code not tested. */
e0433ecc JQ	310	vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci,
e0433ecc JQ	311	controller);
74c62ba8	312
b19159e8	313	return controller->pci_state.bus;
74c62ba8	314
b19159e8 AL	315	free:
	316	printf("%s error\n", __func__);
	317	qemu_free(controller);
	318	return NULL;
74c62ba8	319	}