[mirror_qemu.git] / hw / ppce500_pci.c

/*
 * QEMU PowerPC E500 embedded processors pci controller emulation
 *
 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Yu Liu,     <yu.liu@freescale.com>
 *
 * This file is derived from hw/ppc4xx_pci.c,
 * the copyright for that material belongs to the original owners.
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of  the GNU General  Public License as published by
 * the Free Software Foundation;  either version 2 of the  License, or
 * (at your option) any later version.
 */

#include "hw.h"
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"

#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#define pci_debug(fmt, ...)
#endif

#define PCIE500_CFGADDR       0x0
#define PCIE500_CFGDATA       0x4
#define PCIE500_REG_BASE      0xC00
#define PCIE500_ALL_SIZE      0x1000
#define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)

#define PPCE500_PCI_CONFIG_ADDR         0x0
#define PPCE500_PCI_CONFIG_DATA         0x4
#define PPCE500_PCI_INTACK              0x8

#define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)

#define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)

#define PCI_POTAR               0x0
#define PCI_POTEAR              0x4
#define PCI_POWBAR              0x8
#define PCI_POWAR               0x10

#define PCI_PITAR               0x0
#define PCI_PIWBAR              0x8
#define PCI_PIWBEAR             0xC
#define PCI_PIWAR               0x10

#define PPCE500_PCI_NR_POBS     5
#define PPCE500_PCI_NR_PIBS     3

struct  pci_outbound {
    uint32_t potar;
    uint32_t potear;
    uint32_t powbar;
    uint32_t powar;
};

struct pci_inbound {
    uint32_t pitar;
    uint32_t piwbar;
    uint32_t piwbear;
    uint32_t piwar;
};

struct PPCE500PCIState {
    PCIHostState pci_state;
    struct pci_outbound pob[PPCE500_PCI_NR_POBS];
    struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
    uint32_t gasket_time;
    qemu_irq irq[4];
    /* mmio maps */
    MemoryRegion container;
    MemoryRegion iomem;
};

typedef struct PPCE500PCIState PPCE500PCIState;

static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
                              unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    uint32_t value = 0;
    int idx;

    win = addr & 0xfe0;

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            value = pci->pob[idx].potar;
            break;
        case PCI_POTEAR:
            value = pci->pob[idx].potear;
            break;
        case PCI_POWBAR:
            value = pci->pob[idx].powbar;
            break;
        case PCI_POWAR:
            value = pci->pob[idx].powar;
            break;
        default:
            break;
        }
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            value = pci->pib[idx].pitar;
            break;
        case PCI_PIWBAR:
            value = pci->pib[idx].piwbar;
            break;
        case PCI_PIWBEAR:
            value = pci->pib[idx].piwbear;
            break;
        case PCI_PIWAR:
            value = pci->pib[idx].piwar;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        value = pci->gasket_time;
        break;

    default:
        break;
    }

    pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
              win, addr, value);
    return value;
}

static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
                           uint64_t value, unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    int idx;

    win = addr & 0xfe0;

    pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
              __func__, (unsigned)value, win, addr);

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            pci->pob[idx].potar = value;
            break;
        case PCI_POTEAR:
            pci->pob[idx].potear = value;
            break;
        case PCI_POWBAR:
            pci->pob[idx].powbar = value;
            break;
        case PCI_POWAR:
            pci->pob[idx].powar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            pci->pib[idx].pitar = value;
            break;
        case PCI_PIWBAR:
            pci->pib[idx].piwbar = value;
            break;
        case PCI_PIWBEAR:
            pci->pib[idx].piwbear = value;
            break;
        case PCI_PIWAR:
            pci->pib[idx].piwar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        pci->gasket_time = value;
        break;

    default:
        break;
    };
}

static const MemoryRegionOps e500_pci_reg_ops = {
    .read = pci_reg_read4,
    .write = pci_reg_write4,
    .endianness = DEVICE_BIG_ENDIAN,
};

static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int devno = pci_dev->devfn >> 3, ret = 0;

    switch (devno) {
        /* Two PCI slot */
        case 0x11:
        case 0x12:
            ret = (irq_num + devno - 0x10) % 4;
            break;
        default:
            printf("Error:%s:unknown dev number\n", __func__);
    }

    pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
           pci_dev->devfn, irq_num, ret, devno);

    return ret;
}

static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);

    qemu_set_irq(pic[irq_num], level);
}

static const VMStateDescription vmstate_pci_outbound = {
    .name = "pci_outbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(potar, struct pci_outbound),
        VMSTATE_UINT32(potear, struct pci_outbound),
        VMSTATE_UINT32(powbar, struct pci_outbound),
        VMSTATE_UINT32(powar, struct pci_outbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_inbound = {
    .name = "pci_inbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(pitar, struct pci_inbound),
        VMSTATE_UINT32(piwbar, struct pci_inbound),
        VMSTATE_UINT32(piwbear, struct pci_inbound),
        VMSTATE_UINT32(piwar, struct pci_inbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppce500_pci = {
    .name = "ppce500_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
                             vmstate_pci_outbound, struct pci_outbound),
        VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
                             vmstate_pci_outbound, struct pci_inbound),
        VMSTATE_UINT32(gasket_time, PPCE500PCIState),
        VMSTATE_END_OF_LIST()
    }
};

#include "exec-memory.h"

static int e500_pcihost_initfn(SysBusDevice *dev)
{
    PCIHostState *h;
    PPCE500PCIState *s;
    PCIBus *b;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *address_space_io = get_system_io();

    h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
    s = DO_UPCAST(PPCE500PCIState, pci_state, h);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(dev, &s->irq[i]);
    }

    b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
                         mpc85xx_pci_map_irq, s->irq, address_space_mem,
                         address_space_io, PCI_DEVFN(0x11, 0), 4);
    s->pci_state.bus = b;

    pci_create_simple(b, 0, "e500-host-bridge");

    memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
                          "pci.reg", PCIE500_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
    sysbus_init_mmio(dev, &s->container);

    return 0;
}

static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->vendor_id = PCI_VENDOR_ID_FREESCALE;
    k->device_id = PCI_DEVICE_ID_MPC8533E;
    k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
}

static DeviceInfo e500_host_bridge_info = {
    .name = "e500-host-bridge",
    .desc = "Host bridge",
    .size = sizeof(PCIDevice),
    .class_init = e500_host_bridge_class_init,
};

static void e500_pcihost_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = e500_pcihost_initfn;
}

static DeviceInfo e500_pcihost_info = {
    .name = "e500-pcihost",
    .size = sizeof(PPCE500PCIState),
    .vmsd = &vmstate_ppce500_pci,
    .class_init = e500_pcihost_class_init,
};

static void e500_pci_register(void)
{
    sysbus_register_withprop(&e500_pcihost_info);
    pci_qdev_register(&e500_host_bridge_info);
}
device_init(e500_pci_register);
Commit	Line	Data
74c62ba8 AJ	1	/*
	2	* QEMU PowerPC E500 embedded processors pci controller emulation
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
	5	*
	6	* Author: Yu Liu, <yu.liu@freescale.com>
	7	*
	8	* This file is derived from hw/ppc4xx_pci.c,
	9	* the copyright for that material belongs to the original owners.
	10	*
	11	* This is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include "hw.h"
74c62ba8 AJ	18	#include "pci.h"
	19	#include "pci_host.h"
	20	#include "bswap.h"
74c62ba8 AJ	21
74c62ba8 AJ	22	#ifdef DEBUG_PCI
001faf32	23	#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8	24	#else
001faf32	25	#define pci_debug(fmt, ...)
74c62ba8 AJ	26	#endif
	27
	28	#define PCIE500_CFGADDR 0x0
	29	#define PCIE500_CFGDATA 0x4
	30	#define PCIE500_REG_BASE 0xC00
be13cc7a AG	31	#define PCIE500_ALL_SIZE 0x1000
be13cc7a AG	32	#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
74c62ba8 AJ	33
	34	#define PPCE500_PCI_CONFIG_ADDR 0x0
	35	#define PPCE500_PCI_CONFIG_DATA 0x4
	36	#define PPCE500_PCI_INTACK 0x8
	37
	38	#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
	39	#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
	40	#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
	41	#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
	42	#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
	43	#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
	44	#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
	45
	46	#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
	47
	48	#define PCI_POTAR 0x0
	49	#define PCI_POTEAR 0x4
	50	#define PCI_POWBAR 0x8
	51	#define PCI_POWAR 0x10
	52
	53	#define PCI_PITAR 0x0
	54	#define PCI_PIWBAR 0x8
	55	#define PCI_PIWBEAR 0xC
	56	#define PCI_PIWAR 0x10
	57
	58	#define PPCE500_PCI_NR_POBS 5
	59	#define PPCE500_PCI_NR_PIBS 3
	60
	61	struct pci_outbound {
	62	uint32_t potar;
	63	uint32_t potear;
	64	uint32_t powbar;
	65	uint32_t powar;
	66	};
	67
	68	struct pci_inbound {
	69	uint32_t pitar;
	70	uint32_t piwbar;
	71	uint32_t piwbear;
	72	uint32_t piwar;
	73	};
	74
	75	struct PPCE500PCIState {
be13cc7a	76	PCIHostState pci_state;
74c62ba8 AJ	77	struct pci_outbound pob[PPCE500_PCI_NR_POBS];
	78	struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
	79	uint32_t gasket_time;
be13cc7a AG	80	qemu_irq irq[4];
be13cc7a AG	81	/* mmio maps */
cb4e15c7	82	MemoryRegion container;
cd5cba79	83	MemoryRegion iomem;
74c62ba8 AJ	84	};
	85
	86	typedef struct PPCE500PCIState PPCE500PCIState;
	87
cd5cba79 AK	88	static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
cd5cba79 AK	89	unsigned size)
74c62ba8 AJ	90	{
	91	PPCE500PCIState *pci = opaque;
	92	unsigned long win;
	93	uint32_t value = 0;
eeae2e7b	94	int idx;
74c62ba8 AJ	95
	96	win = addr & 0xfe0;
	97
	98	switch (win) {
	99	case PPCE500_PCI_OW1:
	100	case PPCE500_PCI_OW2:
	101	case PPCE500_PCI_OW3:
	102	case PPCE500_PCI_OW4:
eeae2e7b	103	idx = (addr >> 5) & 0x7;
74c62ba8	104	switch (addr & 0xC) {
6875dc8e	105	case PCI_POTAR:
eeae2e7b	106	value = pci->pob[idx].potar;
6875dc8e LY	107	break;
6875dc8e LY	108	case PCI_POTEAR:
eeae2e7b	109	value = pci->pob[idx].potear;
6875dc8e LY	110	break;
6875dc8e LY	111	case PCI_POWBAR:
eeae2e7b	112	value = pci->pob[idx].powbar;
6875dc8e LY	113	break;
6875dc8e LY	114	case PCI_POWAR:
eeae2e7b	115	value = pci->pob[idx].powar;
6875dc8e LY	116	break;
	117	default:
	118	break;
74c62ba8 AJ	119	}
	120	break;
	121
	122	case PPCE500_PCI_IW3:
	123	case PPCE500_PCI_IW2:
	124	case PPCE500_PCI_IW1:
eeae2e7b	125	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	126	switch (addr & 0xC) {
6875dc8e	127	case PCI_PITAR:
eeae2e7b	128	value = pci->pib[idx].pitar;
6875dc8e LY	129	break;
6875dc8e LY	130	case PCI_PIWBAR:
eeae2e7b	131	value = pci->pib[idx].piwbar;
6875dc8e LY	132	break;
6875dc8e LY	133	case PCI_PIWBEAR:
eeae2e7b	134	value = pci->pib[idx].piwbear;
6875dc8e LY	135	break;
6875dc8e LY	136	case PCI_PIWAR:
eeae2e7b	137	value = pci->pib[idx].piwar;
6875dc8e LY	138	break;
	139	default:
	140	break;
74c62ba8 AJ	141	};
	142	break;
	143
	144	case PPCE500_PCI_GASKET_TIMR:
	145	value = pci->gasket_time;
	146	break;
	147
	148	default:
	149	break;
	150	}
	151
c0a2a096 BS	152	pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
c0a2a096 BS	153	win, addr, value);
74c62ba8 AJ	154	return value;
	155	}
	156
c227f099	157	static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
cd5cba79	158	uint64_t value, unsigned size)
74c62ba8 AJ	159	{
	160	PPCE500PCIState *pci = opaque;
	161	unsigned long win;
eeae2e7b	162	int idx;
74c62ba8 AJ	163
	164	win = addr & 0xfe0;
	165
c0a2a096	166	pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
cd5cba79	167	__func__, (unsigned)value, win, addr);
74c62ba8 AJ	168
	169	switch (win) {
	170	case PPCE500_PCI_OW1:
	171	case PPCE500_PCI_OW2:
	172	case PPCE500_PCI_OW3:
	173	case PPCE500_PCI_OW4:
eeae2e7b	174	idx = (addr >> 5) & 0x7;
74c62ba8	175	switch (addr & 0xC) {
6875dc8e	176	case PCI_POTAR:
eeae2e7b	177	pci->pob[idx].potar = value;
6875dc8e LY	178	break;
6875dc8e LY	179	case PCI_POTEAR:
eeae2e7b	180	pci->pob[idx].potear = value;
6875dc8e LY	181	break;
6875dc8e LY	182	case PCI_POWBAR:
eeae2e7b	183	pci->pob[idx].powbar = value;
6875dc8e LY	184	break;
6875dc8e LY	185	case PCI_POWAR:
eeae2e7b	186	pci->pob[idx].powar = value;
6875dc8e LY	187	break;
	188	default:
	189	break;
74c62ba8 AJ	190	};
	191	break;
	192
	193	case PPCE500_PCI_IW3:
	194	case PPCE500_PCI_IW2:
	195	case PPCE500_PCI_IW1:
eeae2e7b	196	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	197	switch (addr & 0xC) {
6875dc8e	198	case PCI_PITAR:
eeae2e7b	199	pci->pib[idx].pitar = value;
6875dc8e LY	200	break;
6875dc8e LY	201	case PCI_PIWBAR:
eeae2e7b	202	pci->pib[idx].piwbar = value;
6875dc8e LY	203	break;
6875dc8e LY	204	case PCI_PIWBEAR:
eeae2e7b	205	pci->pib[idx].piwbear = value;
6875dc8e LY	206	break;
6875dc8e LY	207	case PCI_PIWAR:
eeae2e7b	208	pci->pib[idx].piwar = value;
6875dc8e LY	209	break;
	210	default:
	211	break;
74c62ba8 AJ	212	};
	213	break;
	214
	215	case PPCE500_PCI_GASKET_TIMR:
	216	pci->gasket_time = value;
	217	break;
	218
	219	default:
	220	break;
	221	};
	222	}
	223
cd5cba79 AK	224	static const MemoryRegionOps e500_pci_reg_ops = {
	225	.read = pci_reg_read4,
	226	.write = pci_reg_write4,
	227	.endianness = DEVICE_BIG_ENDIAN,
74c62ba8 AJ	228	};
	229
	230	static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	231	{
	232	int devno = pci_dev->devfn >> 3, ret = 0;
	233
	234	switch (devno) {
	235	/* Two PCI slot */
	236	case 0x11:
	237	case 0x12:
	238	ret = (irq_num + devno - 0x10) % 4;
	239	break;
	240	default:
72b310e9	241	printf("Error:%s:unknown dev number\n", __func__);
74c62ba8 AJ	242	}
	243
	244	pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
	245	pci_dev->devfn, irq_num, ret, devno);
	246
	247	return ret;
	248	}
	249
5d4e84c8	250	static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
74c62ba8	251	{
5d4e84c8 JQ	252	qemu_irq *pic = opaque;
5d4e84c8 JQ	253
74c62ba8 AJ	254	pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
	255
	256	qemu_set_irq(pic[irq_num], level);
	257	}
	258
e0433ecc JQ	259	static const VMStateDescription vmstate_pci_outbound = {
	260	.name = "pci_outbound",
	261	.version_id = 0,
	262	.minimum_version_id = 0,
	263	.minimum_version_id_old = 0,
	264	.fields = (VMStateField[]) {
	265	VMSTATE_UINT32(potar, struct pci_outbound),
	266	VMSTATE_UINT32(potear, struct pci_outbound),
	267	VMSTATE_UINT32(powbar, struct pci_outbound),
	268	VMSTATE_UINT32(powar, struct pci_outbound),
	269	VMSTATE_END_OF_LIST()
74c62ba8	270	}
e0433ecc	271	};
74c62ba8	272
e0433ecc JQ	273	static const VMStateDescription vmstate_pci_inbound = {
	274	.name = "pci_inbound",
	275	.version_id = 0,
	276	.minimum_version_id = 0,
	277	.minimum_version_id_old = 0,
	278	.fields = (VMStateField[]) {
	279	VMSTATE_UINT32(pitar, struct pci_inbound),
	280	VMSTATE_UINT32(piwbar, struct pci_inbound),
	281	VMSTATE_UINT32(piwbear, struct pci_inbound),
	282	VMSTATE_UINT32(piwar, struct pci_inbound),
	283	VMSTATE_END_OF_LIST()
74c62ba8	284	}
e0433ecc	285	};
74c62ba8	286
e0433ecc JQ	287	static const VMStateDescription vmstate_ppce500_pci = {
	288	.name = "ppce500_pci",
	289	.version_id = 1,
	290	.minimum_version_id = 1,
	291	.minimum_version_id_old = 1,
	292	.fields = (VMStateField[]) {
e0433ecc JQ	293	VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
	294	vmstate_pci_outbound, struct pci_outbound),
	295	VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
	296	vmstate_pci_outbound, struct pci_inbound),
	297	VMSTATE_UINT32(gasket_time, PPCE500PCIState),
	298	VMSTATE_END_OF_LIST()
74c62ba8	299	}
e0433ecc	300	};
74c62ba8	301
1e39101c AK	302	#include "exec-memory.h"
1e39101c AK	303
be13cc7a AG	304	static int e500_pcihost_initfn(SysBusDevice *dev)
	305	{
	306	PCIHostState *h;
	307	PPCE500PCIState *s;
	308	PCIBus *b;
	309	int i;
aee97b84 AK	310	MemoryRegion *address_space_mem = get_system_memory();
aee97b84 AK	311	MemoryRegion *address_space_io = get_system_io();
be13cc7a AG	312
	313	h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
	314	s = DO_UPCAST(PPCE500PCIState, pci_state, h);
	315
	316	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
	317	sysbus_init_irq(dev, &s->irq[i]);
	318	}
	319
	320	b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
aee97b84 AK	321	mpc85xx_pci_map_irq, s->irq, address_space_mem,
aee97b84 AK	322	address_space_io, PCI_DEVFN(0x11, 0), 4);
be13cc7a AG	323	s->pci_state.bus = b;
	324
	325	pci_create_simple(b, 0, "e500-host-bridge");
	326
cb4e15c7	327	memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
d0ed8076 AK	328	memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
	329	"pci-conf-idx", 4);
	330	memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
	331	"pci-conf-data", 4);
cd5cba79 AK	332	memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
cd5cba79 AK	333	"pci.reg", PCIE500_REG_SIZE);
cb4e15c7 BC	334	memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
	335	memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
	336	memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
	337	sysbus_init_mmio(dev, &s->container);
be13cc7a AG	338
	339	return 0;
	340	}
	341
40021f08 AL	342	static void e500_host_bridge_class_init(ObjectClass klass, void data)
	343	{
	344	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	345
	346	k->vendor_id = PCI_VENDOR_ID_FREESCALE;
	347	k->device_id = PCI_DEVICE_ID_MPC8533E;
	348	k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
	349	}
	350
	351	static DeviceInfo e500_host_bridge_info = {
	352	.name = "e500-host-bridge",
	353	.desc = "Host bridge",
	354	.size = sizeof(PCIDevice),
	355	.class_init = e500_host_bridge_class_init,
be13cc7a AG	356	};
be13cc7a AG	357
999e12bb AL	358	static void e500_pcihost_class_init(ObjectClass klass, void data)
	359	{
	360	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	361
	362	k->init = e500_pcihost_initfn;
	363	}
	364
	365	static DeviceInfo e500_pcihost_info = {
	366	.name = "e500-pcihost",
	367	.size = sizeof(PPCE500PCIState),
	368	.vmsd = &vmstate_ppce500_pci,
	369	.class_init = e500_pcihost_class_init,
be13cc7a AG	370	};
	371
	372	static void e500_pci_register(void)
74c62ba8	373	{
be13cc7a AG	374	sysbus_register_withprop(&e500_pcihost_info);
be13cc7a AG	375	pci_qdev_register(&e500_host_bridge_info);
74c62ba8	376	}
be13cc7a	377	device_init(e500_pci_register);