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Commit | Line | Data |
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74c62ba8 AJ |
1 | /* |
2 | * QEMU PowerPC E500 embedded processors pci controller emulation | |
3 | * | |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc4xx_pci.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
3eddc1be | 18 | #include "hw/ppc/e500-ccsr.h" |
74c62ba8 AJ |
19 | #include "pci.h" |
20 | #include "pci_host.h" | |
21 | #include "bswap.h" | |
74c62ba8 AJ |
22 | |
23 | #ifdef DEBUG_PCI | |
001faf32 | 24 | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
74c62ba8 | 25 | #else |
001faf32 | 26 | #define pci_debug(fmt, ...) |
74c62ba8 AJ |
27 | #endif |
28 | ||
29 | #define PCIE500_CFGADDR 0x0 | |
30 | #define PCIE500_CFGDATA 0x4 | |
31 | #define PCIE500_REG_BASE 0xC00 | |
be13cc7a AG |
32 | #define PCIE500_ALL_SIZE 0x1000 |
33 | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) | |
74c62ba8 | 34 | |
a1bc20df AG |
35 | #define PCIE500_PCI_IOLEN 0x10000ULL |
36 | ||
74c62ba8 AJ |
37 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
38 | #define PPCE500_PCI_CONFIG_DATA 0x4 | |
39 | #define PPCE500_PCI_INTACK 0x8 | |
40 | ||
41 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) | |
42 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) | |
43 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) | |
44 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) | |
45 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) | |
46 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) | |
47 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) | |
48 | ||
49 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) | |
50 | ||
51 | #define PCI_POTAR 0x0 | |
52 | #define PCI_POTEAR 0x4 | |
53 | #define PCI_POWBAR 0x8 | |
54 | #define PCI_POWAR 0x10 | |
55 | ||
56 | #define PCI_PITAR 0x0 | |
57 | #define PCI_PIWBAR 0x8 | |
58 | #define PCI_PIWBEAR 0xC | |
59 | #define PCI_PIWAR 0x10 | |
60 | ||
61 | #define PPCE500_PCI_NR_POBS 5 | |
62 | #define PPCE500_PCI_NR_PIBS 3 | |
63 | ||
64 | struct pci_outbound { | |
65 | uint32_t potar; | |
66 | uint32_t potear; | |
67 | uint32_t powbar; | |
68 | uint32_t powar; | |
69 | }; | |
70 | ||
71 | struct pci_inbound { | |
72 | uint32_t pitar; | |
73 | uint32_t piwbar; | |
74 | uint32_t piwbear; | |
75 | uint32_t piwar; | |
76 | }; | |
77 | ||
9c1a61f0 AF |
78 | #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" |
79 | ||
80 | #define PPC_E500_PCI_HOST_BRIDGE(obj) \ | |
81 | OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE) | |
82 | ||
74c62ba8 | 83 | struct PPCE500PCIState { |
67c332fd | 84 | PCIHostState parent_obj; |
9c1a61f0 | 85 | |
74c62ba8 AJ |
86 | struct pci_outbound pob[PPCE500_PCI_NR_POBS]; |
87 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; | |
88 | uint32_t gasket_time; | |
be13cc7a | 89 | qemu_irq irq[4]; |
eafb325f | 90 | uint32_t first_slot; |
be13cc7a | 91 | /* mmio maps */ |
cb4e15c7 | 92 | MemoryRegion container; |
cd5cba79 | 93 | MemoryRegion iomem; |
a1bc20df | 94 | MemoryRegion pio; |
74c62ba8 AJ |
95 | }; |
96 | ||
3eddc1be BB |
97 | #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" |
98 | #define PPC_E500_PCI_BRIDGE(obj) \ | |
99 | OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE) | |
100 | ||
101 | struct PPCE500PCIBridgeState { | |
102 | /*< private >*/ | |
103 | PCIDevice parent; | |
104 | /*< public >*/ | |
105 | ||
106 | MemoryRegion bar0; | |
107 | }; | |
108 | ||
109 | typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState; | |
74c62ba8 AJ |
110 | typedef struct PPCE500PCIState PPCE500PCIState; |
111 | ||
a8170e5e | 112 | static uint64_t pci_reg_read4(void *opaque, hwaddr addr, |
cd5cba79 | 113 | unsigned size) |
74c62ba8 AJ |
114 | { |
115 | PPCE500PCIState *pci = opaque; | |
116 | unsigned long win; | |
117 | uint32_t value = 0; | |
eeae2e7b | 118 | int idx; |
74c62ba8 AJ |
119 | |
120 | win = addr & 0xfe0; | |
121 | ||
122 | switch (win) { | |
123 | case PPCE500_PCI_OW1: | |
124 | case PPCE500_PCI_OW2: | |
125 | case PPCE500_PCI_OW3: | |
126 | case PPCE500_PCI_OW4: | |
eeae2e7b | 127 | idx = (addr >> 5) & 0x7; |
74c62ba8 | 128 | switch (addr & 0xC) { |
6875dc8e | 129 | case PCI_POTAR: |
eeae2e7b | 130 | value = pci->pob[idx].potar; |
6875dc8e LY |
131 | break; |
132 | case PCI_POTEAR: | |
eeae2e7b | 133 | value = pci->pob[idx].potear; |
6875dc8e LY |
134 | break; |
135 | case PCI_POWBAR: | |
eeae2e7b | 136 | value = pci->pob[idx].powbar; |
6875dc8e LY |
137 | break; |
138 | case PCI_POWAR: | |
eeae2e7b | 139 | value = pci->pob[idx].powar; |
6875dc8e LY |
140 | break; |
141 | default: | |
142 | break; | |
74c62ba8 AJ |
143 | } |
144 | break; | |
145 | ||
146 | case PPCE500_PCI_IW3: | |
147 | case PPCE500_PCI_IW2: | |
148 | case PPCE500_PCI_IW1: | |
eeae2e7b | 149 | idx = ((addr >> 5) & 0x3) - 1; |
74c62ba8 | 150 | switch (addr & 0xC) { |
6875dc8e | 151 | case PCI_PITAR: |
eeae2e7b | 152 | value = pci->pib[idx].pitar; |
6875dc8e LY |
153 | break; |
154 | case PCI_PIWBAR: | |
eeae2e7b | 155 | value = pci->pib[idx].piwbar; |
6875dc8e LY |
156 | break; |
157 | case PCI_PIWBEAR: | |
eeae2e7b | 158 | value = pci->pib[idx].piwbear; |
6875dc8e LY |
159 | break; |
160 | case PCI_PIWAR: | |
eeae2e7b | 161 | value = pci->pib[idx].piwar; |
6875dc8e LY |
162 | break; |
163 | default: | |
164 | break; | |
74c62ba8 AJ |
165 | }; |
166 | break; | |
167 | ||
168 | case PPCE500_PCI_GASKET_TIMR: | |
169 | value = pci->gasket_time; | |
170 | break; | |
171 | ||
172 | default: | |
173 | break; | |
174 | } | |
175 | ||
c0a2a096 BS |
176 | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
177 | win, addr, value); | |
74c62ba8 AJ |
178 | return value; |
179 | } | |
180 | ||
a8170e5e | 181 | static void pci_reg_write4(void *opaque, hwaddr addr, |
cd5cba79 | 182 | uint64_t value, unsigned size) |
74c62ba8 AJ |
183 | { |
184 | PPCE500PCIState *pci = opaque; | |
185 | unsigned long win; | |
eeae2e7b | 186 | int idx; |
74c62ba8 AJ |
187 | |
188 | win = addr & 0xfe0; | |
189 | ||
c0a2a096 | 190 | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
cd5cba79 | 191 | __func__, (unsigned)value, win, addr); |
74c62ba8 AJ |
192 | |
193 | switch (win) { | |
194 | case PPCE500_PCI_OW1: | |
195 | case PPCE500_PCI_OW2: | |
196 | case PPCE500_PCI_OW3: | |
197 | case PPCE500_PCI_OW4: | |
eeae2e7b | 198 | idx = (addr >> 5) & 0x7; |
74c62ba8 | 199 | switch (addr & 0xC) { |
6875dc8e | 200 | case PCI_POTAR: |
eeae2e7b | 201 | pci->pob[idx].potar = value; |
6875dc8e LY |
202 | break; |
203 | case PCI_POTEAR: | |
eeae2e7b | 204 | pci->pob[idx].potear = value; |
6875dc8e LY |
205 | break; |
206 | case PCI_POWBAR: | |
eeae2e7b | 207 | pci->pob[idx].powbar = value; |
6875dc8e LY |
208 | break; |
209 | case PCI_POWAR: | |
eeae2e7b | 210 | pci->pob[idx].powar = value; |
6875dc8e LY |
211 | break; |
212 | default: | |
213 | break; | |
74c62ba8 AJ |
214 | }; |
215 | break; | |
216 | ||
217 | case PPCE500_PCI_IW3: | |
218 | case PPCE500_PCI_IW2: | |
219 | case PPCE500_PCI_IW1: | |
eeae2e7b | 220 | idx = ((addr >> 5) & 0x3) - 1; |
74c62ba8 | 221 | switch (addr & 0xC) { |
6875dc8e | 222 | case PCI_PITAR: |
eeae2e7b | 223 | pci->pib[idx].pitar = value; |
6875dc8e LY |
224 | break; |
225 | case PCI_PIWBAR: | |
eeae2e7b | 226 | pci->pib[idx].piwbar = value; |
6875dc8e LY |
227 | break; |
228 | case PCI_PIWBEAR: | |
eeae2e7b | 229 | pci->pib[idx].piwbear = value; |
6875dc8e LY |
230 | break; |
231 | case PCI_PIWAR: | |
eeae2e7b | 232 | pci->pib[idx].piwar = value; |
6875dc8e LY |
233 | break; |
234 | default: | |
235 | break; | |
74c62ba8 AJ |
236 | }; |
237 | break; | |
238 | ||
239 | case PPCE500_PCI_GASKET_TIMR: | |
240 | pci->gasket_time = value; | |
241 | break; | |
242 | ||
243 | default: | |
244 | break; | |
245 | }; | |
246 | } | |
247 | ||
cd5cba79 AK |
248 | static const MemoryRegionOps e500_pci_reg_ops = { |
249 | .read = pci_reg_read4, | |
250 | .write = pci_reg_write4, | |
251 | .endianness = DEVICE_BIG_ENDIAN, | |
74c62ba8 AJ |
252 | }; |
253 | ||
254 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) | |
255 | { | |
256 | int devno = pci_dev->devfn >> 3, ret = 0; | |
257 | ||
258 | switch (devno) { | |
259 | /* Two PCI slot */ | |
260 | case 0x11: | |
261 | case 0x12: | |
262 | ret = (irq_num + devno - 0x10) % 4; | |
263 | break; | |
264 | default: | |
72b310e9 | 265 | printf("Error:%s:unknown dev number\n", __func__); |
74c62ba8 AJ |
266 | } |
267 | ||
268 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, | |
269 | pci_dev->devfn, irq_num, ret, devno); | |
270 | ||
271 | return ret; | |
272 | } | |
273 | ||
5d4e84c8 | 274 | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) |
74c62ba8 | 275 | { |
5d4e84c8 JQ |
276 | qemu_irq *pic = opaque; |
277 | ||
74c62ba8 AJ |
278 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level); |
279 | ||
280 | qemu_set_irq(pic[irq_num], level); | |
281 | } | |
282 | ||
e0433ecc JQ |
283 | static const VMStateDescription vmstate_pci_outbound = { |
284 | .name = "pci_outbound", | |
285 | .version_id = 0, | |
286 | .minimum_version_id = 0, | |
287 | .minimum_version_id_old = 0, | |
288 | .fields = (VMStateField[]) { | |
289 | VMSTATE_UINT32(potar, struct pci_outbound), | |
290 | VMSTATE_UINT32(potear, struct pci_outbound), | |
291 | VMSTATE_UINT32(powbar, struct pci_outbound), | |
292 | VMSTATE_UINT32(powar, struct pci_outbound), | |
293 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 294 | } |
e0433ecc | 295 | }; |
74c62ba8 | 296 | |
e0433ecc JQ |
297 | static const VMStateDescription vmstate_pci_inbound = { |
298 | .name = "pci_inbound", | |
299 | .version_id = 0, | |
300 | .minimum_version_id = 0, | |
301 | .minimum_version_id_old = 0, | |
302 | .fields = (VMStateField[]) { | |
303 | VMSTATE_UINT32(pitar, struct pci_inbound), | |
304 | VMSTATE_UINT32(piwbar, struct pci_inbound), | |
305 | VMSTATE_UINT32(piwbear, struct pci_inbound), | |
306 | VMSTATE_UINT32(piwar, struct pci_inbound), | |
307 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 308 | } |
e0433ecc | 309 | }; |
74c62ba8 | 310 | |
e0433ecc JQ |
311 | static const VMStateDescription vmstate_ppce500_pci = { |
312 | .name = "ppce500_pci", | |
313 | .version_id = 1, | |
314 | .minimum_version_id = 1, | |
315 | .minimum_version_id_old = 1, | |
316 | .fields = (VMStateField[]) { | |
e0433ecc JQ |
317 | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, |
318 | vmstate_pci_outbound, struct pci_outbound), | |
319 | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, | |
320 | vmstate_pci_outbound, struct pci_inbound), | |
321 | VMSTATE_UINT32(gasket_time, PPCE500PCIState), | |
322 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 323 | } |
e0433ecc | 324 | }; |
74c62ba8 | 325 | |
1e39101c AK |
326 | #include "exec-memory.h" |
327 | ||
3eddc1be BB |
328 | static int e500_pcihost_bridge_initfn(PCIDevice *d) |
329 | { | |
330 | PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); | |
331 | PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), | |
332 | "/e500-ccsr")); | |
333 | ||
99750506 AG |
334 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); |
335 | d->config[PCI_HEADER_TYPE] = | |
336 | (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | | |
337 | PCI_HEADER_TYPE_BRIDGE; | |
338 | ||
3eddc1be BB |
339 | memory_region_init_alias(&b->bar0, "e500-pci-bar0", &ccsr->ccsr_space, |
340 | 0, int128_get64(ccsr->ccsr_space.size)); | |
341 | pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); | |
99750506 | 342 | |
3eddc1be BB |
343 | return 0; |
344 | } | |
345 | ||
be13cc7a AG |
346 | static int e500_pcihost_initfn(SysBusDevice *dev) |
347 | { | |
348 | PCIHostState *h; | |
349 | PPCE500PCIState *s; | |
350 | PCIBus *b; | |
351 | int i; | |
aee97b84 | 352 | MemoryRegion *address_space_mem = get_system_memory(); |
be13cc7a | 353 | |
8558d942 | 354 | h = PCI_HOST_BRIDGE(dev); |
9c1a61f0 | 355 | s = PPC_E500_PCI_HOST_BRIDGE(dev); |
be13cc7a AG |
356 | |
357 | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { | |
358 | sysbus_init_irq(dev, &s->irq[i]); | |
359 | } | |
360 | ||
a1bc20df AG |
361 | memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN); |
362 | ||
9c1a61f0 | 363 | b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq, |
aee97b84 | 364 | mpc85xx_pci_map_irq, s->irq, address_space_mem, |
eafb325f | 365 | &s->pio, PCI_DEVFN(s->first_slot, 0), 4); |
9c1a61f0 | 366 | h->bus = b; |
be13cc7a AG |
367 | |
368 | pci_create_simple(b, 0, "e500-host-bridge"); | |
369 | ||
cb4e15c7 | 370 | memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE); |
d0ed8076 AK |
371 | memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h, |
372 | "pci-conf-idx", 4); | |
373 | memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, | |
374 | "pci-conf-data", 4); | |
cd5cba79 AK |
375 | memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s, |
376 | "pci.reg", PCIE500_REG_SIZE); | |
cb4e15c7 BC |
377 | memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); |
378 | memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); | |
379 | memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); | |
380 | sysbus_init_mmio(dev, &s->container); | |
a1bc20df | 381 | sysbus_init_mmio(dev, &s->pio); |
be13cc7a AG |
382 | |
383 | return 0; | |
384 | } | |
385 | ||
40021f08 AL |
386 | static void e500_host_bridge_class_init(ObjectClass *klass, void *data) |
387 | { | |
39bffca2 | 388 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
389 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
390 | ||
3eddc1be | 391 | k->init = e500_pcihost_bridge_initfn; |
40021f08 AL |
392 | k->vendor_id = PCI_VENDOR_ID_FREESCALE; |
393 | k->device_id = PCI_DEVICE_ID_MPC8533E; | |
394 | k->class_id = PCI_CLASS_PROCESSOR_POWERPC; | |
39bffca2 | 395 | dc->desc = "Host bridge"; |
40021f08 AL |
396 | } |
397 | ||
4240abff | 398 | static const TypeInfo e500_host_bridge_info = { |
39bffca2 AL |
399 | .name = "e500-host-bridge", |
400 | .parent = TYPE_PCI_DEVICE, | |
3eddc1be | 401 | .instance_size = sizeof(PPCE500PCIBridgeState), |
39bffca2 | 402 | .class_init = e500_host_bridge_class_init, |
be13cc7a AG |
403 | }; |
404 | ||
eafb325f AG |
405 | static Property pcihost_properties[] = { |
406 | DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), | |
407 | DEFINE_PROP_END_OF_LIST(), | |
408 | }; | |
409 | ||
999e12bb AL |
410 | static void e500_pcihost_class_init(ObjectClass *klass, void *data) |
411 | { | |
39bffca2 | 412 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
413 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
414 | ||
415 | k->init = e500_pcihost_initfn; | |
eafb325f | 416 | dc->props = pcihost_properties; |
39bffca2 | 417 | dc->vmsd = &vmstate_ppce500_pci; |
999e12bb AL |
418 | } |
419 | ||
4240abff | 420 | static const TypeInfo e500_pcihost_info = { |
9c1a61f0 | 421 | .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, |
8558d942 | 422 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
423 | .instance_size = sizeof(PPCE500PCIState), |
424 | .class_init = e500_pcihost_class_init, | |
be13cc7a AG |
425 | }; |
426 | ||
83f7d43a | 427 | static void e500_pci_register_types(void) |
74c62ba8 | 428 | { |
39bffca2 AL |
429 | type_register_static(&e500_pcihost_info); |
430 | type_register_static(&e500_host_bridge_info); | |
74c62ba8 | 431 | } |
83f7d43a AF |
432 | |
433 | type_init(e500_pci_register_types) |