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502a5395 PB |
1 | /* |
2 | * QEMU PREP PCI host | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "pci.h" | |
502a5395 | 27 | #include "pci_host.h" |
18e08a55 | 28 | #include "prep_pci.h" |
502a5395 PB |
29 | |
30 | typedef PCIHostState PREPPCIState; | |
31 | ||
c227f099 | 32 | static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) |
502a5395 PB |
33 | { |
34 | int i; | |
35 | ||
36 | for(i = 0; i < 11; i++) { | |
37 | if ((addr & (1 << (11 + i))) != 0) | |
38 | break; | |
39 | } | |
40 | return (addr & 0x7ff) | (i << 11); | |
41 | } | |
42 | ||
c227f099 | 43 | static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
502a5395 PB |
44 | { |
45 | PREPPCIState *s = opaque; | |
46 | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1); | |
47 | } | |
48 | ||
c227f099 | 49 | static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
502a5395 PB |
50 | { |
51 | PREPPCIState *s = opaque; | |
502a5395 | 52 | val = bswap16(val); |
502a5395 PB |
53 | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2); |
54 | } | |
55 | ||
c227f099 | 56 | static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
502a5395 PB |
57 | { |
58 | PREPPCIState *s = opaque; | |
502a5395 | 59 | val = bswap32(val); |
502a5395 PB |
60 | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4); |
61 | } | |
62 | ||
c227f099 | 63 | static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
64 | { |
65 | PREPPCIState *s = opaque; | |
66 | uint32_t val; | |
67 | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1); | |
68 | return val; | |
69 | } | |
70 | ||
c227f099 | 71 | static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
72 | { |
73 | PREPPCIState *s = opaque; | |
74 | uint32_t val; | |
75 | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2); | |
502a5395 | 76 | val = bswap16(val); |
502a5395 PB |
77 | return val; |
78 | } | |
79 | ||
c227f099 | 80 | static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
81 | { |
82 | PREPPCIState *s = opaque; | |
83 | uint32_t val; | |
84 | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4); | |
502a5395 | 85 | val = bswap32(val); |
502a5395 PB |
86 | return val; |
87 | } | |
88 | ||
d60efc6b | 89 | static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = { |
502a5395 PB |
90 | &PPC_PCIIO_writeb, |
91 | &PPC_PCIIO_writew, | |
92 | &PPC_PCIIO_writel, | |
93 | }; | |
94 | ||
d60efc6b | 95 | static CPUReadMemoryFunc * const PPC_PCIIO_read[] = { |
502a5395 PB |
96 | &PPC_PCIIO_readb, |
97 | &PPC_PCIIO_readw, | |
98 | &PPC_PCIIO_readl, | |
99 | }; | |
100 | ||
d2b59317 | 101 | static int prep_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 102 | { |
80b3ada7 | 103 | return (irq_num + (pci_dev->devfn >> 3)) & 1; |
d2b59317 PB |
104 | } |
105 | ||
5d4e84c8 | 106 | static void prep_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 107 | { |
5d4e84c8 JQ |
108 | qemu_irq *pic = opaque; |
109 | ||
8c9d7f83 | 110 | qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); |
502a5395 PB |
111 | } |
112 | ||
1e39101c | 113 | PCIBus *pci_prep_init(qemu_irq *pic, MemoryRegion *address_space) |
502a5395 PB |
114 | { |
115 | PREPPCIState *s; | |
116 | PCIDevice *d; | |
117 | int PPC_io_memory; | |
118 | ||
119 | s = qemu_mallocz(sizeof(PREPPCIState)); | |
02e2da45 | 120 | s->bus = pci_register_bus(NULL, "pci", |
1e39101c AK |
121 | prep_set_irq, prep_map_irq, pic, |
122 | address_space, 0, 4); | |
502a5395 | 123 | |
f08b32fe | 124 | pci_host_conf_register_ioport(0xcf8, s); |
502a5395 | 125 | |
4f5e19e6 | 126 | pci_host_data_register_ioport(0xcfc, s); |
502a5395 | 127 | |
1eed09cb | 128 | PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read, |
2507c12a AG |
129 | PPC_PCIIO_write, s, |
130 | DEVICE_NATIVE_ENDIAN); | |
502a5395 PB |
131 | cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
132 | ||
5fafdf24 TS |
133 | /* PCI host bridge */ |
134 | d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven", | |
502a5395 | 135 | sizeof(PCIDevice), 0, NULL, NULL); |
deb54399 AL |
136 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); |
137 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN); | |
502a5395 | 138 | d->config[0x08] = 0x00; // revision |
173a543b | 139 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
502a5395 PB |
140 | d->config[0x0C] = 0x08; // cache_line_size |
141 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 PB |
142 | d->config[0x34] = 0x00; // capabilities_pointer |
143 | ||
144 | return s->bus; | |
145 | } |