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502a5395 PB |
1 | /* |
2 | * QEMU PREP PCI host | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "pci.h" | |
502a5395 | 27 | #include "pci_host.h" |
18e08a55 | 28 | #include "prep_pci.h" |
502a5395 PB |
29 | |
30 | typedef PCIHostState PREPPCIState; | |
31 | ||
55526054 AF |
32 | typedef struct RavenPCIState { |
33 | PCIDevice dev; | |
34 | } RavenPCIState; | |
35 | ||
c227f099 | 36 | static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) |
502a5395 PB |
37 | { |
38 | int i; | |
39 | ||
40 | for(i = 0; i < 11; i++) { | |
41 | if ((addr & (1 << (11 + i))) != 0) | |
42 | break; | |
43 | } | |
44 | return (addr & 0x7ff) | (i << 11); | |
45 | } | |
46 | ||
c227f099 | 47 | static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
502a5395 PB |
48 | { |
49 | PREPPCIState *s = opaque; | |
50 | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1); | |
51 | } | |
52 | ||
c227f099 | 53 | static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
502a5395 PB |
54 | { |
55 | PREPPCIState *s = opaque; | |
502a5395 | 56 | val = bswap16(val); |
502a5395 PB |
57 | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2); |
58 | } | |
59 | ||
c227f099 | 60 | static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
502a5395 PB |
61 | { |
62 | PREPPCIState *s = opaque; | |
502a5395 | 63 | val = bswap32(val); |
502a5395 PB |
64 | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4); |
65 | } | |
66 | ||
c227f099 | 67 | static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
68 | { |
69 | PREPPCIState *s = opaque; | |
70 | uint32_t val; | |
71 | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1); | |
72 | return val; | |
73 | } | |
74 | ||
c227f099 | 75 | static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
76 | { |
77 | PREPPCIState *s = opaque; | |
78 | uint32_t val; | |
79 | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2); | |
502a5395 | 80 | val = bswap16(val); |
502a5395 PB |
81 | return val; |
82 | } | |
83 | ||
c227f099 | 84 | static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
85 | { |
86 | PREPPCIState *s = opaque; | |
87 | uint32_t val; | |
88 | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4); | |
502a5395 | 89 | val = bswap32(val); |
502a5395 PB |
90 | return val; |
91 | } | |
92 | ||
f81138ce AK |
93 | static const MemoryRegionOps PPC_PCIIO_ops = { |
94 | .old_mmio = { | |
95 | .read = { PPC_PCIIO_readb, PPC_PCIIO_readw, PPC_PCIIO_readl, }, | |
96 | .write = { PPC_PCIIO_writeb, PPC_PCIIO_writew, PPC_PCIIO_writel, }, | |
97 | }, | |
98 | .endianness = DEVICE_NATIVE_ENDIAN, | |
502a5395 PB |
99 | }; |
100 | ||
d2b59317 | 101 | static int prep_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 102 | { |
80b3ada7 | 103 | return (irq_num + (pci_dev->devfn >> 3)) & 1; |
d2b59317 PB |
104 | } |
105 | ||
5d4e84c8 | 106 | static void prep_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 107 | { |
5d4e84c8 JQ |
108 | qemu_irq *pic = opaque; |
109 | ||
8c9d7f83 | 110 | qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); |
502a5395 PB |
111 | } |
112 | ||
aee97b84 AK |
113 | PCIBus *pci_prep_init(qemu_irq *pic, |
114 | MemoryRegion *address_space_mem, | |
115 | MemoryRegion *address_space_io) | |
502a5395 PB |
116 | { |
117 | PREPPCIState *s; | |
502a5395 | 118 | |
7267c094 | 119 | s = g_malloc0(sizeof(PREPPCIState)); |
02e2da45 | 120 | s->bus = pci_register_bus(NULL, "pci", |
1e39101c | 121 | prep_set_irq, prep_map_irq, pic, |
aee97b84 AK |
122 | address_space_mem, |
123 | address_space_io, | |
124 | 0, 4); | |
502a5395 | 125 | |
d0ed8076 AK |
126 | memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s, |
127 | "pci-conf-idx", 1); | |
128 | memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem); | |
129 | sysbus_init_ioports(&s->busdev, 0xcf8, 1); | |
130 | ||
12da94ff | 131 | memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s, |
d0ed8076 AK |
132 | "pci-conf-data", 1); |
133 | memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem); | |
134 | sysbus_init_ioports(&s->busdev, 0xcfc, 1); | |
502a5395 | 135 | |
f81138ce AK |
136 | memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000); |
137 | memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg); | |
502a5395 | 138 | |
55526054 AF |
139 | pci_create_simple(s->bus, 0, "raven"); |
140 | ||
141 | return s->bus; | |
142 | } | |
143 | ||
144 | static int raven_init(PCIDevice *d) | |
145 | { | |
502a5395 PB |
146 | d->config[0x0C] = 0x08; // cache_line_size |
147 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 PB |
148 | d->config[0x34] = 0x00; // capabilities_pointer |
149 | ||
55526054 | 150 | return 0; |
502a5395 | 151 | } |
55526054 AF |
152 | |
153 | static const VMStateDescription vmstate_raven = { | |
154 | .name = "raven", | |
155 | .version_id = 0, | |
156 | .minimum_version_id = 0, | |
157 | .fields = (VMStateField[]) { | |
158 | VMSTATE_PCI_DEVICE(dev, RavenPCIState), | |
159 | VMSTATE_END_OF_LIST() | |
160 | }, | |
161 | }; | |
162 | ||
163 | static PCIDeviceInfo raven_info = { | |
164 | .qdev.name = "raven", | |
165 | .qdev.desc = "PReP Host Bridge - Motorola Raven", | |
166 | .qdev.size = sizeof(RavenPCIState), | |
167 | .qdev.vmsd = &vmstate_raven, | |
168 | .qdev.no_user = 1, | |
169 | .no_hotplug = 1, | |
170 | .init = raven_init, | |
171 | .vendor_id = PCI_VENDOR_ID_MOTOROLA, | |
172 | .device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN, | |
173 | .revision = 0x00, | |
174 | .class_id = PCI_CLASS_BRIDGE_HOST, | |
175 | .qdev.props = (Property[]) { | |
176 | DEFINE_PROP_END_OF_LIST() | |
177 | }, | |
178 | }; | |
179 | ||
180 | static void raven_register_devices(void) | |
181 | { | |
182 | pci_qdev_register(&raven_info); | |
183 | } | |
184 | ||
185 | device_init(raven_register_devices) |