[mirror_qemu.git] / hw / pxa.h

/*
 * Intel XScale PXA255/270 processor support.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licenced under the GNU GPL v2.
 */
#ifndef PXA_H
# define PXA_H			"pxa.h"

/* Interrupt numbers */
# define PXA2XX_PIC_SSP3	0
# define PXA2XX_PIC_USBH2	2
# define PXA2XX_PIC_USBH1	3
# define PXA2XX_PIC_KEYPAD	4
# define PXA2XX_PIC_PWRI2C	6
# define PXA25X_PIC_HWUART	7
# define PXA27X_PIC_OST_4_11	7
# define PXA2XX_PIC_GPIO_0	8
# define PXA2XX_PIC_GPIO_1	9
# define PXA2XX_PIC_GPIO_X	10
# define PXA2XX_PIC_I2S 	13
# define PXA26X_PIC_ASSP	15
# define PXA25X_PIC_NSSP	16
# define PXA27X_PIC_SSP2	16
# define PXA2XX_PIC_LCD		17
# define PXA2XX_PIC_I2C		18
# define PXA2XX_PIC_ICP		19
# define PXA2XX_PIC_STUART	20
# define PXA2XX_PIC_BTUART	21
# define PXA2XX_PIC_FFUART	22
# define PXA2XX_PIC_MMC		23
# define PXA2XX_PIC_SSP		24
# define PXA2XX_PIC_DMA		25
# define PXA2XX_PIC_OST_0	26
# define PXA2XX_PIC_RTC1HZ	30
# define PXA2XX_PIC_RTCALARM	31

/* DMA requests */
# define PXA2XX_RX_RQ_I2S	2
# define PXA2XX_TX_RQ_I2S	3
# define PXA2XX_RX_RQ_BTUART	4
# define PXA2XX_TX_RQ_BTUART	5
# define PXA2XX_RX_RQ_FFUART	6
# define PXA2XX_TX_RQ_FFUART	7
# define PXA2XX_RX_RQ_SSP1	13
# define PXA2XX_TX_RQ_SSP1	14
# define PXA2XX_RX_RQ_SSP2	15
# define PXA2XX_TX_RQ_SSP2	16
# define PXA2XX_RX_RQ_ICP	17
# define PXA2XX_TX_RQ_ICP	18
# define PXA2XX_RX_RQ_STUART	19
# define PXA2XX_TX_RQ_STUART	20
# define PXA2XX_RX_RQ_MMCI	21
# define PXA2XX_TX_RQ_MMCI	22
# define PXA2XX_USB_RQ(x)	((x) + 24)
# define PXA2XX_RX_RQ_SSP3	66
# define PXA2XX_TX_RQ_SSP3	67

# define PXA2XX_SDRAM_BASE	0xa0000000
# define PXA2XX_INTERNAL_BASE	0x5c000000
# define PXA2XX_INTERNAL_SIZE	0x40000

/* pxa2xx_pic.c */
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);

/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
                CPUState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);

/* pxa2xx_dma.c */
typedef struct PXA2xxDMAState PXA2xxDMAState;
PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
                qemu_irq irq);
PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);

/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);

/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
                BlockDriverState *bd, qemu_irq irq, void *dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                qemu_irq coverswitch);

/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);

/* pxa2xx_keypad.c */
struct  keymap {
    int column;
    int row;
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
                int size);

/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
                qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);

typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;

typedef struct {
    CPUState *env;
    DeviceState *pic;
    qemu_irq reset;
    PXA2xxDMAState *dma;
    DeviceState *gpio;
    PXA2xxLCDState *lcd;
    SSIBus **ssp;
    PXA2xxI2CState *i2c[2];
    PXA2xxMMCIState *mmc;
    PXA2xxPCMCIAState *pcmcia[2];
    PXA2xxI2SState *i2s;
    PXA2xxFIrState *fir;
    PXA2xxKeyPadState *kp;

    /* Power management */
    target_phys_addr_t pm_base;
    uint32_t pm_regs[0x40];

    /* Clock management */
    target_phys_addr_t cm_base;
    uint32_t cm_regs[4];
    uint32_t clkcfg;

    /* Memory management */
    target_phys_addr_t mm_base;
    uint32_t mm_regs[0x1a];

    /* Performance monitoring */
    uint32_t pmnc;

    /* Real-Time clock */
    target_phys_addr_t rtc_base;
    uint32_t rttr;
    uint32_t rtsr;
    uint32_t rtar;
    uint32_t rdar1;
    uint32_t rdar2;
    uint32_t ryar1;
    uint32_t ryar2;
    uint32_t swar1;
    uint32_t swar2;
    uint32_t piar;
    uint32_t last_rcnr;
    uint32_t last_rdcr;
    uint32_t last_rycr;
    uint32_t last_swcr;
    uint32_t last_rtcpicr;
    int64_t last_hz;
    int64_t last_sw;
    int64_t last_pi;
    QEMUTimer *rtc_hz;
    QEMUTimer *rtc_rdal1;
    QEMUTimer *rtc_rdal2;
    QEMUTimer *rtc_swal1;
    QEMUTimer *rtc_swal2;
    QEMUTimer *rtc_pi;
    qemu_irq rtc_irq;
} PXA2xxState;

struct PXA2xxI2SState {
    qemu_irq irq;
    PXA2xxDMAState *dma;
    void (*data_req)(void *, int, int);

    uint32_t control[2];
    uint32_t status;
    uint32_t mask;
    uint32_t clk;

    int enable;
    int rx_len;
    int tx_len;
    void (*codec_out)(void *, uint32_t);
    uint32_t (*codec_in)(void *);
    void *opaque;

    int fifo_len;
    uint32_t fifo[16];
};

# define PA_FMT			"0x%08lx"
# define REG_FMT		"0x" TARGET_FMT_plx

PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
PXA2xxState *pxa255_init(unsigned int sdram_size);

#endif	/* PXA_H */
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 processor support.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
3efda49d	7	* This code is licenced under the GNU GPL v2.
c1713132 AZ	8	*/
	9	#ifndef PXA_H
	10	# define PXA_H "pxa.h"
	11
	12	/* Interrupt numbers */
	13	# define PXA2XX_PIC_SSP3 0
	14	# define PXA2XX_PIC_USBH2 2
	15	# define PXA2XX_PIC_USBH1 3
31b87f2e	16	# define PXA2XX_PIC_KEYPAD 4
c1713132 AZ	17	# define PXA2XX_PIC_PWRI2C 6
	18	# define PXA25X_PIC_HWUART 7
	19	# define PXA27X_PIC_OST_4_11 7
	20	# define PXA2XX_PIC_GPIO_0 8
	21	# define PXA2XX_PIC_GPIO_1 9
	22	# define PXA2XX_PIC_GPIO_X 10
	23	# define PXA2XX_PIC_I2S 13
	24	# define PXA26X_PIC_ASSP 15
	25	# define PXA25X_PIC_NSSP 16
	26	# define PXA27X_PIC_SSP2 16
	27	# define PXA2XX_PIC_LCD 17
	28	# define PXA2XX_PIC_I2C 18
	29	# define PXA2XX_PIC_ICP 19
	30	# define PXA2XX_PIC_STUART 20
	31	# define PXA2XX_PIC_BTUART 21
	32	# define PXA2XX_PIC_FFUART 22
	33	# define PXA2XX_PIC_MMC 23
	34	# define PXA2XX_PIC_SSP 24
	35	# define PXA2XX_PIC_DMA 25
	36	# define PXA2XX_PIC_OST_0 26
	37	# define PXA2XX_PIC_RTC1HZ 30
	38	# define PXA2XX_PIC_RTCALARM 31
	39
	40	/* DMA requests */
	41	# define PXA2XX_RX_RQ_I2S 2
	42	# define PXA2XX_TX_RQ_I2S 3
	43	# define PXA2XX_RX_RQ_BTUART 4
	44	# define PXA2XX_TX_RQ_BTUART 5
	45	# define PXA2XX_RX_RQ_FFUART 6
	46	# define PXA2XX_TX_RQ_FFUART 7
	47	# define PXA2XX_RX_RQ_SSP1 13
	48	# define PXA2XX_TX_RQ_SSP1 14
	49	# define PXA2XX_RX_RQ_SSP2 15
	50	# define PXA2XX_TX_RQ_SSP2 16
	51	# define PXA2XX_RX_RQ_ICP 17
	52	# define PXA2XX_TX_RQ_ICP 18
	53	# define PXA2XX_RX_RQ_STUART 19
	54	# define PXA2XX_TX_RQ_STUART 20
	55	# define PXA2XX_RX_RQ_MMCI 21
	56	# define PXA2XX_TX_RQ_MMCI 22
	57	# define PXA2XX_USB_RQ(x) ((x) + 24)
	58	# define PXA2XX_RX_RQ_SSP3 66
	59	# define PXA2XX_TX_RQ_SSP3 67
	60
d95b2f8d AZ	61	# define PXA2XX_SDRAM_BASE 0xa0000000
d95b2f8d AZ	62	# define PXA2XX_INTERNAL_BASE 0x5c000000
a07dec22	63	# define PXA2XX_INTERNAL_SIZE 0x40000
c1713132 AZ	64
c1713132 AZ	65	/* pxa2xx_pic.c */
e1f8c729	66	DeviceState pxa2xx_pic_init(target_phys_addr_t base, CPUState env);
c1713132 AZ	67
c1713132 AZ	68	/* pxa2xx_gpio.c */
0bb53337	69	DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
e1f8c729	70	CPUState env, DeviceState pic, int lines);
0bb53337	71	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
c1713132 AZ	72
c1713132 AZ	73	/* pxa2xx_dma.c */
bc24a225	74	typedef struct PXA2xxDMAState PXA2xxDMAState;
c227f099	75	PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
c1713132	76	qemu_irq irq);
c227f099	77	PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
c1713132	78	qemu_irq irq);
bc24a225	79	void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
c1713132	80
a171fe39	81	/* pxa2xx_lcd.c */
bc24a225	82	typedef struct PXA2xxLCDState PXA2xxLCDState;
c227f099	83	PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
3023f332	84	qemu_irq irq);
bc24a225	85	void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
a171fe39 AZ	86	void pxa2xx_lcdc_oritentation(void *opaque, int angle);
	87
	88	/* pxa2xx_mmci.c */
bc24a225	89	typedef struct PXA2xxMMCIState PXA2xxMMCIState;
c227f099	90	PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
87ecb68b	91	BlockDriverState bd, qemu_irq irq, void dma);
bc24a225	92	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
02ce600c	93	qemu_irq coverswitch);
a171fe39 AZ	94
a171fe39 AZ	95	/* pxa2xx_pcmcia.c */
bc24a225	96	typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
c227f099	97	PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
bc24a225	98	int pxa2xx_pcmcia_attach(void opaque, PCMCIACardState card);
a171fe39 AZ	99	int pxa2xx_pcmcia_dettach(void *opaque);
	100	void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
	101
31b87f2e AZ	102	/* pxa2xx_keypad.c */
	103	struct keymap {
	104	int column;
	105	int row;
	106	};
bc24a225	107	typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
c227f099	108	PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
31b87f2e	109	qemu_irq irq);
bc24a225	110	void pxa27x_register_keypad(PXA2xxKeyPadState kp, struct keymap map,
31b87f2e AZ	111	int size);
31b87f2e AZ	112
c1713132	113	/* pxa2xx.c */
bc24a225	114	typedef struct PXA2xxI2CState PXA2xxI2CState;
c227f099	115	PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929	116	qemu_irq irq, uint32_t page_size);
bc24a225	117	i2c_bus pxa2xx_i2c_bus(PXA2xxI2CState s);
3f582262	118
bc24a225 PB	119	typedef struct PXA2xxI2SState PXA2xxI2SState;
bc24a225 PB	120	typedef struct PXA2xxFIrState PXA2xxFIrState;
c1713132	121
bc24a225	122	typedef struct {
c1713132	123	CPUState *env;
e1f8c729	124	DeviceState *pic;
38641a52	125	qemu_irq reset;
bc24a225	126	PXA2xxDMAState *dma;
0bb53337	127	DeviceState *gpio;
bc24a225	128	PXA2xxLCDState *lcd;
a984a69e	129	SSIBus **ssp;
bc24a225 PB	130	PXA2xxI2CState *i2c[2];
	131	PXA2xxMMCIState *mmc;
	132	PXA2xxPCMCIAState *pcmcia[2];
	133	PXA2xxI2SState *i2s;
	134	PXA2xxFIrState *fir;
	135	PXA2xxKeyPadState *kp;
c1713132 AZ	136
c1713132 AZ	137	/* Power management */
c227f099	138	target_phys_addr_t pm_base;
c1713132 AZ	139	uint32_t pm_regs[0x40];
	140
	141	/* Clock management */
c227f099	142	target_phys_addr_t cm_base;
c1713132 AZ	143	uint32_t cm_regs[4];
	144	uint32_t clkcfg;
	145
	146	/* Memory management */
c227f099	147	target_phys_addr_t mm_base;
c1713132 AZ	148	uint32_t mm_regs[0x1a];
	149
	150	/* Performance monitoring */
	151	uint32_t pmnc;
	152
	153	/* Real-Time clock */
c227f099	154	target_phys_addr_t rtc_base;
c1713132 AZ	155	uint32_t rttr;
	156	uint32_t rtsr;
	157	uint32_t rtar;
	158	uint32_t rdar1;
	159	uint32_t rdar2;
	160	uint32_t ryar1;
	161	uint32_t ryar2;
	162	uint32_t swar1;
	163	uint32_t swar2;
	164	uint32_t piar;
	165	uint32_t last_rcnr;
	166	uint32_t last_rdcr;
	167	uint32_t last_rycr;
	168	uint32_t last_swcr;
	169	uint32_t last_rtcpicr;
	170	int64_t last_hz;
	171	int64_t last_sw;
	172	int64_t last_pi;
	173	QEMUTimer *rtc_hz;
	174	QEMUTimer *rtc_rdal1;
	175	QEMUTimer *rtc_rdal2;
	176	QEMUTimer *rtc_swal1;
	177	QEMUTimer *rtc_swal2;
	178	QEMUTimer *rtc_pi;
e1f8c729	179	qemu_irq rtc_irq;
bc24a225	180	} PXA2xxState;
c1713132	181
bc24a225	182	struct PXA2xxI2SState {
c1713132	183	qemu_irq irq;
bc24a225	184	PXA2xxDMAState *dma;
c1713132 AZ	185	void (data_req)(void , int, int);
	186
	187	uint32_t control[2];
	188	uint32_t status;
	189	uint32_t mask;
	190	uint32_t clk;
	191
	192	int enable;
	193	int rx_len;
	194	int tx_len;
	195	void (codec_out)(void , uint32_t);
	196	uint32_t (codec_in)(void );
	197	void *opaque;
	198
	199	int fifo_len;
	200	uint32_t fifo[16];
	201	};
	202
	203	# define PA_FMT "0x%08lx"
444ce241	204	# define REG_FMT "0x" TARGET_FMT_plx
c1713132	205
bc24a225 PB	206	PXA2xxState pxa270_init(unsigned int sdram_size, const char revision);
bc24a225 PB	207	PXA2xxState *pxa255_init(unsigned int sdram_size);
c1713132	208
c1713132	209	#endif /* PXA_H */