[mirror_qemu.git] / hw / pxa.h

/*
 * Intel XScale PXA255/270 processor support.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GNU GPL v2.
 */
#ifndef PXA_H
# define PXA_H			"pxa.h"

#include "memory.h"

/* Interrupt numbers */
# define PXA2XX_PIC_SSP3	0
# define PXA2XX_PIC_USBH2	2
# define PXA2XX_PIC_USBH1	3
# define PXA2XX_PIC_KEYPAD	4
# define PXA2XX_PIC_PWRI2C	6
# define PXA25X_PIC_HWUART	7
# define PXA27X_PIC_OST_4_11	7
# define PXA2XX_PIC_GPIO_0	8
# define PXA2XX_PIC_GPIO_1	9
# define PXA2XX_PIC_GPIO_X	10
# define PXA2XX_PIC_I2S 	13
# define PXA26X_PIC_ASSP	15
# define PXA25X_PIC_NSSP	16
# define PXA27X_PIC_SSP2	16
# define PXA2XX_PIC_LCD		17
# define PXA2XX_PIC_I2C		18
# define PXA2XX_PIC_ICP		19
# define PXA2XX_PIC_STUART	20
# define PXA2XX_PIC_BTUART	21
# define PXA2XX_PIC_FFUART	22
# define PXA2XX_PIC_MMC		23
# define PXA2XX_PIC_SSP		24
# define PXA2XX_PIC_DMA		25
# define PXA2XX_PIC_OST_0	26
# define PXA2XX_PIC_RTC1HZ	30
# define PXA2XX_PIC_RTCALARM	31

/* DMA requests */
# define PXA2XX_RX_RQ_I2S	2
# define PXA2XX_TX_RQ_I2S	3
# define PXA2XX_RX_RQ_BTUART	4
# define PXA2XX_TX_RQ_BTUART	5
# define PXA2XX_RX_RQ_FFUART	6
# define PXA2XX_TX_RQ_FFUART	7
# define PXA2XX_RX_RQ_SSP1	13
# define PXA2XX_TX_RQ_SSP1	14
# define PXA2XX_RX_RQ_SSP2	15
# define PXA2XX_TX_RQ_SSP2	16
# define PXA2XX_RX_RQ_ICP	17
# define PXA2XX_TX_RQ_ICP	18
# define PXA2XX_RX_RQ_STUART	19
# define PXA2XX_TX_RQ_STUART	20
# define PXA2XX_RX_RQ_MMCI	21
# define PXA2XX_TX_RQ_MMCI	22
# define PXA2XX_USB_RQ(x)	((x) + 24)
# define PXA2XX_RX_RQ_SSP3	66
# define PXA2XX_TX_RQ_SSP3	67

# define PXA2XX_SDRAM_BASE	0xa0000000
# define PXA2XX_INTERNAL_BASE	0x5c000000
# define PXA2XX_INTERNAL_SIZE	0x40000

/* pxa2xx_pic.c */
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);

/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
                CPUState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);

/* pxa2xx_dma.c */
DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);

/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);

/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
                BlockDriverState *bd, qemu_irq irq,
                qemu_irq rx_dma, qemu_irq tx_dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                qemu_irq coverswitch);

/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);

/* pxa2xx_keypad.c */
struct  keymap {
    int column;
    int row;
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
                int size);

/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
                qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);

typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;

typedef struct {
    CPUState *env;
    DeviceState *pic;
    qemu_irq reset;
    MemoryRegion sdram;
    MemoryRegion internal;
    MemoryRegion cm_iomem;
    MemoryRegion mm_iomem;
    MemoryRegion pm_iomem;
    DeviceState *dma;
    DeviceState *gpio;
    PXA2xxLCDState *lcd;
    SSIBus **ssp;
    PXA2xxI2CState *i2c[2];
    PXA2xxMMCIState *mmc;
    PXA2xxPCMCIAState *pcmcia[2];
    PXA2xxI2SState *i2s;
    PXA2xxFIrState *fir;
    PXA2xxKeyPadState *kp;

    /* Power management */
    target_phys_addr_t pm_base;
    uint32_t pm_regs[0x40];

    /* Clock management */
    target_phys_addr_t cm_base;
    uint32_t cm_regs[4];
    uint32_t clkcfg;

    /* Memory management */
    target_phys_addr_t mm_base;
    uint32_t mm_regs[0x1a];

    /* Performance monitoring */
    uint32_t pmnc;
} PXA2xxState;

struct PXA2xxI2SState {
    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;
    void (*data_req)(void *, int, int);

    uint32_t control[2];
    uint32_t status;
    uint32_t mask;
    uint32_t clk;

    int enable;
    int rx_len;
    int tx_len;
    void (*codec_out)(void *, uint32_t);
    uint32_t (*codec_in)(void *);
    void *opaque;

    int fifo_len;
    uint32_t fifo[16];
};

# define PA_FMT			"0x%08lx"
# define REG_FMT		"0x" TARGET_FMT_plx

PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
                         const char *revision);
PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);

#endif	/* PXA_H */
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 processor support.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
8e31bf38	7	* This code is licensed under the GNU GPL v2.
c1713132 AZ	8	*/
	9	#ifndef PXA_H
	10	# define PXA_H "pxa.h"
	11
a6dc4c2d RH	12	#include "memory.h"
a6dc4c2d RH	13
c1713132 AZ	14	/* Interrupt numbers */
	15	# define PXA2XX_PIC_SSP3 0
	16	# define PXA2XX_PIC_USBH2 2
	17	# define PXA2XX_PIC_USBH1 3
31b87f2e	18	# define PXA2XX_PIC_KEYPAD 4
c1713132 AZ	19	# define PXA2XX_PIC_PWRI2C 6
	20	# define PXA25X_PIC_HWUART 7
	21	# define PXA27X_PIC_OST_4_11 7
	22	# define PXA2XX_PIC_GPIO_0 8
	23	# define PXA2XX_PIC_GPIO_1 9
	24	# define PXA2XX_PIC_GPIO_X 10
	25	# define PXA2XX_PIC_I2S 13
	26	# define PXA26X_PIC_ASSP 15
	27	# define PXA25X_PIC_NSSP 16
	28	# define PXA27X_PIC_SSP2 16
	29	# define PXA2XX_PIC_LCD 17
	30	# define PXA2XX_PIC_I2C 18
	31	# define PXA2XX_PIC_ICP 19
	32	# define PXA2XX_PIC_STUART 20
	33	# define PXA2XX_PIC_BTUART 21
	34	# define PXA2XX_PIC_FFUART 22
	35	# define PXA2XX_PIC_MMC 23
	36	# define PXA2XX_PIC_SSP 24
	37	# define PXA2XX_PIC_DMA 25
	38	# define PXA2XX_PIC_OST_0 26
	39	# define PXA2XX_PIC_RTC1HZ 30
	40	# define PXA2XX_PIC_RTCALARM 31
	41
	42	/* DMA requests */
	43	# define PXA2XX_RX_RQ_I2S 2
	44	# define PXA2XX_TX_RQ_I2S 3
	45	# define PXA2XX_RX_RQ_BTUART 4
	46	# define PXA2XX_TX_RQ_BTUART 5
	47	# define PXA2XX_RX_RQ_FFUART 6
	48	# define PXA2XX_TX_RQ_FFUART 7
	49	# define PXA2XX_RX_RQ_SSP1 13
	50	# define PXA2XX_TX_RQ_SSP1 14
	51	# define PXA2XX_RX_RQ_SSP2 15
	52	# define PXA2XX_TX_RQ_SSP2 16
	53	# define PXA2XX_RX_RQ_ICP 17
	54	# define PXA2XX_TX_RQ_ICP 18
	55	# define PXA2XX_RX_RQ_STUART 19
	56	# define PXA2XX_TX_RQ_STUART 20
	57	# define PXA2XX_RX_RQ_MMCI 21
	58	# define PXA2XX_TX_RQ_MMCI 22
	59	# define PXA2XX_USB_RQ(x) ((x) + 24)
	60	# define PXA2XX_RX_RQ_SSP3 66
	61	# define PXA2XX_TX_RQ_SSP3 67
	62
d95b2f8d AZ	63	# define PXA2XX_SDRAM_BASE 0xa0000000
d95b2f8d AZ	64	# define PXA2XX_INTERNAL_BASE 0x5c000000
a07dec22	65	# define PXA2XX_INTERNAL_SIZE 0x40000
c1713132 AZ	66
c1713132 AZ	67	/* pxa2xx_pic.c */
e1f8c729	68	DeviceState pxa2xx_pic_init(target_phys_addr_t base, CPUState env);
c1713132 AZ	69
c1713132 AZ	70	/* pxa2xx_gpio.c */
0bb53337	71	DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
e1f8c729	72	CPUState env, DeviceState pic, int lines);
0bb53337	73	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
c1713132 AZ	74
c1713132 AZ	75	/* pxa2xx_dma.c */
2115c019 AZ	76	DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
2115c019 AZ	77	DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
c1713132	78
a171fe39	79	/* pxa2xx_lcd.c */
bc24a225	80	typedef struct PXA2xxLCDState PXA2xxLCDState;
c227f099	81	PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
3023f332	82	qemu_irq irq);
bc24a225	83	void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
a171fe39 AZ	84	void pxa2xx_lcdc_oritentation(void *opaque, int angle);
	85
	86	/* pxa2xx_mmci.c */
bc24a225	87	typedef struct PXA2xxMMCIState PXA2xxMMCIState;
c227f099	88	PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
2115c019 AZ	89	BlockDriverState *bd, qemu_irq irq,
2115c019 AZ	90	qemu_irq rx_dma, qemu_irq tx_dma);
bc24a225	91	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
02ce600c	92	qemu_irq coverswitch);
a171fe39 AZ	93
a171fe39 AZ	94	/* pxa2xx_pcmcia.c */
bc24a225	95	typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
c227f099	96	PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
bc24a225	97	int pxa2xx_pcmcia_attach(void opaque, PCMCIACardState card);
a171fe39 AZ	98	int pxa2xx_pcmcia_dettach(void *opaque);
	99	void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
	100
31b87f2e AZ	101	/* pxa2xx_keypad.c */
	102	struct keymap {
	103	int column;
	104	int row;
	105	};
bc24a225	106	typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
c227f099	107	PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
31b87f2e	108	qemu_irq irq);
bc24a225	109	void pxa27x_register_keypad(PXA2xxKeyPadState kp, struct keymap map,
31b87f2e AZ	110	int size);
31b87f2e AZ	111
c1713132	112	/* pxa2xx.c */
bc24a225	113	typedef struct PXA2xxI2CState PXA2xxI2CState;
c227f099	114	PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929	115	qemu_irq irq, uint32_t page_size);
bc24a225	116	i2c_bus pxa2xx_i2c_bus(PXA2xxI2CState s);
3f582262	117
bc24a225 PB	118	typedef struct PXA2xxI2SState PXA2xxI2SState;
bc24a225 PB	119	typedef struct PXA2xxFIrState PXA2xxFIrState;
c1713132	120
bc24a225	121	typedef struct {
c1713132	122	CPUState *env;
e1f8c729	123	DeviceState *pic;
38641a52	124	qemu_irq reset;
adfc39ea AK	125	MemoryRegion sdram;
	126	MemoryRegion internal;
	127	MemoryRegion cm_iomem;
	128	MemoryRegion mm_iomem;
	129	MemoryRegion pm_iomem;
2115c019	130	DeviceState *dma;
0bb53337	131	DeviceState *gpio;
bc24a225	132	PXA2xxLCDState *lcd;
a984a69e	133	SSIBus **ssp;
bc24a225 PB	134	PXA2xxI2CState *i2c[2];
	135	PXA2xxMMCIState *mmc;
	136	PXA2xxPCMCIAState *pcmcia[2];
	137	PXA2xxI2SState *i2s;
	138	PXA2xxFIrState *fir;
	139	PXA2xxKeyPadState *kp;
c1713132 AZ	140
c1713132 AZ	141	/* Power management */
c227f099	142	target_phys_addr_t pm_base;
c1713132 AZ	143	uint32_t pm_regs[0x40];
	144
	145	/* Clock management */
c227f099	146	target_phys_addr_t cm_base;
c1713132 AZ	147	uint32_t cm_regs[4];
	148	uint32_t clkcfg;
	149
	150	/* Memory management */
c227f099	151	target_phys_addr_t mm_base;
c1713132 AZ	152	uint32_t mm_regs[0x1a];
	153
	154	/* Performance monitoring */
	155	uint32_t pmnc;
bc24a225	156	} PXA2xxState;
c1713132	157
bc24a225	158	struct PXA2xxI2SState {
9c843933	159	MemoryRegion iomem;
c1713132	160	qemu_irq irq;
2115c019 AZ	161	qemu_irq rx_dma;
2115c019 AZ	162	qemu_irq tx_dma;
c1713132 AZ	163	void (data_req)(void , int, int);
	164
	165	uint32_t control[2];
	166	uint32_t status;
	167	uint32_t mask;
	168	uint32_t clk;
	169
	170	int enable;
	171	int rx_len;
	172	int tx_len;
	173	void (codec_out)(void , uint32_t);
	174	uint32_t (codec_in)(void );
	175	void *opaque;
	176
	177	int fifo_len;
	178	uint32_t fifo[16];
	179	};
	180
	181	# define PA_FMT "0x%08lx"
444ce241	182	# define REG_FMT "0x" TARGET_FMT_plx
c1713132	183
a6dc4c2d RH	184	PXA2xxState pxa270_init(MemoryRegion address_space, unsigned int sdram_size,
	185	const char *revision);
	186	PXA2xxState pxa255_init(MemoryRegion address_space, unsigned int sdram_size);
c1713132	187
c1713132	188	#endif /* PXA_H */