]> git.proxmox.com Git - mirror_qemu.git/blame - hw/pxa2xx.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Move CPU save/load registration to common code.
[mirror_qemu.git] / hw / pxa2xx.c
CommitLineData
c1713132
AZ		 1/*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "pxa.h"
12#include "sysemu.h"
13#include "pc.h"
14#include "i2c.h"
15#include "qemu-timer.h"
16#include "qemu-char.h"
c1713132
AZ		 17
18static struct {
19 target_phys_addr_t io_base;
20 int irqn;
21} pxa255_serial[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART },
23 { 0x40200000, PXA2XX_PIC_BTUART },
24 { 0x40700000, PXA2XX_PIC_STUART },
25 { 0x41600000, PXA25X_PIC_HWUART },
26 { 0, 0 }
27}, pxa270_serial[] = {
28 { 0x40100000, PXA2XX_PIC_FFUART },
29 { 0x40200000, PXA2XX_PIC_BTUART },
30 { 0x40700000, PXA2XX_PIC_STUART },
31 { 0, 0 }
32};
33
fa58c156 34typedef struct PXASSPDef {
c1713132
AZ		 35 target_phys_addr_t io_base;
36 int irqn;
fa58c156
FB		 37} PXASSPDef;
38
39#if 0
40static PXASSPDef pxa250_ssp[] = {
c1713132
AZ		 41 { 0x41000000, PXA2XX_PIC_SSP },
42 { 0, 0 }
fa58c156
FB		 43};
44#endif
45
46static PXASSPDef pxa255_ssp[] = {
c1713132
AZ		 47 { 0x41000000, PXA2XX_PIC_SSP },
48 { 0x41400000, PXA25X_PIC_NSSP },
49 { 0, 0 }
fa58c156
FB		 50};
51
52#if 0
53static PXASSPDef pxa26x_ssp[] = {
c1713132
AZ		 54 { 0x41000000, PXA2XX_PIC_SSP },
55 { 0x41400000, PXA25X_PIC_NSSP },
56 { 0x41500000, PXA26X_PIC_ASSP },
57 { 0, 0 }
fa58c156
FB		 58};
59#endif
60
61static PXASSPDef pxa27x_ssp[] = {
c1713132
AZ		 62 { 0x41000000, PXA2XX_PIC_SSP },
63 { 0x41700000, PXA27X_PIC_SSP2 },
64 { 0x41900000, PXA2XX_PIC_SSP3 },
65 { 0, 0 }
66};
67
68#define PMCR 0x00 /* Power Manager Control register */
69#define PSSR 0x04 /* Power Manager Sleep Status register */
70#define PSPR 0x08 /* Power Manager Scratch-Pad register */
71#define PWER 0x0c /* Power Manager Wake-Up Enable register */
72#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
73#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
74#define PEDR 0x18 /* Power Manager Edge-Detect Status register */
75#define PCFR 0x1c /* Power Manager General Configuration register */
76#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
77#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
78#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
79#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
80#define RCSR 0x30 /* Reset Controller Status register */
81#define PSLR 0x34 /* Power Manager Sleep Configuration register */
82#define PTSR 0x38 /* Power Manager Standby Configuration register */
83#define PVCR 0x40 /* Power Manager Voltage Change Control register */
84#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
85#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
86#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
87#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
88#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
89
90static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
91{
92 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
93 addr -= s->pm_base;
94
95 switch (addr) {
96 case PMCR ... PCMD31:
97 if (addr & 3)
98 goto fail;
99
100 return s->pm_regs[addr >> 2];
101 default:
102 fail:
103 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
104 break;
105 }
106 return 0;
107}
108
109static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
110 uint32_t value)
111{
112 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
113 addr -= s->pm_base;
114
115 switch (addr) {
116 case PMCR:
117 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
118 s->pm_regs[addr >> 2] |= value & 0x15;
119 break;
120
121 case PSSR: /* Read-clean registers */
122 case RCSR:
123 case PKSR:
124 s->pm_regs[addr >> 2] &= ~value;
125 break;
126
127 default: /* Read-write registers */
128 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
129 s->pm_regs[addr >> 2] = value;
130 break;
131 }
132
133 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
134 break;
135 }
136}
137
138static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
139 pxa2xx_pm_read,
140 pxa2xx_pm_read,
141 pxa2xx_pm_read,
142};
143
144static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
145 pxa2xx_pm_write,
146 pxa2xx_pm_write,
147 pxa2xx_pm_write,
148};
149
aa941b94
AZ		 150static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
151{
152 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
153 int i;
154
155 for (i = 0; i < 0x40; i ++)
156 qemu_put_be32s(f, &s->pm_regs[i]);
157}
158
159static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
160{
161 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
162 int i;
163
164 for (i = 0; i < 0x40; i ++)
165 qemu_get_be32s(f, &s->pm_regs[i]);
166
167 return 0;
168}
169
c1713132
AZ		 170#define CCCR 0x00 /* Core Clock Configuration register */
171#define CKEN 0x04 /* Clock Enable register */
172#define OSCC 0x08 /* Oscillator Configuration register */
173#define CCSR 0x0c /* Core Clock Status register */
174
175static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
176{
177 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
178 addr -= s->cm_base;
179
180 switch (addr) {
181 case CCCR:
182 case CKEN:
183 case OSCC:
184 return s->cm_regs[addr >> 2];
185
186 case CCSR:
187 return s->cm_regs[CCCR >> 2] | (3 << 28);
188
189 default:
190 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
191 break;
192 }
193 return 0;
194}
195
196static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
197 uint32_t value)
198{
199 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
200 addr -= s->cm_base;
201
202 switch (addr) {
203 case CCCR:
204 case CKEN:
205 s->cm_regs[addr >> 2] = value;
206 break;
207
208 case OSCC:
565d2895 209 s->cm_regs[addr >> 2] &= ~0x6c;
c1713132 210 s->cm_regs[addr >> 2] |= value & 0x6e;
565d2895
AZ		 211 if ((value >> 1) & 1) /* OON */
212 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
c1713132
AZ		 213 break;
214
215 default:
216 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
217 break;
218 }
219}
220
221static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
222 pxa2xx_cm_read,
223 pxa2xx_cm_read,
224 pxa2xx_cm_read,
225};
226
227static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
228 pxa2xx_cm_write,
229 pxa2xx_cm_write,
230 pxa2xx_cm_write,
231};
232
aa941b94
AZ		 233static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
234{
235 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
236 int i;
237
238 for (i = 0; i < 4; i ++)
239 qemu_put_be32s(f, &s->cm_regs[i]);
240 qemu_put_be32s(f, &s->clkcfg);
241 qemu_put_be32s(f, &s->pmnc);
242}
243
244static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
245{
246 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
247 int i;
248
249 for (i = 0; i < 4; i ++)
250 qemu_get_be32s(f, &s->cm_regs[i]);
251 qemu_get_be32s(f, &s->clkcfg);
252 qemu_get_be32s(f, &s->pmnc);
253
254 return 0;
255}
256
c1713132
AZ		 257static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
258{
259 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
260
261 switch (reg) {
262 case 6: /* Clock Configuration register */
263 return s->clkcfg;
264
265 case 7: /* Power Mode register */
266 return 0;
267
268 default:
269 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
270 break;
271 }
272 return 0;
273}
274
275static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
276 uint32_t value)
277{
278 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
279 static const char *pwrmode[8] = {
280 "Normal", "Idle", "Deep-idle", "Standby",
281 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
282 };
283
284 switch (reg) {
285 case 6: /* Clock Configuration register */
286 s->clkcfg = value & 0xf;
287 if (value & 2)
288 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
289 break;
290
291 case 7: /* Power Mode register */
292 if (value & 8)
293 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
294 switch (value & 7) {
295 case 0:
296 /* Do nothing */
297 break;
298
299 case 1:
300 /* Idle */
82d17978 301 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
c1713132
AZ		 302 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
303 break;
304 }
305 /* Fall through. */
306
307 case 2:
308 /* Deep-Idle */
309 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
310 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
311 goto message;
312
313 case 3:
a90b7318
AZ		 314 s->env->uncached_cpsr =
315 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
c1713132
AZ		 316 s->env->cp15.c1_sys = 0;
317 s->env->cp15.c1_coproc = 0;
9ee6e8bb 318 s->env->cp15.c2_base0 = 0;
c1713132
AZ		 319 s->env->cp15.c3 = 0;
320 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
321 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
322
323 /*
324 * The scratch-pad register is almost universally used
325 * for storing the return address on suspend. For the
326 * lack of a resuming bootloader, perform a jump
327 * directly to that address.
328 */
329 memset(s->env->regs, 0, 4 * 15);
330 s->env->regs[15] = s->pm_regs[PSPR >> 2];
331
332#if 0
333 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
334 cpu_physical_memory_write(0, &buffer, 4);
335 buffer = s->pm_regs[PSPR >> 2];
336 cpu_physical_memory_write(8, &buffer, 4);
337#endif
338
339 /* Suspend */
340 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
341
342 goto message;
343
344 default:
345 message:
346 printf("%s: machine entered %s mode\n", __FUNCTION__,
347 pwrmode[value & 7]);
348 }
349 break;
350
351 default:
352 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
353 break;
354 }
355}
356
357/* Performace Monitoring Registers */
358#define CPPMNC 0 /* Performance Monitor Control register */
359#define CPCCNT 1 /* Clock Counter register */
360#define CPINTEN 4 /* Interrupt Enable register */
361#define CPFLAG 5 /* Overflow Flag register */
362#define CPEVTSEL 8 /* Event Selection register */
363
364#define CPPMN0 0 /* Performance Count register 0 */
365#define CPPMN1 1 /* Performance Count register 1 */
366#define CPPMN2 2 /* Performance Count register 2 */
367#define CPPMN3 3 /* Performance Count register 3 */
368
369static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
370{
371 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
372
373 switch (reg) {
374 case CPPMNC:
375 return s->pmnc;
376 case CPCCNT:
377 if (s->pmnc & 1)
378 return qemu_get_clock(vm_clock);
379 else
380 return 0;
381 case CPINTEN:
382 case CPFLAG:
383 case CPEVTSEL:
384 return 0;
385
386 default:
387 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
388 break;
389 }
390 return 0;
391}
392
393static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
394 uint32_t value)
395{
396 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
397
398 switch (reg) {
399 case CPPMNC:
400 s->pmnc = value;
401 break;
402
403 case CPCCNT:
404 case CPINTEN:
405 case CPFLAG:
406 case CPEVTSEL:
407 break;
408
409 default:
410 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
411 break;
412 }
413}
414
415static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
416{
417 switch (crm) {
418 case 0:
419 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
420 case 1:
421 return pxa2xx_perf_read(opaque, op2, reg, crm);
422 case 2:
423 switch (reg) {
424 case CPPMN0:
425 case CPPMN1:
426 case CPPMN2:
427 case CPPMN3:
428 return 0;
429 }
430 /* Fall through */
431 default:
432 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
433 break;
434 }
435 return 0;
436}
437
438static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
439 uint32_t value)
440{
441 switch (crm) {
442 case 0:
443 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
444 break;
445 case 1:
446 pxa2xx_perf_write(opaque, op2, reg, crm, value);
447 break;
448 case 2:
449 switch (reg) {
450 case CPPMN0:
451 case CPPMN1:
452 case CPPMN2:
453 case CPPMN3:
454 return;
455 }
456 /* Fall through */
457 default:
458 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
459 break;
460 }
461}
462
463#define MDCNFG 0x00 /* SDRAM Configuration register */
464#define MDREFR 0x04 /* SDRAM Refresh Control register */
465#define MSC0 0x08 /* Static Memory Control register 0 */
466#define MSC1 0x0c /* Static Memory Control register 1 */
467#define MSC2 0x10 /* Static Memory Control register 2 */
468#define MECR 0x14 /* Expansion Memory Bus Config register */
469#define SXCNFG 0x1c /* Synchronous Static Memory Config register */
470#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
471#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
472#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
473#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
474#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
475#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
476#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
477#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
478#define ARB_CNTL 0x48 /* Arbiter Control register */
479#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
480#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
481#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
482#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
483#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
484#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
485#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
486
487static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
488{
489 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
490 addr -= s->mm_base;
491
492 switch (addr) {
493 case MDCNFG ... SA1110:
494 if ((addr & 3) == 0)
495 return s->mm_regs[addr >> 2];
496
497 default:
498 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
499 break;
500 }
501 return 0;
502}
503
504static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
505 uint32_t value)
506{
507 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
508 addr -= s->mm_base;
509
510 switch (addr) {
511 case MDCNFG ... SA1110:
512 if ((addr & 3) == 0) {
513 s->mm_regs[addr >> 2] = value;
514 break;
515 }
516
517 default:
518 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
519 break;
520 }
521}
522
523static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
524 pxa2xx_mm_read,
525 pxa2xx_mm_read,
526 pxa2xx_mm_read,
527};
528
529static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
530 pxa2xx_mm_write,
531 pxa2xx_mm_write,
532 pxa2xx_mm_write,
533};
534
aa941b94
AZ		 535static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
536{
537 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
538 int i;
539
540 for (i = 0; i < 0x1a; i ++)
541 qemu_put_be32s(f, &s->mm_regs[i]);
542}
543
544static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
545{
546 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
547 int i;
548
549 for (i = 0; i < 0x1a; i ++)
550 qemu_get_be32s(f, &s->mm_regs[i]);
551
552 return 0;
553}
554
c1713132
AZ		 555/* Synchronous Serial Ports */
556struct pxa2xx_ssp_s {
557 target_phys_addr_t base;
558 qemu_irq irq;
559 int enable;
560
561 uint32_t sscr[2];
562 uint32_t sspsp;
563 uint32_t ssto;
564 uint32_t ssitr;
565 uint32_t sssr;
566 uint8_t sstsa;
567 uint8_t ssrsa;
568 uint8_t ssacd;
569
570 uint32_t rx_fifo[16];
571 int rx_level;
572 int rx_start;
573
574 uint32_t (*readfn)(void *opaque);
575 void (*writefn)(void *opaque, uint32_t value);
576 void *opaque;
577};
578
579#define SSCR0 0x00 /* SSP Control register 0 */
580#define SSCR1 0x04 /* SSP Control register 1 */
581#define SSSR 0x08 /* SSP Status register */
582#define SSITR 0x0c /* SSP Interrupt Test register */
583#define SSDR 0x10 /* SSP Data register */
584#define SSTO 0x28 /* SSP Time-Out register */
585#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
586#define SSTSA 0x30 /* SSP TX Time Slot Active register */
587#define SSRSA 0x34 /* SSP RX Time Slot Active register */
588#define SSTSS 0x38 /* SSP Time Slot Status register */
589#define SSACD 0x3c /* SSP Audio Clock Divider register */
590
591/* Bitfields for above registers */
592#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
593#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
594#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
595#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
596#define SSCR0_SSE (1 << 7)
597#define SSCR0_RIM (1 << 22)
598#define SSCR0_TIM (1 << 23)
599#define SSCR0_MOD (1 << 31)
600#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
601#define SSCR1_RIE (1 << 0)
602#define SSCR1_TIE (1 << 1)
603#define SSCR1_LBM (1 << 2)
604#define SSCR1_MWDS (1 << 5)
605#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
606#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
607#define SSCR1_EFWR (1 << 14)
608#define SSCR1_PINTE (1 << 18)
609#define SSCR1_TINTE (1 << 19)
610#define SSCR1_RSRE (1 << 20)
611#define SSCR1_TSRE (1 << 21)
612#define SSCR1_EBCEI (1 << 29)
613#define SSITR_INT (7 << 5)
614#define SSSR_TNF (1 << 2)
615#define SSSR_RNE (1 << 3)
616#define SSSR_TFS (1 << 5)
617#define SSSR_RFS (1 << 6)
618#define SSSR_ROR (1 << 7)
619#define SSSR_PINT (1 << 18)
620#define SSSR_TINT (1 << 19)
621#define SSSR_EOC (1 << 20)
622#define SSSR_TUR (1 << 21)
623#define SSSR_BCE (1 << 23)
624#define SSSR_RW 0x00bc0080
625
626static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
627{
628 int level = 0;
629
630 level |= s->ssitr & SSITR_INT;
631 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
632 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
633 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
634 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
635 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
636 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
637 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
638 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
639 qemu_set_irq(s->irq, !!level);
640}
641
642static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
643{
644 s->sssr &= ~(0xf << 12); /* Clear RFL */
645 s->sssr &= ~(0xf << 8); /* Clear TFL */
646 s->sssr &= ~SSSR_TNF;
647 if (s->enable) {
648 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
649 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
650 s->sssr |= SSSR_RFS;
651 else
652 s->sssr &= ~SSSR_RFS;
653 if (0 <= SSCR1_TFT(s->sscr[1]))
654 s->sssr |= SSSR_TFS;
655 else
656 s->sssr &= ~SSSR_TFS;
657 if (s->rx_level)
658 s->sssr |= SSSR_RNE;
659 else
660 s->sssr &= ~SSSR_RNE;
661 s->sssr |= SSSR_TNF;
662 }
663
664 pxa2xx_ssp_int_update(s);
665}
666
667static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
668{
669 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
670 uint32_t retval;
671 addr -= s->base;
672
673 switch (addr) {
674 case SSCR0:
675 return s->sscr[0];
676 case SSCR1:
677 return s->sscr[1];
678 case SSPSP:
679 return s->sspsp;
680 case SSTO:
681 return s->ssto;
682 case SSITR:
683 return s->ssitr;
684 case SSSR:
685 return s->sssr | s->ssitr;
686 case SSDR:
687 if (!s->enable)
688 return 0xffffffff;
689 if (s->rx_level < 1) {
690 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
691 return 0xffffffff;
692 }
693 s->rx_level --;
694 retval = s->rx_fifo[s->rx_start ++];
695 s->rx_start &= 0xf;
696 pxa2xx_ssp_fifo_update(s);
697 return retval;
698 case SSTSA:
699 return s->sstsa;
700 case SSRSA:
701 return s->ssrsa;
702 case SSTSS:
703 return 0;
704 case SSACD:
705 return s->ssacd;
706 default:
707 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
708 break;
709 }
710 return 0;
711}
712
713static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
714 uint32_t value)
715{
716 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
717 addr -= s->base;
718
719 switch (addr) {
720 case SSCR0:
721 s->sscr[0] = value & 0xc7ffffff;
722 s->enable = value & SSCR0_SSE;
723 if (value & SSCR0_MOD)
724 printf("%s: Attempt to use network mode\n", __FUNCTION__);
725 if (s->enable && SSCR0_DSS(value) < 4)
726 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
727 SSCR0_DSS(value));
728 if (!(value & SSCR0_SSE)) {
729 s->sssr = 0;
730 s->ssitr = 0;
731 s->rx_level = 0;
732 }
733 pxa2xx_ssp_fifo_update(s);
734 break;
735
736 case SSCR1:
737 s->sscr[1] = value;
738 if (value & (SSCR1_LBM | SSCR1_EFWR))
739 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
740 pxa2xx_ssp_fifo_update(s);
741 break;
742
743 case SSPSP:
744 s->sspsp = value;
745 break;
746
747 case SSTO:
748 s->ssto = value;
749 break;
750
751 case SSITR:
752 s->ssitr = value & SSITR_INT;
753 pxa2xx_ssp_int_update(s);
754 break;
755
756 case SSSR:
757 s->sssr &= ~(value & SSSR_RW);
758 pxa2xx_ssp_int_update(s);
759 break;
760
761 case SSDR:
762 if (SSCR0_UWIRE(s->sscr[0])) {
763 if (s->sscr[1] & SSCR1_MWDS)
764 value &= 0xffff;
765 else
766 value &= 0xff;
767 } else
768 /* Note how 32bits overflow does no harm here */
769 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
770
771 /* Data goes from here to the Tx FIFO and is shifted out from
772 * there directly to the slave, no need to buffer it.
773 */
774 if (s->enable) {
775 if (s->writefn)
776 s->writefn(s->opaque, value);
777
778 if (s->rx_level < 0x10) {
779 if (s->readfn)
780 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
781 s->readfn(s->opaque);
782 else
783 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
784 } else
785 s->sssr |= SSSR_ROR;
786 }
787 pxa2xx_ssp_fifo_update(s);
788 break;
789
790 case SSTSA:
791 s->sstsa = value;
792 break;
793
794 case SSRSA:
795 s->ssrsa = value;
796 break;
797
798 case SSACD:
799 s->ssacd = value;
800 break;
801
802 default:
803 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
804 break;
805 }
806}
807
808void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
809 uint32_t (*readfn)(void *opaque),
810 void (*writefn)(void *opaque, uint32_t value), void *opaque)
811{
812 if (!port) {
813 printf("%s: no such SSP\n", __FUNCTION__);
814 exit(-1);
815 }
816
817 port->opaque = opaque;
818 port->readfn = readfn;
819 port->writefn = writefn;
820}
821
822static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
823 pxa2xx_ssp_read,
824 pxa2xx_ssp_read,
825 pxa2xx_ssp_read,
826};
827
828static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
829 pxa2xx_ssp_write,
830 pxa2xx_ssp_write,
831 pxa2xx_ssp_write,
832};
833
aa941b94
AZ		 834static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
835{
836 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
837 int i;
838
839 qemu_put_be32(f, s->enable);
840
841 qemu_put_be32s(f, &s->sscr[0]);
842 qemu_put_be32s(f, &s->sscr[1]);
843 qemu_put_be32s(f, &s->sspsp);
844 qemu_put_be32s(f, &s->ssto);
845 qemu_put_be32s(f, &s->ssitr);
846 qemu_put_be32s(f, &s->sssr);
847 qemu_put_8s(f, &s->sstsa);
848 qemu_put_8s(f, &s->ssrsa);
849 qemu_put_8s(f, &s->ssacd);
850
851 qemu_put_byte(f, s->rx_level);
852 for (i = 0; i < s->rx_level; i ++)
853 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
854}
855
856static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
857{
858 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
859 int i;
860
861 s->enable = qemu_get_be32(f);
862
863 qemu_get_be32s(f, &s->sscr[0]);
864 qemu_get_be32s(f, &s->sscr[1]);
865 qemu_get_be32s(f, &s->sspsp);
866 qemu_get_be32s(f, &s->ssto);
867 qemu_get_be32s(f, &s->ssitr);
868 qemu_get_be32s(f, &s->sssr);
869 qemu_get_8s(f, &s->sstsa);
870 qemu_get_8s(f, &s->ssrsa);
871 qemu_get_8s(f, &s->ssacd);
872
873 s->rx_level = qemu_get_byte(f);
874 s->rx_start = 0;
875 for (i = 0; i < s->rx_level; i ++)
876 s->rx_fifo[i] = qemu_get_byte(f);
877
878 return 0;
879}
880
c1713132
AZ		 881/* Real-Time Clock */
882#define RCNR 0x00 /* RTC Counter register */
883#define RTAR 0x04 /* RTC Alarm register */
884#define RTSR 0x08 /* RTC Status register */
885#define RTTR 0x0c /* RTC Timer Trim register */
886#define RDCR 0x10 /* RTC Day Counter register */
887#define RYCR 0x14 /* RTC Year Counter register */
888#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
889#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
890#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
891#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
892#define SWCR 0x28 /* RTC Stopwatch Counter register */
893#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
894#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
895#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
896#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
897
898static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
899{
900 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
901}
902
903static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
904{
905 int64_t rt = qemu_get_clock(rt_clock);
906 s->last_rcnr += ((rt - s->last_hz) << 15) /
907 (1000 * ((s->rttr & 0xffff) + 1));
908 s->last_rdcr += ((rt - s->last_hz) << 15) /
909 (1000 * ((s->rttr & 0xffff) + 1));
910 s->last_hz = rt;
911}
912
913static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
914{
915 int64_t rt = qemu_get_clock(rt_clock);
916 if (s->rtsr & (1 << 12))
917 s->last_swcr += (rt - s->last_sw) / 10;
918 s->last_sw = rt;
919}
920
921static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
922{
923 int64_t rt = qemu_get_clock(rt_clock);
924 if (s->rtsr & (1 << 15))
925 s->last_swcr += rt - s->last_pi;
926 s->last_pi = rt;
927}
928
929static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
930 uint32_t rtsr)
931{
932 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
933 qemu_mod_timer(s->rtc_hz, s->last_hz +
934 (((s->rtar - s->last_rcnr) * 1000 *
935 ((s->rttr & 0xffff) + 1)) >> 15));
936 else
937 qemu_del_timer(s->rtc_hz);
938
939 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
940 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
941 (((s->rdar1 - s->last_rdcr) * 1000 *
942 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
943 else
944 qemu_del_timer(s->rtc_rdal1);
945
946 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
947 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
948 (((s->rdar2 - s->last_rdcr) * 1000 *
949 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
950 else
951 qemu_del_timer(s->rtc_rdal2);
952
953 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
954 qemu_mod_timer(s->rtc_swal1, s->last_sw +
955 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
956 else
957 qemu_del_timer(s->rtc_swal1);
958
959 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
960 qemu_mod_timer(s->rtc_swal2, s->last_sw +
961 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
962 else
963 qemu_del_timer(s->rtc_swal2);
964
965 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
966 qemu_mod_timer(s->rtc_pi, s->last_pi +
967 (s->piar & 0xffff) - s->last_rtcpicr);
968 else
969 qemu_del_timer(s->rtc_pi);
970}
971
972static inline void pxa2xx_rtc_hz_tick(void *opaque)
973{
974 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
975 s->rtsr |= (1 << 0);
976 pxa2xx_rtc_alarm_update(s, s->rtsr);
977 pxa2xx_rtc_int_update(s);
978}
979
980static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
981{
982 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
983 s->rtsr |= (1 << 4);
984 pxa2xx_rtc_alarm_update(s, s->rtsr);
985 pxa2xx_rtc_int_update(s);
986}
987
988static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
989{
990 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
991 s->rtsr |= (1 << 6);
992 pxa2xx_rtc_alarm_update(s, s->rtsr);
993 pxa2xx_rtc_int_update(s);
994}
995
996static inline void pxa2xx_rtc_swal1_tick(void *opaque)
997{
998 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
999 s->rtsr |= (1 << 8);
1000 pxa2xx_rtc_alarm_update(s, s->rtsr);
1001 pxa2xx_rtc_int_update(s);
1002}
1003
1004static inline void pxa2xx_rtc_swal2_tick(void *opaque)
1005{
1006 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1007 s->rtsr |= (1 << 10);
1008 pxa2xx_rtc_alarm_update(s, s->rtsr);
1009 pxa2xx_rtc_int_update(s);
1010}
1011
1012static inline void pxa2xx_rtc_pi_tick(void *opaque)
1013{
1014 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1015 s->rtsr |= (1 << 13);
1016 pxa2xx_rtc_piupdate(s);
1017 s->last_rtcpicr = 0;
1018 pxa2xx_rtc_alarm_update(s, s->rtsr);
1019 pxa2xx_rtc_int_update(s);
1020}
1021
1022static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1023{
1024 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1025 addr -= s->rtc_base;
1026
1027 switch (addr) {
1028 case RTTR:
1029 return s->rttr;
1030 case RTSR:
1031 return s->rtsr;
1032 case RTAR:
1033 return s->rtar;
1034 case RDAR1:
1035 return s->rdar1;
1036 case RDAR2:
1037 return s->rdar2;
1038 case RYAR1:
1039 return s->ryar1;
1040 case RYAR2:
1041 return s->ryar2;
1042 case SWAR1:
1043 return s->swar1;
1044 case SWAR2:
1045 return s->swar2;
1046 case PIAR:
1047 return s->piar;
1048 case RCNR:
1049 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1050 (1000 * ((s->rttr & 0xffff) + 1));
1051 case RDCR:
1052 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1053 (1000 * ((s->rttr & 0xffff) + 1));
1054 case RYCR:
1055 return s->last_rycr;
1056 case SWCR:
1057 if (s->rtsr & (1 << 12))
1058 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1059 else
1060 return s->last_swcr;
1061 default:
1062 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1063 break;
1064 }
1065 return 0;
1066}
1067
1068static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1069 uint32_t value)
1070{
1071 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1072 addr -= s->rtc_base;
1073
1074 switch (addr) {
1075 case RTTR:
1076 if (!(s->rttr & (1 << 31))) {
1077 pxa2xx_rtc_hzupdate(s);
1078 s->rttr = value;
1079 pxa2xx_rtc_alarm_update(s, s->rtsr);
1080 }
1081 break;
1082
1083 case RTSR:
1084 if ((s->rtsr ^ value) & (1 << 15))
1085 pxa2xx_rtc_piupdate(s);
1086
1087 if ((s->rtsr ^ value) & (1 << 12))
1088 pxa2xx_rtc_swupdate(s);
1089
1090 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1091 pxa2xx_rtc_alarm_update(s, value);
1092
1093 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1094 pxa2xx_rtc_int_update(s);
1095 break;
1096
1097 case RTAR:
1098 s->rtar = value;
1099 pxa2xx_rtc_alarm_update(s, s->rtsr);
1100 break;
1101
1102 case RDAR1:
1103 s->rdar1 = value;
1104 pxa2xx_rtc_alarm_update(s, s->rtsr);
1105 break;
1106
1107 case RDAR2:
1108 s->rdar2 = value;
1109 pxa2xx_rtc_alarm_update(s, s->rtsr);
1110 break;
1111
1112 case RYAR1:
1113 s->ryar1 = value;
1114 pxa2xx_rtc_alarm_update(s, s->rtsr);
1115 break;
1116
1117 case RYAR2:
1118 s->ryar2 = value;
1119 pxa2xx_rtc_alarm_update(s, s->rtsr);
1120 break;
1121
1122 case SWAR1:
1123 pxa2xx_rtc_swupdate(s);
1124 s->swar1 = value;
1125 s->last_swcr = 0;
1126 pxa2xx_rtc_alarm_update(s, s->rtsr);
1127 break;
1128
1129 case SWAR2:
1130 s->swar2 = value;
1131 pxa2xx_rtc_alarm_update(s, s->rtsr);
1132 break;
1133
1134 case PIAR:
1135 s->piar = value;
1136 pxa2xx_rtc_alarm_update(s, s->rtsr);
1137 break;
1138
1139 case RCNR:
1140 pxa2xx_rtc_hzupdate(s);
1141 s->last_rcnr = value;
1142 pxa2xx_rtc_alarm_update(s, s->rtsr);
1143 break;
1144
1145 case RDCR:
1146 pxa2xx_rtc_hzupdate(s);
1147 s->last_rdcr = value;
1148 pxa2xx_rtc_alarm_update(s, s->rtsr);
1149 break;
1150
1151 case RYCR:
1152 s->last_rycr = value;
1153 break;
1154
1155 case SWCR:
1156 pxa2xx_rtc_swupdate(s);
1157 s->last_swcr = value;
1158 pxa2xx_rtc_alarm_update(s, s->rtsr);
1159 break;
1160
1161 case RTCPICR:
1162 pxa2xx_rtc_piupdate(s);
1163 s->last_rtcpicr = value & 0xffff;
1164 pxa2xx_rtc_alarm_update(s, s->rtsr);
1165 break;
1166
1167 default:
1168 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1169 }
1170}
1171
aa941b94
AZ		 1172static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1173 pxa2xx_rtc_read,
1174 pxa2xx_rtc_read,
1175 pxa2xx_rtc_read,
1176};
1177
1178static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1179 pxa2xx_rtc_write,
1180 pxa2xx_rtc_write,
1181 pxa2xx_rtc_write,
1182};
1183
1184static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
c1713132 1185{
f6503059 1186 struct tm tm;
c1713132
AZ		 1187 int wom;
1188
1189 s->rttr = 0x7fff;
1190 s->rtsr = 0;
1191
f6503059
AZ		 1192 qemu_get_timedate(&tm, 0);
1193 wom = ((tm.tm_mday - 1) / 7) + 1;
1194
1195 s->last_rcnr = (uint32_t) mktime(&tm);
1196 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1197 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1198 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1199 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1200 s->last_swcr = (tm.tm_hour << 19) |
1201 (tm.tm_min << 13) | (tm.tm_sec << 7);
c1713132
AZ		 1202 s->last_rtcpicr = 0;
1203 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1204
1205 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1206 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1207 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1208 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1209 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1210 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1211}
1212
aa941b94
AZ		 1213static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1214{
1215 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132 1216
aa941b94
AZ		 1217 pxa2xx_rtc_hzupdate(s);
1218 pxa2xx_rtc_piupdate(s);
1219 pxa2xx_rtc_swupdate(s);
1220
1221 qemu_put_be32s(f, &s->rttr);
1222 qemu_put_be32s(f, &s->rtsr);
1223 qemu_put_be32s(f, &s->rtar);
1224 qemu_put_be32s(f, &s->rdar1);
1225 qemu_put_be32s(f, &s->rdar2);
1226 qemu_put_be32s(f, &s->ryar1);
1227 qemu_put_be32s(f, &s->ryar2);
1228 qemu_put_be32s(f, &s->swar1);
1229 qemu_put_be32s(f, &s->swar2);
1230 qemu_put_be32s(f, &s->piar);
1231 qemu_put_be32s(f, &s->last_rcnr);
1232 qemu_put_be32s(f, &s->last_rdcr);
1233 qemu_put_be32s(f, &s->last_rycr);
1234 qemu_put_be32s(f, &s->last_swcr);
1235 qemu_put_be32s(f, &s->last_rtcpicr);
a050e24d
AZ		 1236 qemu_put_be64s(f, (uint64_t *) &s->last_hz);
1237 qemu_put_be64s(f, (uint64_t *) &s->last_sw);
1238 qemu_put_be64s(f, (uint64_t *) &s->last_pi);
aa941b94
AZ		 1239}
1240
1241static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1242{
1243 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1244
1245 qemu_get_be32s(f, &s->rttr);
1246 qemu_get_be32s(f, &s->rtsr);
1247 qemu_get_be32s(f, &s->rtar);
1248 qemu_get_be32s(f, &s->rdar1);
1249 qemu_get_be32s(f, &s->rdar2);
1250 qemu_get_be32s(f, &s->ryar1);
1251 qemu_get_be32s(f, &s->ryar2);
1252 qemu_get_be32s(f, &s->swar1);
1253 qemu_get_be32s(f, &s->swar2);
1254 qemu_get_be32s(f, &s->piar);
1255 qemu_get_be32s(f, &s->last_rcnr);
1256 qemu_get_be32s(f, &s->last_rdcr);
1257 qemu_get_be32s(f, &s->last_rycr);
1258 qemu_get_be32s(f, &s->last_swcr);
1259 qemu_get_be32s(f, &s->last_rtcpicr);
a050e24d
AZ		 1260 qemu_get_be64s(f, (uint64_t *) &s->last_hz);
1261 qemu_get_be64s(f, (uint64_t *) &s->last_sw);
1262 qemu_get_be64s(f, (uint64_t *) &s->last_pi);
aa941b94
AZ		 1263
1264 pxa2xx_rtc_alarm_update(s, s->rtsr);
1265
1266 return 0;
1267}
c1713132 1268
3f582262
AZ		 1269/* I2C Interface */
1270struct pxa2xx_i2c_s {
1271 i2c_slave slave;
1272 i2c_bus *bus;
1273 target_phys_addr_t base;
1274 qemu_irq irq;
1275
1276 uint16_t control;
1277 uint16_t status;
1278 uint8_t ibmr;
1279 uint8_t data;
1280};
1281
1282#define IBMR 0x80 /* I2C Bus Monitor register */
1283#define IDBR 0x88 /* I2C Data Buffer register */
1284#define ICR 0x90 /* I2C Control register */
1285#define ISR 0x98 /* I2C Status register */
1286#define ISAR 0xa0 /* I2C Slave Address register */
1287
1288static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
1289{
1290 uint16_t level = 0;
1291 level |= s->status & s->control & (1 << 10); /* BED */
1292 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1293 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1294 level |= s->status & (1 << 9); /* SAD */
1295 qemu_set_irq(s->irq, !!level);
1296}
1297
1298/* These are only stubs now. */
1299static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1300{
1301 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1302
1303 switch (event) {
1304 case I2C_START_SEND:
1305 s->status |= (1 << 9); /* set SAD */
1306 s->status &= ~(1 << 0); /* clear RWM */
1307 break;
1308 case I2C_START_RECV:
1309 s->status |= (1 << 9); /* set SAD */
1310 s->status |= 1 << 0; /* set RWM */
1311 break;
1312 case I2C_FINISH:
1313 s->status |= (1 << 4); /* set SSD */
1314 break;
1315 case I2C_NACK:
1316 s->status |= 1 << 1; /* set ACKNAK */
1317 break;
1318 }
1319 pxa2xx_i2c_update(s);
1320}
1321
1322static int pxa2xx_i2c_rx(i2c_slave *i2c)
1323{
1324 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1325 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1326 return 0;
1327
1328 if (s->status & (1 << 0)) { /* RWM */
1329 s->status |= 1 << 6; /* set ITE */
1330 }
1331 pxa2xx_i2c_update(s);
1332
1333 return s->data;
1334}
1335
1336static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1337{
1338 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1339 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1340 return 1;
1341
1342 if (!(s->status & (1 << 0))) { /* RWM */
1343 s->status |= 1 << 7; /* set IRF */
1344 s->data = data;
1345 }
1346 pxa2xx_i2c_update(s);
1347
1348 return 1;
1349}
1350
1351static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1352{
1353 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1354 addr -= s->base;
1355
1356 switch (addr) {
1357 case ICR:
1358 return s->control;
1359 case ISR:
1360 return s->status | (i2c_bus_busy(s->bus) << 2);
1361 case ISAR:
1362 return s->slave.address;
1363 case IDBR:
1364 return s->data;
1365 case IBMR:
1366 if (s->status & (1 << 2))
1367 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1368 else
1369 s->ibmr = 0;
1370 return s->ibmr;
1371 default:
1372 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1373 break;
1374 }
1375 return 0;
1376}
1377
1378static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1379 uint32_t value)
1380{
1381 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1382 int ack;
1383 addr -= s->base;
1384
1385 switch (addr) {
1386 case ICR:
1387 s->control = value & 0xfff7;
1388 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1389 /* TODO: slave mode */
1390 if (value & (1 << 0)) { /* START condition */
1391 if (s->data & 1)
1392 s->status |= 1 << 0; /* set RWM */
1393 else
1394 s->status &= ~(1 << 0); /* clear RWM */
1395 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1396 } else {
1397 if (s->status & (1 << 0)) { /* RWM */
1398 s->data = i2c_recv(s->bus);
1399 if (value & (1 << 2)) /* ACKNAK */
1400 i2c_nack(s->bus);
1401 ack = 1;
1402 } else
1403 ack = !i2c_send(s->bus, s->data);
1404 }
1405
1406 if (value & (1 << 1)) /* STOP condition */
1407 i2c_end_transfer(s->bus);
1408
1409 if (ack) {
1410 if (value & (1 << 0)) /* START condition */
1411 s->status |= 1 << 6; /* set ITE */
1412 else
1413 if (s->status & (1 << 0)) /* RWM */
1414 s->status |= 1 << 7; /* set IRF */
1415 else
1416 s->status |= 1 << 6; /* set ITE */
1417 s->status &= ~(1 << 1); /* clear ACKNAK */
1418 } else {
1419 s->status |= 1 << 6; /* set ITE */
1420 s->status |= 1 << 10; /* set BED */
1421 s->status |= 1 << 1; /* set ACKNAK */
1422 }
1423 }
1424 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1425 if (value & (1 << 4)) /* MA */
1426 i2c_end_transfer(s->bus);
1427 pxa2xx_i2c_update(s);
1428 break;
1429
1430 case ISR:
1431 s->status &= ~(value & 0x07f0);
1432 pxa2xx_i2c_update(s);
1433 break;
1434
1435 case ISAR:
1436 i2c_set_slave_address(&s->slave, value & 0x7f);
1437 break;
1438
1439 case IDBR:
1440 s->data = value & 0xff;
1441 break;
1442
1443 default:
1444 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1445 }
1446}
1447
1448static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
1449 pxa2xx_i2c_read,
1450 pxa2xx_i2c_read,
1451 pxa2xx_i2c_read,
1452};
1453
1454static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1455 pxa2xx_i2c_write,
1456 pxa2xx_i2c_write,
1457 pxa2xx_i2c_write,
1458};
1459
aa941b94
AZ		 1460static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1461{
1462 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1463
1464 qemu_put_be16s(f, &s->control);
1465 qemu_put_be16s(f, &s->status);
1466 qemu_put_8s(f, &s->ibmr);
1467 qemu_put_8s(f, &s->data);
1468
1469 i2c_bus_save(f, s->bus);
1470 i2c_slave_save(f, &s->slave);
1471}
1472
1473static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1474{
1475 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1476
1477 qemu_get_be16s(f, &s->control);
1478 qemu_get_be16s(f, &s->status);
1479 qemu_get_8s(f, &s->ibmr);
1480 qemu_get_8s(f, &s->data);
1481
1482 i2c_bus_load(f, s->bus);
1483 i2c_slave_load(f, &s->slave);
1484 return 0;
1485}
1486
3f582262 1487struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929 1488 qemu_irq irq, uint32_t page_size)
3f582262
AZ		 1489{
1490 int iomemtype;
1491 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
3f6c925f 1492 i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
3f582262
AZ		 1493
1494 s->base = base;
1495 s->irq = irq;
1496 s->slave.event = pxa2xx_i2c_event;
1497 s->slave.recv = pxa2xx_i2c_rx;
1498 s->slave.send = pxa2xx_i2c_tx;
1499 s->bus = i2c_init_bus();
1500
2a163929
AZ		 1501 iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
1502 pxa2xx_i2c_writefn, s);
1503 cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
3f582262 1504
aa941b94
AZ		 1505 register_savevm("pxa2xx_i2c", base, 0,
1506 pxa2xx_i2c_save, pxa2xx_i2c_load, s);
1507
3f582262
AZ		 1508 return s;
1509}
1510
1511i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
1512{
1513 return s->bus;
1514}
1515
c1713132
AZ		 1516/* PXA Inter-IC Sound Controller */
1517static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1518{
1519 i2s->rx_len = 0;
1520 i2s->tx_len = 0;
1521 i2s->fifo_len = 0;
1522 i2s->clk = 0x1a;
1523 i2s->control[0] = 0x00;
1524 i2s->control[1] = 0x00;
1525 i2s->status = 0x00;
1526 i2s->mask = 0x00;
1527}
1528
1529#define SACR_TFTH(val) ((val >> 8) & 0xf)
1530#define SACR_RFTH(val) ((val >> 12) & 0xf)
1531#define SACR_DREC(val) (val & (1 << 3))
1532#define SACR_DPRL(val) (val & (1 << 4))
1533
1534static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1535{
1536 int rfs, tfs;
1537 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1538 !SACR_DREC(i2s->control[1]);
1539 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1540 i2s->enable && !SACR_DPRL(i2s->control[1]);
1541
1542 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1543 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1544
1545 i2s->status &= 0xe0;
59c0149b
AZ		 1546 if (i2s->fifo_len < 16 || !i2s->enable)
1547 i2s->status |= 1 << 0; /* TNF */
c1713132
AZ		 1548 if (i2s->rx_len)
1549 i2s->status |= 1 << 1; /* RNE */
1550 if (i2s->enable)
1551 i2s->status |= 1 << 2; /* BSY */
1552 if (tfs)
1553 i2s->status |= 1 << 3; /* TFS */
1554 if (rfs)
1555 i2s->status |= 1 << 4; /* RFS */
1556 if (!(i2s->tx_len && i2s->enable))
1557 i2s->status |= i2s->fifo_len << 8; /* TFL */
1558 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1559
1560 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1561}
1562
1563#define SACR0 0x00 /* Serial Audio Global Control register */
1564#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1565#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1566#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1567#define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1568#define SADIV 0x60 /* Serial Audio Clock Divider register */
1569#define SADR 0x80 /* Serial Audio Data register */
1570
1571static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1572{
1573 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1574 addr -= s->base;
1575
1576 switch (addr) {
1577 case SACR0:
1578 return s->control[0];
1579 case SACR1:
1580 return s->control[1];
1581 case SASR0:
1582 return s->status;
1583 case SAIMR:
1584 return s->mask;
1585 case SAICR:
1586 return 0;
1587 case SADIV:
1588 return s->clk;
1589 case SADR:
1590 if (s->rx_len > 0) {
1591 s->rx_len --;
1592 pxa2xx_i2s_update(s);
1593 return s->codec_in(s->opaque);
1594 }
1595 return 0;
1596 default:
1597 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1598 break;
1599 }
1600 return 0;
1601}
1602
1603static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1604 uint32_t value)
1605{
1606 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1607 uint32_t *sample;
1608 addr -= s->base;
1609
1610 switch (addr) {
1611 case SACR0:
1612 if (value & (1 << 3)) /* RST */
1613 pxa2xx_i2s_reset(s);
1614 s->control[0] = value & 0xff3d;
1615 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1616 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1617 s->codec_out(s->opaque, *sample);
1618 s->status &= ~(1 << 7); /* I2SOFF */
1619 }
1620 if (value & (1 << 4)) /* EFWR */
1621 printf("%s: Attempt to use special function\n", __FUNCTION__);
1622 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1623 pxa2xx_i2s_update(s);
1624 break;
1625 case SACR1:
1626 s->control[1] = value & 0x0039;
1627 if (value & (1 << 5)) /* ENLBF */
1628 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1629 if (value & (1 << 4)) /* DPRL */
1630 s->fifo_len = 0;
1631 pxa2xx_i2s_update(s);
1632 break;
1633 case SAIMR:
1634 s->mask = value & 0x0078;
1635 pxa2xx_i2s_update(s);
1636 break;
1637 case SAICR:
1638 s->status &= ~(value & (3 << 5));
1639 pxa2xx_i2s_update(s);
1640 break;
1641 case SADIV:
1642 s->clk = value & 0x007f;
1643 break;
1644 case SADR:
1645 if (s->tx_len && s->enable) {
1646 s->tx_len --;
1647 pxa2xx_i2s_update(s);
1648 s->codec_out(s->opaque, value);
1649 } else if (s->fifo_len < 16) {
1650 s->fifo[s->fifo_len ++] = value;
1651 pxa2xx_i2s_update(s);
1652 }
1653 break;
1654 default:
1655 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1656 }
1657}
1658
1659static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1660 pxa2xx_i2s_read,
1661 pxa2xx_i2s_read,
1662 pxa2xx_i2s_read,
1663};
1664
1665static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1666 pxa2xx_i2s_write,
1667 pxa2xx_i2s_write,
1668 pxa2xx_i2s_write,
1669};
1670
aa941b94
AZ		 1671static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1672{
1673 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1674
1675 qemu_put_be32s(f, &s->control[0]);
1676 qemu_put_be32s(f, &s->control[1]);
1677 qemu_put_be32s(f, &s->status);
1678 qemu_put_be32s(f, &s->mask);
1679 qemu_put_be32s(f, &s->clk);
1680
1681 qemu_put_be32(f, s->enable);
1682 qemu_put_be32(f, s->rx_len);
1683 qemu_put_be32(f, s->tx_len);
1684 qemu_put_be32(f, s->fifo_len);
1685}
1686
1687static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1688{
1689 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1690
1691 qemu_get_be32s(f, &s->control[0]);
1692 qemu_get_be32s(f, &s->control[1]);
1693 qemu_get_be32s(f, &s->status);
1694 qemu_get_be32s(f, &s->mask);
1695 qemu_get_be32s(f, &s->clk);
1696
1697 s->enable = qemu_get_be32(f);
1698 s->rx_len = qemu_get_be32(f);
1699 s->tx_len = qemu_get_be32(f);
1700 s->fifo_len = qemu_get_be32(f);
1701
1702 return 0;
1703}
1704
c1713132
AZ		 1705static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1706{
1707 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1708 uint32_t *sample;
1709
1710 /* Signal FIFO errors */
1711 if (s->enable && s->tx_len)
1712 s->status |= 1 << 5; /* TUR */
1713 if (s->enable && s->rx_len)
1714 s->status |= 1 << 6; /* ROR */
1715
1716 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1717 * handle the cases where it makes a difference. */
1718 s->tx_len = tx - s->fifo_len;
1719 s->rx_len = rx;
1720 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1721 if (s->enable)
1722 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1723 s->codec_out(s->opaque, *sample);
1724 pxa2xx_i2s_update(s);
1725}
1726
1727static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1728 qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1729{
1730 int iomemtype;
1731 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1732 qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1733
1734 s->base = base;
1735 s->irq = irq;
1736 s->dma = dma;
1737 s->data_req = pxa2xx_i2s_data_req;
1738
1739 pxa2xx_i2s_reset(s);
1740
1741 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1742 pxa2xx_i2s_writefn, s);
187337f8 1743 cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
c1713132 1744
aa941b94
AZ		 1745 register_savevm("pxa2xx_i2s", base, 0,
1746 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1747
c1713132
AZ		 1748 return s;
1749}
1750
1751/* PXA Fast Infra-red Communications Port */
1752struct pxa2xx_fir_s {
1753 target_phys_addr_t base;
1754 qemu_irq irq;
1755 struct pxa2xx_dma_state_s *dma;
1756 int enable;
1757 CharDriverState *chr;
1758
1759 uint8_t control[3];
1760 uint8_t status[2];
1761
1762 int rx_len;
1763 int rx_start;
1764 uint8_t rx_fifo[64];
1765};
1766
1767static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1768{
1769 s->control[0] = 0x00;
1770 s->control[1] = 0x00;
1771 s->control[2] = 0x00;
1772 s->status[0] = 0x00;
1773 s->status[1] = 0x00;
1774 s->enable = 0;
1775}
1776
1777static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1778{
1779 static const int tresh[4] = { 8, 16, 32, 0 };
1780 int intr = 0;
1781 if ((s->control[0] & (1 << 4)) && /* RXE */
1782 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1783 s->status[0] |= 1 << 4; /* RFS */
1784 else
1785 s->status[0] &= ~(1 << 4); /* RFS */
1786 if (s->control[0] & (1 << 3)) /* TXE */
1787 s->status[0] |= 1 << 3; /* TFS */
1788 else
1789 s->status[0] &= ~(1 << 3); /* TFS */
1790 if (s->rx_len)
1791 s->status[1] |= 1 << 2; /* RNE */
1792 else
1793 s->status[1] &= ~(1 << 2); /* RNE */
1794 if (s->control[0] & (1 << 4)) /* RXE */
1795 s->status[1] |= 1 << 0; /* RSY */
1796 else
1797 s->status[1] &= ~(1 << 0); /* RSY */
1798
1799 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1800 (s->status[0] & (1 << 4)); /* RFS */
1801 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1802 (s->status[0] & (1 << 3)); /* TFS */
1803 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1804 (s->status[0] & (1 << 6)); /* EOC */
1805 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1806 (s->status[0] & (1 << 1)); /* TUR */
1807 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1808
1809 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1810 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1811
1812 qemu_set_irq(s->irq, intr && s->enable);
1813}
1814
1815#define ICCR0 0x00 /* FICP Control register 0 */
1816#define ICCR1 0x04 /* FICP Control register 1 */
1817#define ICCR2 0x08 /* FICP Control register 2 */
1818#define ICDR 0x0c /* FICP Data register */
1819#define ICSR0 0x14 /* FICP Status register 0 */
1820#define ICSR1 0x18 /* FICP Status register 1 */
1821#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1822
1823static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1824{
1825 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1826 uint8_t ret;
1827 addr -= s->base;
1828
1829 switch (addr) {
1830 case ICCR0:
1831 return s->control[0];
1832 case ICCR1:
1833 return s->control[1];
1834 case ICCR2:
1835 return s->control[2];
1836 case ICDR:
1837 s->status[0] &= ~0x01;
1838 s->status[1] &= ~0x72;
1839 if (s->rx_len) {
1840 s->rx_len --;
1841 ret = s->rx_fifo[s->rx_start ++];
1842 s->rx_start &= 63;
1843 pxa2xx_fir_update(s);
1844 return ret;
1845 }
1846 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1847 break;
1848 case ICSR0:
1849 return s->status[0];
1850 case ICSR1:
1851 return s->status[1] | (1 << 3); /* TNF */
1852 case ICFOR:
1853 return s->rx_len;
1854 default:
1855 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1856 break;
1857 }
1858 return 0;
1859}
1860
1861static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1862 uint32_t value)
1863{
1864 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1865 uint8_t ch;
1866 addr -= s->base;
1867
1868 switch (addr) {
1869 case ICCR0:
1870 s->control[0] = value;
1871 if (!(value & (1 << 4))) /* RXE */
1872 s->rx_len = s->rx_start = 0;
1873 if (!(value & (1 << 3))) /* TXE */
1874 /* Nop */;
1875 s->enable = value & 1; /* ITR */
1876 if (!s->enable)
1877 s->status[0] = 0;
1878 pxa2xx_fir_update(s);
1879 break;
1880 case ICCR1:
1881 s->control[1] = value;
1882 break;
1883 case ICCR2:
1884 s->control[2] = value & 0x3f;
1885 pxa2xx_fir_update(s);
1886 break;
1887 case ICDR:
1888 if (s->control[2] & (1 << 2)) /* TXP */
1889 ch = value;
1890 else
1891 ch = ~value;
1892 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1893 qemu_chr_write(s->chr, &ch, 1);
1894 break;
1895 case ICSR0:
1896 s->status[0] &= ~(value & 0x66);
1897 pxa2xx_fir_update(s);
1898 break;
1899 case ICFOR:
1900 break;
1901 default:
1902 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1903 }
1904}
1905
1906static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1907 pxa2xx_fir_read,
1908 pxa2xx_fir_read,
1909 pxa2xx_fir_read,
1910};
1911
1912static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1913 pxa2xx_fir_write,
1914 pxa2xx_fir_write,
1915 pxa2xx_fir_write,
1916};
1917
1918static int pxa2xx_fir_is_empty(void *opaque)
1919{
1920 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1921 return (s->rx_len < 64);
1922}
1923
1924static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1925{
1926 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1927 if (!(s->control[0] & (1 << 4))) /* RXE */
1928 return;
1929
1930 while (size --) {
1931 s->status[1] |= 1 << 4; /* EOF */
1932 if (s->rx_len >= 64) {
1933 s->status[1] |= 1 << 6; /* ROR */
1934 break;
1935 }
1936
1937 if (s->control[2] & (1 << 3)) /* RXP */
1938 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1939 else
1940 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1941 }
1942
1943 pxa2xx_fir_update(s);
1944}
1945
1946static void pxa2xx_fir_event(void *opaque, int event)
1947{
1948}
1949
aa941b94
AZ		 1950static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1951{
1952 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1953 int i;
1954
1955 qemu_put_be32(f, s->enable);
1956
1957 qemu_put_8s(f, &s->control[0]);
1958 qemu_put_8s(f, &s->control[1]);
1959 qemu_put_8s(f, &s->control[2]);
1960 qemu_put_8s(f, &s->status[0]);
1961 qemu_put_8s(f, &s->status[1]);
1962
1963 qemu_put_byte(f, s->rx_len);
1964 for (i = 0; i < s->rx_len; i ++)
1965 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1966}
1967
1968static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1969{
1970 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1971 int i;
1972
1973 s->enable = qemu_get_be32(f);
1974
1975 qemu_get_8s(f, &s->control[0]);
1976 qemu_get_8s(f, &s->control[1]);
1977 qemu_get_8s(f, &s->control[2]);
1978 qemu_get_8s(f, &s->status[0]);
1979 qemu_get_8s(f, &s->status[1]);
1980
1981 s->rx_len = qemu_get_byte(f);
1982 s->rx_start = 0;
1983 for (i = 0; i < s->rx_len; i ++)
1984 s->rx_fifo[i] = qemu_get_byte(f);
1985
1986 return 0;
1987}
1988
c1713132
AZ		 1989static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1990 qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1991 CharDriverState *chr)
1992{
1993 int iomemtype;
1994 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1995 qemu_mallocz(sizeof(struct pxa2xx_fir_s));
1996
1997 s->base = base;
1998 s->irq = irq;
1999 s->dma = dma;
2000 s->chr = chr;
2001
2002 pxa2xx_fir_reset(s);
2003
2004 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
2005 pxa2xx_fir_writefn, s);
187337f8 2006 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
c1713132
AZ		 2007
2008 if (chr)
2009 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2010 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2011
aa941b94
AZ		 2012 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
2013
c1713132
AZ		 2014 return s;
2015}
2016
38641a52 2017static void pxa2xx_reset(void *opaque, int line, int level)
c1713132
AZ		 2018{
2019 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
38641a52 2020
c1713132
AZ		 2021 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2022 cpu_reset(s->env);
2023 /* TODO: reset peripherals */
2024 }
2025}
2026
2027/* Initialise a PXA270 integrated chip (ARM based core). */
d95b2f8d
AZ		 2028struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2029 DisplayState *ds, const char *revision)
c1713132
AZ		 2030{
2031 struct pxa2xx_state_s *s;
2032 struct pxa2xx_ssp_s *ssp;
c1713132 2033 int iomemtype, i;
e4bcb14c 2034 int index;
c1713132
AZ		 2035 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2036
4207117c
AZ		 2037 if (revision && strncmp(revision, "pxa27", 5)) {
2038 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2039 exit(1);
2040 }
aaed909a
FB		 2041 if (!revision)
2042 revision = "pxa270";
2043
2044 s->env = cpu_init(revision);
2045 if (!s->env) {
2046 fprintf(stderr, "Unable to find CPU definition\n");
2047 exit(1);
2048 }
38641a52
AZ		 2049 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2050
d95b2f8d
AZ		 2051 /* SDRAM & Internal Memory Storage */
2052 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2053 sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2054 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2055 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
2056
c1713132
AZ		 2057 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2058
2059 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2060
a171fe39 2061 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
3f582262 2062 s->pic[PXA27X_PIC_OST_4_11]);
a171fe39 2063
c1713132
AZ		 2064 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2065
e4bcb14c
TS		 2066 index = drive_get_index(IF_SD, 0, 0);
2067 if (index == -1) {
2068 fprintf(stderr, "qemu: missing SecureDigital device\n");
2069 exit(1);
2070 }
2071 s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2072 s->pic[PXA2XX_PIC_MMC], s->dma);
a171fe39 2073
c1713132
AZ		 2074 for (i = 0; pxa270_serial[i].io_base; i ++)
2075 if (serial_hds[i])
2076 serial_mm_init(pxa270_serial[i].io_base, 2,
b6cd0ea1
AJ		 2077 s->pic[pxa270_serial[i].irqn], 14857000/16,
2078 serial_hds[i], 1);
c1713132
AZ		 2079 else
2080 break;
2081 if (serial_hds[i])
2082 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2083 s->dma, serial_hds[i]);
2084
a171fe39
AZ		 2085 if (ds)
2086 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2087
c1713132 2088 s->cm_base = 0x41300000;
82d17978 2089 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
c1713132
AZ		 2090 s->clkcfg = 0x00000009; /* Turbo mode active */
2091 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2092 pxa2xx_cm_writefn, s);
187337f8 2093 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
aa941b94 2094 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
c1713132
AZ		 2095
2096 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2097
2098 s->mm_base = 0x48000000;
2099 s->mm_regs[MDMRS >> 2] = 0x00020002;
2100 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2101 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2102 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2103 pxa2xx_mm_writefn, s);
187337f8 2104 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
aa941b94 2105 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
c1713132 2106
2a163929
AZ		 2107 s->pm_base = 0x40f00000;
2108 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2109 pxa2xx_pm_writefn, s);
187337f8 2110 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2a163929
AZ		 2111 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2112
c1713132
AZ		 2113 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2114 s->ssp = (struct pxa2xx_ssp_s **)
2115 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2116 ssp = (struct pxa2xx_ssp_s *)
2117 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2118 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2119 s->ssp[i] = &ssp[i];
2120 ssp[i].base = pxa27x_ssp[i].io_base;
2121 ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
2122
2123 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2124 pxa2xx_ssp_writefn, &ssp[i]);
187337f8 2125 cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
aa941b94
AZ		 2126 register_savevm("pxa2xx_ssp", i, 0,
2127 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
c1713132
AZ		 2128 }
2129
a171fe39
AZ		 2130 if (usb_enabled) {
2131 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2132 }
2133
2134 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2135 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2136
c1713132
AZ		 2137 s->rtc_base = 0x40900000;
2138 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2139 pxa2xx_rtc_writefn, s);
187337f8 2140 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
aa941b94
AZ		 2141 pxa2xx_rtc_init(s);
2142 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
c1713132 2143
2a163929
AZ		 2144 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2145 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
c1713132
AZ		 2146
2147 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2148
31b87f2e
AZ		 2149 s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
2150
c1713132 2151 /* GPIO1 resets the processor */
fe8f096b 2152 /* The handler can be overridden by board-specific code */
38641a52 2153 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
c1713132
AZ		 2154 return s;
2155}
2156
2157/* Initialise a PXA255 integrated chip (ARM based core). */
d95b2f8d
AZ		 2158struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2159 DisplayState *ds)
c1713132
AZ		 2160{
2161 struct pxa2xx_state_s *s;
2162 struct pxa2xx_ssp_s *ssp;
2163 int iomemtype, i;
e4bcb14c 2164 int index;
aaed909a 2165
c1713132
AZ		 2166 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2167
aaed909a
FB		 2168 s->env = cpu_init("pxa255");
2169 if (!s->env) {
2170 fprintf(stderr, "Unable to find CPU definition\n");
2171 exit(1);
2172 }
38641a52
AZ		 2173 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2174
d95b2f8d 2175 /* SDRAM & Internal Memory Storage */
a07dec22
AZ		 2176 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2177 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2178 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2179 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
d95b2f8d 2180
c1713132
AZ		 2181 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2182
2183 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2184
3f582262 2185 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
a171fe39 2186
3bdd58a4 2187 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
c1713132 2188
e4bcb14c
TS		 2189 index = drive_get_index(IF_SD, 0, 0);
2190 if (index == -1) {
2191 fprintf(stderr, "qemu: missing SecureDigital device\n");
2192 exit(1);
2193 }
2194 s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2195 s->pic[PXA2XX_PIC_MMC], s->dma);
a171fe39 2196
c1713132
AZ		 2197 for (i = 0; pxa255_serial[i].io_base; i ++)
2198 if (serial_hds[i])
2199 serial_mm_init(pxa255_serial[i].io_base, 2,
b6cd0ea1
AJ		 2200 s->pic[pxa255_serial[i].irqn], 14745600/16,
2201 serial_hds[i], 1);
c1713132
AZ		 2202 else
2203 break;
2204 if (serial_hds[i])
2205 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2206 s->dma, serial_hds[i]);
2207
a171fe39
AZ		 2208 if (ds)
2209 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2210
c1713132 2211 s->cm_base = 0x41300000;
82d17978 2212 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
c1713132
AZ		 2213 s->clkcfg = 0x00000009; /* Turbo mode active */
2214 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2215 pxa2xx_cm_writefn, s);
187337f8 2216 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
aa941b94 2217 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
c1713132
AZ		 2218
2219 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2220
2221 s->mm_base = 0x48000000;
2222 s->mm_regs[MDMRS >> 2] = 0x00020002;
2223 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2224 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2225 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2226 pxa2xx_mm_writefn, s);
187337f8 2227 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
aa941b94 2228 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
c1713132 2229
2a163929
AZ		 2230 s->pm_base = 0x40f00000;
2231 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2232 pxa2xx_pm_writefn, s);
187337f8 2233 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2a163929
AZ		 2234 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2235
c1713132
AZ		 2236 for (i = 0; pxa255_ssp[i].io_base; i ++);
2237 s->ssp = (struct pxa2xx_ssp_s **)
2238 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2239 ssp = (struct pxa2xx_ssp_s *)
2240 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2241 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2242 s->ssp[i] = &ssp[i];
2243 ssp[i].base = pxa255_ssp[i].io_base;
2244 ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
2245
2246 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2247 pxa2xx_ssp_writefn, &ssp[i]);
187337f8 2248 cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
aa941b94
AZ		 2249 register_savevm("pxa2xx_ssp", i, 0,
2250 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
c1713132
AZ		 2251 }
2252
a171fe39
AZ		 2253 if (usb_enabled) {
2254 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2255 }
2256
2257 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2258 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2259
c1713132
AZ		 2260 s->rtc_base = 0x40900000;
2261 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2262 pxa2xx_rtc_writefn, s);
187337f8 2263 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
aa941b94
AZ		 2264 pxa2xx_rtc_init(s);
2265 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
c1713132 2266
2a163929
AZ		 2267 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2268 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
c1713132
AZ		 2269
2270 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2271
2272 /* GPIO1 resets the processor */
fe8f096b 2273 /* The handler can be overridden by board-specific code */
38641a52 2274 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
c1713132
AZ		 2275 return s;
2276}
QEMU mirror