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[mirror_qemu.git] / hw / pxa2xx.c
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c1713132
AZ		 1/*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10# include "vl.h"
11
12static struct {
13 target_phys_addr_t io_base;
14 int irqn;
15} pxa255_serial[] = {
16 { 0x40100000, PXA2XX_PIC_FFUART },
17 { 0x40200000, PXA2XX_PIC_BTUART },
18 { 0x40700000, PXA2XX_PIC_STUART },
19 { 0x41600000, PXA25X_PIC_HWUART },
20 { 0, 0 }
21}, pxa270_serial[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART },
23 { 0x40200000, PXA2XX_PIC_BTUART },
24 { 0x40700000, PXA2XX_PIC_STUART },
25 { 0, 0 }
26};
27
28static struct {
29 target_phys_addr_t io_base;
30 int irqn;
31} pxa250_ssp[] = {
32 { 0x41000000, PXA2XX_PIC_SSP },
33 { 0, 0 }
34}, pxa255_ssp[] = {
35 { 0x41000000, PXA2XX_PIC_SSP },
36 { 0x41400000, PXA25X_PIC_NSSP },
37 { 0, 0 }
38}, pxa26x_ssp[] = {
39 { 0x41000000, PXA2XX_PIC_SSP },
40 { 0x41400000, PXA25X_PIC_NSSP },
41 { 0x41500000, PXA26X_PIC_ASSP },
42 { 0, 0 }
43}, pxa27x_ssp[] = {
44 { 0x41000000, PXA2XX_PIC_SSP },
45 { 0x41700000, PXA27X_PIC_SSP2 },
46 { 0x41900000, PXA2XX_PIC_SSP3 },
47 { 0, 0 }
48};
49
50#define PMCR 0x00 /* Power Manager Control register */
51#define PSSR 0x04 /* Power Manager Sleep Status register */
52#define PSPR 0x08 /* Power Manager Scratch-Pad register */
53#define PWER 0x0c /* Power Manager Wake-Up Enable register */
54#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56#define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57#define PCFR 0x1c /* Power Manager General Configuration register */
58#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62#define RCSR 0x30 /* Reset Controller Status register */
63#define PSLR 0x34 /* Power Manager Sleep Configuration register */
64#define PTSR 0x38 /* Power Manager Standby Configuration register */
65#define PVCR 0x40 /* Power Manager Voltage Change Control register */
66#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
71
72static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
73{
74 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
75 addr -= s->pm_base;
76
77 switch (addr) {
78 case PMCR ... PCMD31:
79 if (addr & 3)
80 goto fail;
81
82 return s->pm_regs[addr >> 2];
83 default:
84 fail:
85 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
86 break;
87 }
88 return 0;
89}
90
91static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
92 uint32_t value)
93{
94 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
95 addr -= s->pm_base;
96
97 switch (addr) {
98 case PMCR:
99 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
100 s->pm_regs[addr >> 2] |= value & 0x15;
101 break;
102
103 case PSSR: /* Read-clean registers */
104 case RCSR:
105 case PKSR:
106 s->pm_regs[addr >> 2] &= ~value;
107 break;
108
109 default: /* Read-write registers */
110 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
111 s->pm_regs[addr >> 2] = value;
112 break;
113 }
114
115 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
116 break;
117 }
118}
119
120static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
121 pxa2xx_pm_read,
122 pxa2xx_pm_read,
123 pxa2xx_pm_read,
124};
125
126static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
127 pxa2xx_pm_write,
128 pxa2xx_pm_write,
129 pxa2xx_pm_write,
130};
131
aa941b94
AZ		 132static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
133{
134 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
135 int i;
136
137 for (i = 0; i < 0x40; i ++)
138 qemu_put_be32s(f, &s->pm_regs[i]);
139}
140
141static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
142{
143 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
144 int i;
145
146 for (i = 0; i < 0x40; i ++)
147 qemu_get_be32s(f, &s->pm_regs[i]);
148
149 return 0;
150}
151
c1713132
AZ		 152#define CCCR 0x00 /* Core Clock Configuration register */
153#define CKEN 0x04 /* Clock Enable register */
154#define OSCC 0x08 /* Oscillator Configuration register */
155#define CCSR 0x0c /* Core Clock Status register */
156
157static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
158{
159 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
160 addr -= s->cm_base;
161
162 switch (addr) {
163 case CCCR:
164 case CKEN:
165 case OSCC:
166 return s->cm_regs[addr >> 2];
167
168 case CCSR:
169 return s->cm_regs[CCCR >> 2] | (3 << 28);
170
171 default:
172 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
173 break;
174 }
175 return 0;
176}
177
178static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
179 uint32_t value)
180{
181 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
182 addr -= s->cm_base;
183
184 switch (addr) {
185 case CCCR:
186 case CKEN:
187 s->cm_regs[addr >> 2] = value;
188 break;
189
190 case OSCC:
565d2895 191 s->cm_regs[addr >> 2] &= ~0x6c;
c1713132 192 s->cm_regs[addr >> 2] |= value & 0x6e;
565d2895
AZ		 193 if ((value >> 1) & 1) /* OON */
194 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
c1713132
AZ		 195 break;
196
197 default:
198 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
199 break;
200 }
201}
202
203static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
204 pxa2xx_cm_read,
205 pxa2xx_cm_read,
206 pxa2xx_cm_read,
207};
208
209static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
210 pxa2xx_cm_write,
211 pxa2xx_cm_write,
212 pxa2xx_cm_write,
213};
214
aa941b94
AZ		 215static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
216{
217 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
218 int i;
219
220 for (i = 0; i < 4; i ++)
221 qemu_put_be32s(f, &s->cm_regs[i]);
222 qemu_put_be32s(f, &s->clkcfg);
223 qemu_put_be32s(f, &s->pmnc);
224}
225
226static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
227{
228 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
229 int i;
230
231 for (i = 0; i < 4; i ++)
232 qemu_get_be32s(f, &s->cm_regs[i]);
233 qemu_get_be32s(f, &s->clkcfg);
234 qemu_get_be32s(f, &s->pmnc);
235
236 return 0;
237}
238
c1713132
AZ		 239static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
240{
241 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
242
243 switch (reg) {
244 case 6: /* Clock Configuration register */
245 return s->clkcfg;
246
247 case 7: /* Power Mode register */
248 return 0;
249
250 default:
251 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
252 break;
253 }
254 return 0;
255}
256
257static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
258 uint32_t value)
259{
260 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
261 static const char *pwrmode[8] = {
262 "Normal", "Idle", "Deep-idle", "Standby",
263 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
264 };
265
266 switch (reg) {
267 case 6: /* Clock Configuration register */
268 s->clkcfg = value & 0xf;
269 if (value & 2)
270 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
271 break;
272
273 case 7: /* Power Mode register */
274 if (value & 8)
275 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
276 switch (value & 7) {
277 case 0:
278 /* Do nothing */
279 break;
280
281 case 1:
282 /* Idle */
82d17978 283 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
c1713132
AZ		 284 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
285 break;
286 }
287 /* Fall through. */
288
289 case 2:
290 /* Deep-Idle */
291 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
292 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
293 goto message;
294
295 case 3:
a90b7318
AZ		 296 s->env->uncached_cpsr =
297 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
c1713132
AZ		 298 s->env->cp15.c1_sys = 0;
299 s->env->cp15.c1_coproc = 0;
ce819861 300 s->env->cp15.c2_base = 0;
c1713132
AZ		 301 s->env->cp15.c3 = 0;
302 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
303 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
304
305 /*
306 * The scratch-pad register is almost universally used
307 * for storing the return address on suspend. For the
308 * lack of a resuming bootloader, perform a jump
309 * directly to that address.
310 */
311 memset(s->env->regs, 0, 4 * 15);
312 s->env->regs[15] = s->pm_regs[PSPR >> 2];
313
314#if 0
315 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
316 cpu_physical_memory_write(0, &buffer, 4);
317 buffer = s->pm_regs[PSPR >> 2];
318 cpu_physical_memory_write(8, &buffer, 4);
319#endif
320
321 /* Suspend */
322 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
323
324 goto message;
325
326 default:
327 message:
328 printf("%s: machine entered %s mode\n", __FUNCTION__,
329 pwrmode[value & 7]);
330 }
331 break;
332
333 default:
334 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
335 break;
336 }
337}
338
339/* Performace Monitoring Registers */
340#define CPPMNC 0 /* Performance Monitor Control register */
341#define CPCCNT 1 /* Clock Counter register */
342#define CPINTEN 4 /* Interrupt Enable register */
343#define CPFLAG 5 /* Overflow Flag register */
344#define CPEVTSEL 8 /* Event Selection register */
345
346#define CPPMN0 0 /* Performance Count register 0 */
347#define CPPMN1 1 /* Performance Count register 1 */
348#define CPPMN2 2 /* Performance Count register 2 */
349#define CPPMN3 3 /* Performance Count register 3 */
350
351static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
352{
353 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
354
355 switch (reg) {
356 case CPPMNC:
357 return s->pmnc;
358 case CPCCNT:
359 if (s->pmnc & 1)
360 return qemu_get_clock(vm_clock);
361 else
362 return 0;
363 case CPINTEN:
364 case CPFLAG:
365 case CPEVTSEL:
366 return 0;
367
368 default:
369 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
370 break;
371 }
372 return 0;
373}
374
375static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
376 uint32_t value)
377{
378 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
379
380 switch (reg) {
381 case CPPMNC:
382 s->pmnc = value;
383 break;
384
385 case CPCCNT:
386 case CPINTEN:
387 case CPFLAG:
388 case CPEVTSEL:
389 break;
390
391 default:
392 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
393 break;
394 }
395}
396
397static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
398{
399 switch (crm) {
400 case 0:
401 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
402 case 1:
403 return pxa2xx_perf_read(opaque, op2, reg, crm);
404 case 2:
405 switch (reg) {
406 case CPPMN0:
407 case CPPMN1:
408 case CPPMN2:
409 case CPPMN3:
410 return 0;
411 }
412 /* Fall through */
413 default:
414 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
415 break;
416 }
417 return 0;
418}
419
420static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
421 uint32_t value)
422{
423 switch (crm) {
424 case 0:
425 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
426 break;
427 case 1:
428 pxa2xx_perf_write(opaque, op2, reg, crm, value);
429 break;
430 case 2:
431 switch (reg) {
432 case CPPMN0:
433 case CPPMN1:
434 case CPPMN2:
435 case CPPMN3:
436 return;
437 }
438 /* Fall through */
439 default:
440 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
441 break;
442 }
443}
444
445#define MDCNFG 0x00 /* SDRAM Configuration register */
446#define MDREFR 0x04 /* SDRAM Refresh Control register */
447#define MSC0 0x08 /* Static Memory Control register 0 */
448#define MSC1 0x0c /* Static Memory Control register 1 */
449#define MSC2 0x10 /* Static Memory Control register 2 */
450#define MECR 0x14 /* Expansion Memory Bus Config register */
451#define SXCNFG 0x1c /* Synchronous Static Memory Config register */
452#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
453#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
454#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
455#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
456#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
457#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
458#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
459#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
460#define ARB_CNTL 0x48 /* Arbiter Control register */
461#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
462#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
463#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
464#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
465#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
466#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
467#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
468
469static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
470{
471 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
472 addr -= s->mm_base;
473
474 switch (addr) {
475 case MDCNFG ... SA1110:
476 if ((addr & 3) == 0)
477 return s->mm_regs[addr >> 2];
478
479 default:
480 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
481 break;
482 }
483 return 0;
484}
485
486static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
487 uint32_t value)
488{
489 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
490 addr -= s->mm_base;
491
492 switch (addr) {
493 case MDCNFG ... SA1110:
494 if ((addr & 3) == 0) {
495 s->mm_regs[addr >> 2] = value;
496 break;
497 }
498
499 default:
500 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
501 break;
502 }
503}
504
505static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
506 pxa2xx_mm_read,
507 pxa2xx_mm_read,
508 pxa2xx_mm_read,
509};
510
511static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
512 pxa2xx_mm_write,
513 pxa2xx_mm_write,
514 pxa2xx_mm_write,
515};
516
aa941b94
AZ		 517static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
518{
519 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
520 int i;
521
522 for (i = 0; i < 0x1a; i ++)
523 qemu_put_be32s(f, &s->mm_regs[i]);
524}
525
526static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
527{
528 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
529 int i;
530
531 for (i = 0; i < 0x1a; i ++)
532 qemu_get_be32s(f, &s->mm_regs[i]);
533
534 return 0;
535}
536
c1713132
AZ		 537/* Synchronous Serial Ports */
538struct pxa2xx_ssp_s {
539 target_phys_addr_t base;
540 qemu_irq irq;
541 int enable;
542
543 uint32_t sscr[2];
544 uint32_t sspsp;
545 uint32_t ssto;
546 uint32_t ssitr;
547 uint32_t sssr;
548 uint8_t sstsa;
549 uint8_t ssrsa;
550 uint8_t ssacd;
551
552 uint32_t rx_fifo[16];
553 int rx_level;
554 int rx_start;
555
556 uint32_t (*readfn)(void *opaque);
557 void (*writefn)(void *opaque, uint32_t value);
558 void *opaque;
559};
560
561#define SSCR0 0x00 /* SSP Control register 0 */
562#define SSCR1 0x04 /* SSP Control register 1 */
563#define SSSR 0x08 /* SSP Status register */
564#define SSITR 0x0c /* SSP Interrupt Test register */
565#define SSDR 0x10 /* SSP Data register */
566#define SSTO 0x28 /* SSP Time-Out register */
567#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
568#define SSTSA 0x30 /* SSP TX Time Slot Active register */
569#define SSRSA 0x34 /* SSP RX Time Slot Active register */
570#define SSTSS 0x38 /* SSP Time Slot Status register */
571#define SSACD 0x3c /* SSP Audio Clock Divider register */
572
573/* Bitfields for above registers */
574#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
575#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
576#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
577#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
578#define SSCR0_SSE (1 << 7)
579#define SSCR0_RIM (1 << 22)
580#define SSCR0_TIM (1 << 23)
581#define SSCR0_MOD (1 << 31)
582#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
583#define SSCR1_RIE (1 << 0)
584#define SSCR1_TIE (1 << 1)
585#define SSCR1_LBM (1 << 2)
586#define SSCR1_MWDS (1 << 5)
587#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
588#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
589#define SSCR1_EFWR (1 << 14)
590#define SSCR1_PINTE (1 << 18)
591#define SSCR1_TINTE (1 << 19)
592#define SSCR1_RSRE (1 << 20)
593#define SSCR1_TSRE (1 << 21)
594#define SSCR1_EBCEI (1 << 29)
595#define SSITR_INT (7 << 5)
596#define SSSR_TNF (1 << 2)
597#define SSSR_RNE (1 << 3)
598#define SSSR_TFS (1 << 5)
599#define SSSR_RFS (1 << 6)
600#define SSSR_ROR (1 << 7)
601#define SSSR_PINT (1 << 18)
602#define SSSR_TINT (1 << 19)
603#define SSSR_EOC (1 << 20)
604#define SSSR_TUR (1 << 21)
605#define SSSR_BCE (1 << 23)
606#define SSSR_RW 0x00bc0080
607
608static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
609{
610 int level = 0;
611
612 level |= s->ssitr & SSITR_INT;
613 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
614 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
615 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
616 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
617 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
618 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
619 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
620 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
621 qemu_set_irq(s->irq, !!level);
622}
623
624static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
625{
626 s->sssr &= ~(0xf << 12); /* Clear RFL */
627 s->sssr &= ~(0xf << 8); /* Clear TFL */
628 s->sssr &= ~SSSR_TNF;
629 if (s->enable) {
630 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
631 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
632 s->sssr |= SSSR_RFS;
633 else
634 s->sssr &= ~SSSR_RFS;
635 if (0 <= SSCR1_TFT(s->sscr[1]))
636 s->sssr |= SSSR_TFS;
637 else
638 s->sssr &= ~SSSR_TFS;
639 if (s->rx_level)
640 s->sssr |= SSSR_RNE;
641 else
642 s->sssr &= ~SSSR_RNE;
643 s->sssr |= SSSR_TNF;
644 }
645
646 pxa2xx_ssp_int_update(s);
647}
648
649static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
650{
651 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
652 uint32_t retval;
653 addr -= s->base;
654
655 switch (addr) {
656 case SSCR0:
657 return s->sscr[0];
658 case SSCR1:
659 return s->sscr[1];
660 case SSPSP:
661 return s->sspsp;
662 case SSTO:
663 return s->ssto;
664 case SSITR:
665 return s->ssitr;
666 case SSSR:
667 return s->sssr | s->ssitr;
668 case SSDR:
669 if (!s->enable)
670 return 0xffffffff;
671 if (s->rx_level < 1) {
672 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
673 return 0xffffffff;
674 }
675 s->rx_level --;
676 retval = s->rx_fifo[s->rx_start ++];
677 s->rx_start &= 0xf;
678 pxa2xx_ssp_fifo_update(s);
679 return retval;
680 case SSTSA:
681 return s->sstsa;
682 case SSRSA:
683 return s->ssrsa;
684 case SSTSS:
685 return 0;
686 case SSACD:
687 return s->ssacd;
688 default:
689 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
690 break;
691 }
692 return 0;
693}
694
695static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
696 uint32_t value)
697{
698 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
699 addr -= s->base;
700
701 switch (addr) {
702 case SSCR0:
703 s->sscr[0] = value & 0xc7ffffff;
704 s->enable = value & SSCR0_SSE;
705 if (value & SSCR0_MOD)
706 printf("%s: Attempt to use network mode\n", __FUNCTION__);
707 if (s->enable && SSCR0_DSS(value) < 4)
708 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
709 SSCR0_DSS(value));
710 if (!(value & SSCR0_SSE)) {
711 s->sssr = 0;
712 s->ssitr = 0;
713 s->rx_level = 0;
714 }
715 pxa2xx_ssp_fifo_update(s);
716 break;
717
718 case SSCR1:
719 s->sscr[1] = value;
720 if (value & (SSCR1_LBM | SSCR1_EFWR))
721 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
722 pxa2xx_ssp_fifo_update(s);
723 break;
724
725 case SSPSP:
726 s->sspsp = value;
727 break;
728
729 case SSTO:
730 s->ssto = value;
731 break;
732
733 case SSITR:
734 s->ssitr = value & SSITR_INT;
735 pxa2xx_ssp_int_update(s);
736 break;
737
738 case SSSR:
739 s->sssr &= ~(value & SSSR_RW);
740 pxa2xx_ssp_int_update(s);
741 break;
742
743 case SSDR:
744 if (SSCR0_UWIRE(s->sscr[0])) {
745 if (s->sscr[1] & SSCR1_MWDS)
746 value &= 0xffff;
747 else
748 value &= 0xff;
749 } else
750 /* Note how 32bits overflow does no harm here */
751 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
752
753 /* Data goes from here to the Tx FIFO and is shifted out from
754 * there directly to the slave, no need to buffer it.
755 */
756 if (s->enable) {
757 if (s->writefn)
758 s->writefn(s->opaque, value);
759
760 if (s->rx_level < 0x10) {
761 if (s->readfn)
762 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
763 s->readfn(s->opaque);
764 else
765 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
766 } else
767 s->sssr |= SSSR_ROR;
768 }
769 pxa2xx_ssp_fifo_update(s);
770 break;
771
772 case SSTSA:
773 s->sstsa = value;
774 break;
775
776 case SSRSA:
777 s->ssrsa = value;
778 break;
779
780 case SSACD:
781 s->ssacd = value;
782 break;
783
784 default:
785 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
786 break;
787 }
788}
789
790void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
791 uint32_t (*readfn)(void *opaque),
792 void (*writefn)(void *opaque, uint32_t value), void *opaque)
793{
794 if (!port) {
795 printf("%s: no such SSP\n", __FUNCTION__);
796 exit(-1);
797 }
798
799 port->opaque = opaque;
800 port->readfn = readfn;
801 port->writefn = writefn;
802}
803
804static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
805 pxa2xx_ssp_read,
806 pxa2xx_ssp_read,
807 pxa2xx_ssp_read,
808};
809
810static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
811 pxa2xx_ssp_write,
812 pxa2xx_ssp_write,
813 pxa2xx_ssp_write,
814};
815
aa941b94
AZ		 816static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
817{
818 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
819 int i;
820
821 qemu_put_be32(f, s->enable);
822
823 qemu_put_be32s(f, &s->sscr[0]);
824 qemu_put_be32s(f, &s->sscr[1]);
825 qemu_put_be32s(f, &s->sspsp);
826 qemu_put_be32s(f, &s->ssto);
827 qemu_put_be32s(f, &s->ssitr);
828 qemu_put_be32s(f, &s->sssr);
829 qemu_put_8s(f, &s->sstsa);
830 qemu_put_8s(f, &s->ssrsa);
831 qemu_put_8s(f, &s->ssacd);
832
833 qemu_put_byte(f, s->rx_level);
834 for (i = 0; i < s->rx_level; i ++)
835 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
836}
837
838static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
839{
840 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
841 int i;
842
843 s->enable = qemu_get_be32(f);
844
845 qemu_get_be32s(f, &s->sscr[0]);
846 qemu_get_be32s(f, &s->sscr[1]);
847 qemu_get_be32s(f, &s->sspsp);
848 qemu_get_be32s(f, &s->ssto);
849 qemu_get_be32s(f, &s->ssitr);
850 qemu_get_be32s(f, &s->sssr);
851 qemu_get_8s(f, &s->sstsa);
852 qemu_get_8s(f, &s->ssrsa);
853 qemu_get_8s(f, &s->ssacd);
854
855 s->rx_level = qemu_get_byte(f);
856 s->rx_start = 0;
857 for (i = 0; i < s->rx_level; i ++)
858 s->rx_fifo[i] = qemu_get_byte(f);
859
860 return 0;
861}
862
c1713132
AZ		 863/* Real-Time Clock */
864#define RCNR 0x00 /* RTC Counter register */
865#define RTAR 0x04 /* RTC Alarm register */
866#define RTSR 0x08 /* RTC Status register */
867#define RTTR 0x0c /* RTC Timer Trim register */
868#define RDCR 0x10 /* RTC Day Counter register */
869#define RYCR 0x14 /* RTC Year Counter register */
870#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
871#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
872#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
873#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
874#define SWCR 0x28 /* RTC Stopwatch Counter register */
875#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
876#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
877#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
878#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
879
880static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
881{
882 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
883}
884
885static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
886{
887 int64_t rt = qemu_get_clock(rt_clock);
888 s->last_rcnr += ((rt - s->last_hz) << 15) /
889 (1000 * ((s->rttr & 0xffff) + 1));
890 s->last_rdcr += ((rt - s->last_hz) << 15) /
891 (1000 * ((s->rttr & 0xffff) + 1));
892 s->last_hz = rt;
893}
894
895static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
896{
897 int64_t rt = qemu_get_clock(rt_clock);
898 if (s->rtsr & (1 << 12))
899 s->last_swcr += (rt - s->last_sw) / 10;
900 s->last_sw = rt;
901}
902
903static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
904{
905 int64_t rt = qemu_get_clock(rt_clock);
906 if (s->rtsr & (1 << 15))
907 s->last_swcr += rt - s->last_pi;
908 s->last_pi = rt;
909}
910
911static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
912 uint32_t rtsr)
913{
914 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
915 qemu_mod_timer(s->rtc_hz, s->last_hz +
916 (((s->rtar - s->last_rcnr) * 1000 *
917 ((s->rttr & 0xffff) + 1)) >> 15));
918 else
919 qemu_del_timer(s->rtc_hz);
920
921 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
922 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
923 (((s->rdar1 - s->last_rdcr) * 1000 *
924 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
925 else
926 qemu_del_timer(s->rtc_rdal1);
927
928 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
929 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
930 (((s->rdar2 - s->last_rdcr) * 1000 *
931 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
932 else
933 qemu_del_timer(s->rtc_rdal2);
934
935 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
936 qemu_mod_timer(s->rtc_swal1, s->last_sw +
937 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
938 else
939 qemu_del_timer(s->rtc_swal1);
940
941 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
942 qemu_mod_timer(s->rtc_swal2, s->last_sw +
943 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
944 else
945 qemu_del_timer(s->rtc_swal2);
946
947 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
948 qemu_mod_timer(s->rtc_pi, s->last_pi +
949 (s->piar & 0xffff) - s->last_rtcpicr);
950 else
951 qemu_del_timer(s->rtc_pi);
952}
953
954static inline void pxa2xx_rtc_hz_tick(void *opaque)
955{
956 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
957 s->rtsr |= (1 << 0);
958 pxa2xx_rtc_alarm_update(s, s->rtsr);
959 pxa2xx_rtc_int_update(s);
960}
961
962static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
963{
964 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
965 s->rtsr |= (1 << 4);
966 pxa2xx_rtc_alarm_update(s, s->rtsr);
967 pxa2xx_rtc_int_update(s);
968}
969
970static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
971{
972 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
973 s->rtsr |= (1 << 6);
974 pxa2xx_rtc_alarm_update(s, s->rtsr);
975 pxa2xx_rtc_int_update(s);
976}
977
978static inline void pxa2xx_rtc_swal1_tick(void *opaque)
979{
980 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
981 s->rtsr |= (1 << 8);
982 pxa2xx_rtc_alarm_update(s, s->rtsr);
983 pxa2xx_rtc_int_update(s);
984}
985
986static inline void pxa2xx_rtc_swal2_tick(void *opaque)
987{
988 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
989 s->rtsr |= (1 << 10);
990 pxa2xx_rtc_alarm_update(s, s->rtsr);
991 pxa2xx_rtc_int_update(s);
992}
993
994static inline void pxa2xx_rtc_pi_tick(void *opaque)
995{
996 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
997 s->rtsr |= (1 << 13);
998 pxa2xx_rtc_piupdate(s);
999 s->last_rtcpicr = 0;
1000 pxa2xx_rtc_alarm_update(s, s->rtsr);
1001 pxa2xx_rtc_int_update(s);
1002}
1003
1004static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1005{
1006 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1007 addr -= s->rtc_base;
1008
1009 switch (addr) {
1010 case RTTR:
1011 return s->rttr;
1012 case RTSR:
1013 return s->rtsr;
1014 case RTAR:
1015 return s->rtar;
1016 case RDAR1:
1017 return s->rdar1;
1018 case RDAR2:
1019 return s->rdar2;
1020 case RYAR1:
1021 return s->ryar1;
1022 case RYAR2:
1023 return s->ryar2;
1024 case SWAR1:
1025 return s->swar1;
1026 case SWAR2:
1027 return s->swar2;
1028 case PIAR:
1029 return s->piar;
1030 case RCNR:
1031 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1032 (1000 * ((s->rttr & 0xffff) + 1));
1033 case RDCR:
1034 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1035 (1000 * ((s->rttr & 0xffff) + 1));
1036 case RYCR:
1037 return s->last_rycr;
1038 case SWCR:
1039 if (s->rtsr & (1 << 12))
1040 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1041 else
1042 return s->last_swcr;
1043 default:
1044 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1045 break;
1046 }
1047 return 0;
1048}
1049
1050static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1051 uint32_t value)
1052{
1053 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1054 addr -= s->rtc_base;
1055
1056 switch (addr) {
1057 case RTTR:
1058 if (!(s->rttr & (1 << 31))) {
1059 pxa2xx_rtc_hzupdate(s);
1060 s->rttr = value;
1061 pxa2xx_rtc_alarm_update(s, s->rtsr);
1062 }
1063 break;
1064
1065 case RTSR:
1066 if ((s->rtsr ^ value) & (1 << 15))
1067 pxa2xx_rtc_piupdate(s);
1068
1069 if ((s->rtsr ^ value) & (1 << 12))
1070 pxa2xx_rtc_swupdate(s);
1071
1072 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1073 pxa2xx_rtc_alarm_update(s, value);
1074
1075 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1076 pxa2xx_rtc_int_update(s);
1077 break;
1078
1079 case RTAR:
1080 s->rtar = value;
1081 pxa2xx_rtc_alarm_update(s, s->rtsr);
1082 break;
1083
1084 case RDAR1:
1085 s->rdar1 = value;
1086 pxa2xx_rtc_alarm_update(s, s->rtsr);
1087 break;
1088
1089 case RDAR2:
1090 s->rdar2 = value;
1091 pxa2xx_rtc_alarm_update(s, s->rtsr);
1092 break;
1093
1094 case RYAR1:
1095 s->ryar1 = value;
1096 pxa2xx_rtc_alarm_update(s, s->rtsr);
1097 break;
1098
1099 case RYAR2:
1100 s->ryar2 = value;
1101 pxa2xx_rtc_alarm_update(s, s->rtsr);
1102 break;
1103
1104 case SWAR1:
1105 pxa2xx_rtc_swupdate(s);
1106 s->swar1 = value;
1107 s->last_swcr = 0;
1108 pxa2xx_rtc_alarm_update(s, s->rtsr);
1109 break;
1110
1111 case SWAR2:
1112 s->swar2 = value;
1113 pxa2xx_rtc_alarm_update(s, s->rtsr);
1114 break;
1115
1116 case PIAR:
1117 s->piar = value;
1118 pxa2xx_rtc_alarm_update(s, s->rtsr);
1119 break;
1120
1121 case RCNR:
1122 pxa2xx_rtc_hzupdate(s);
1123 s->last_rcnr = value;
1124 pxa2xx_rtc_alarm_update(s, s->rtsr);
1125 break;
1126
1127 case RDCR:
1128 pxa2xx_rtc_hzupdate(s);
1129 s->last_rdcr = value;
1130 pxa2xx_rtc_alarm_update(s, s->rtsr);
1131 break;
1132
1133 case RYCR:
1134 s->last_rycr = value;
1135 break;
1136
1137 case SWCR:
1138 pxa2xx_rtc_swupdate(s);
1139 s->last_swcr = value;
1140 pxa2xx_rtc_alarm_update(s, s->rtsr);
1141 break;
1142
1143 case RTCPICR:
1144 pxa2xx_rtc_piupdate(s);
1145 s->last_rtcpicr = value & 0xffff;
1146 pxa2xx_rtc_alarm_update(s, s->rtsr);
1147 break;
1148
1149 default:
1150 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1151 }
1152}
1153
aa941b94
AZ		 1154static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1155 pxa2xx_rtc_read,
1156 pxa2xx_rtc_read,
1157 pxa2xx_rtc_read,
1158};
1159
1160static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1161 pxa2xx_rtc_write,
1162 pxa2xx_rtc_write,
1163 pxa2xx_rtc_write,
1164};
1165
1166static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
c1713132
AZ		 1167{
1168 struct tm *tm;
1169 time_t ti;
1170 int wom;
1171
1172 s->rttr = 0x7fff;
1173 s->rtsr = 0;
1174
1175 time(&ti);
1176 if (rtc_utc)
1177 tm = gmtime(&ti);
1178 else
1179 tm = localtime(&ti);
1180 wom = ((tm->tm_mday - 1) / 7) + 1;
1181
1182 s->last_rcnr = (uint32_t) ti;
1183 s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) |
1184 (tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec;
1185 s->last_rycr = ((tm->tm_year + 1900) << 9) |
1186 ((tm->tm_mon + 1) << 5) | tm->tm_mday;
1187 s->last_swcr = (tm->tm_hour << 19) |
1188 (tm->tm_min << 13) | (tm->tm_sec << 7);
1189 s->last_rtcpicr = 0;
1190 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1191
1192 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1193 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1194 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1195 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1196 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1197 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1198}
1199
aa941b94
AZ		 1200static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1201{
1202 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132 1203
aa941b94
AZ		 1204 pxa2xx_rtc_hzupdate(s);
1205 pxa2xx_rtc_piupdate(s);
1206 pxa2xx_rtc_swupdate(s);
1207
1208 qemu_put_be32s(f, &s->rttr);
1209 qemu_put_be32s(f, &s->rtsr);
1210 qemu_put_be32s(f, &s->rtar);
1211 qemu_put_be32s(f, &s->rdar1);
1212 qemu_put_be32s(f, &s->rdar2);
1213 qemu_put_be32s(f, &s->ryar1);
1214 qemu_put_be32s(f, &s->ryar2);
1215 qemu_put_be32s(f, &s->swar1);
1216 qemu_put_be32s(f, &s->swar2);
1217 qemu_put_be32s(f, &s->piar);
1218 qemu_put_be32s(f, &s->last_rcnr);
1219 qemu_put_be32s(f, &s->last_rdcr);
1220 qemu_put_be32s(f, &s->last_rycr);
1221 qemu_put_be32s(f, &s->last_swcr);
1222 qemu_put_be32s(f, &s->last_rtcpicr);
1223 qemu_put_be64s(f, &s->last_hz);
1224 qemu_put_be64s(f, &s->last_sw);
1225 qemu_put_be64s(f, &s->last_pi);
1226}
1227
1228static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1229{
1230 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1231
1232 qemu_get_be32s(f, &s->rttr);
1233 qemu_get_be32s(f, &s->rtsr);
1234 qemu_get_be32s(f, &s->rtar);
1235 qemu_get_be32s(f, &s->rdar1);
1236 qemu_get_be32s(f, &s->rdar2);
1237 qemu_get_be32s(f, &s->ryar1);
1238 qemu_get_be32s(f, &s->ryar2);
1239 qemu_get_be32s(f, &s->swar1);
1240 qemu_get_be32s(f, &s->swar2);
1241 qemu_get_be32s(f, &s->piar);
1242 qemu_get_be32s(f, &s->last_rcnr);
1243 qemu_get_be32s(f, &s->last_rdcr);
1244 qemu_get_be32s(f, &s->last_rycr);
1245 qemu_get_be32s(f, &s->last_swcr);
1246 qemu_get_be32s(f, &s->last_rtcpicr);
1247 qemu_get_be64s(f, &s->last_hz);
1248 qemu_get_be64s(f, &s->last_sw);
1249 qemu_get_be64s(f, &s->last_pi);
1250
1251 pxa2xx_rtc_alarm_update(s, s->rtsr);
1252
1253 return 0;
1254}
c1713132 1255
3f582262
AZ		 1256/* I2C Interface */
1257struct pxa2xx_i2c_s {
1258 i2c_slave slave;
1259 i2c_bus *bus;
1260 target_phys_addr_t base;
1261 qemu_irq irq;
1262
1263 uint16_t control;
1264 uint16_t status;
1265 uint8_t ibmr;
1266 uint8_t data;
1267};
1268
1269#define IBMR 0x80 /* I2C Bus Monitor register */
1270#define IDBR 0x88 /* I2C Data Buffer register */
1271#define ICR 0x90 /* I2C Control register */
1272#define ISR 0x98 /* I2C Status register */
1273#define ISAR 0xa0 /* I2C Slave Address register */
1274
1275static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
1276{
1277 uint16_t level = 0;
1278 level |= s->status & s->control & (1 << 10); /* BED */
1279 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1280 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1281 level |= s->status & (1 << 9); /* SAD */
1282 qemu_set_irq(s->irq, !!level);
1283}
1284
1285/* These are only stubs now. */
1286static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1287{
1288 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1289
1290 switch (event) {
1291 case I2C_START_SEND:
1292 s->status |= (1 << 9); /* set SAD */
1293 s->status &= ~(1 << 0); /* clear RWM */
1294 break;
1295 case I2C_START_RECV:
1296 s->status |= (1 << 9); /* set SAD */
1297 s->status |= 1 << 0; /* set RWM */
1298 break;
1299 case I2C_FINISH:
1300 s->status |= (1 << 4); /* set SSD */
1301 break;
1302 case I2C_NACK:
1303 s->status |= 1 << 1; /* set ACKNAK */
1304 break;
1305 }
1306 pxa2xx_i2c_update(s);
1307}
1308
1309static int pxa2xx_i2c_rx(i2c_slave *i2c)
1310{
1311 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1312 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1313 return 0;
1314
1315 if (s->status & (1 << 0)) { /* RWM */
1316 s->status |= 1 << 6; /* set ITE */
1317 }
1318 pxa2xx_i2c_update(s);
1319
1320 return s->data;
1321}
1322
1323static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1324{
1325 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1326 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1327 return 1;
1328
1329 if (!(s->status & (1 << 0))) { /* RWM */
1330 s->status |= 1 << 7; /* set IRF */
1331 s->data = data;
1332 }
1333 pxa2xx_i2c_update(s);
1334
1335 return 1;
1336}
1337
1338static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1339{
1340 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1341 addr -= s->base;
1342
1343 switch (addr) {
1344 case ICR:
1345 return s->control;
1346 case ISR:
1347 return s->status | (i2c_bus_busy(s->bus) << 2);
1348 case ISAR:
1349 return s->slave.address;
1350 case IDBR:
1351 return s->data;
1352 case IBMR:
1353 if (s->status & (1 << 2))
1354 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1355 else
1356 s->ibmr = 0;
1357 return s->ibmr;
1358 default:
1359 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1360 break;
1361 }
1362 return 0;
1363}
1364
1365static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1366 uint32_t value)
1367{
1368 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1369 int ack;
1370 addr -= s->base;
1371
1372 switch (addr) {
1373 case ICR:
1374 s->control = value & 0xfff7;
1375 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1376 /* TODO: slave mode */
1377 if (value & (1 << 0)) { /* START condition */
1378 if (s->data & 1)
1379 s->status |= 1 << 0; /* set RWM */
1380 else
1381 s->status &= ~(1 << 0); /* clear RWM */
1382 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1383 } else {
1384 if (s->status & (1 << 0)) { /* RWM */
1385 s->data = i2c_recv(s->bus);
1386 if (value & (1 << 2)) /* ACKNAK */
1387 i2c_nack(s->bus);
1388 ack = 1;
1389 } else
1390 ack = !i2c_send(s->bus, s->data);
1391 }
1392
1393 if (value & (1 << 1)) /* STOP condition */
1394 i2c_end_transfer(s->bus);
1395
1396 if (ack) {
1397 if (value & (1 << 0)) /* START condition */
1398 s->status |= 1 << 6; /* set ITE */
1399 else
1400 if (s->status & (1 << 0)) /* RWM */
1401 s->status |= 1 << 7; /* set IRF */
1402 else
1403 s->status |= 1 << 6; /* set ITE */
1404 s->status &= ~(1 << 1); /* clear ACKNAK */
1405 } else {
1406 s->status |= 1 << 6; /* set ITE */
1407 s->status |= 1 << 10; /* set BED */
1408 s->status |= 1 << 1; /* set ACKNAK */
1409 }
1410 }
1411 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1412 if (value & (1 << 4)) /* MA */
1413 i2c_end_transfer(s->bus);
1414 pxa2xx_i2c_update(s);
1415 break;
1416
1417 case ISR:
1418 s->status &= ~(value & 0x07f0);
1419 pxa2xx_i2c_update(s);
1420 break;
1421
1422 case ISAR:
1423 i2c_set_slave_address(&s->slave, value & 0x7f);
1424 break;
1425
1426 case IDBR:
1427 s->data = value & 0xff;
1428 break;
1429
1430 default:
1431 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1432 }
1433}
1434
1435static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
1436 pxa2xx_i2c_read,
1437 pxa2xx_i2c_read,
1438 pxa2xx_i2c_read,
1439};
1440
1441static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1442 pxa2xx_i2c_write,
1443 pxa2xx_i2c_write,
1444 pxa2xx_i2c_write,
1445};
1446
aa941b94
AZ		 1447static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1448{
1449 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1450
1451 qemu_put_be16s(f, &s->control);
1452 qemu_put_be16s(f, &s->status);
1453 qemu_put_8s(f, &s->ibmr);
1454 qemu_put_8s(f, &s->data);
1455
1456 i2c_bus_save(f, s->bus);
1457 i2c_slave_save(f, &s->slave);
1458}
1459
1460static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1461{
1462 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1463
1464 qemu_get_be16s(f, &s->control);
1465 qemu_get_be16s(f, &s->status);
1466 qemu_get_8s(f, &s->ibmr);
1467 qemu_get_8s(f, &s->data);
1468
1469 i2c_bus_load(f, s->bus);
1470 i2c_slave_load(f, &s->slave);
1471 return 0;
1472}
1473
3f582262 1474struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929 1475 qemu_irq irq, uint32_t page_size)
3f582262
AZ		 1476{
1477 int iomemtype;
1478 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
3f6c925f 1479 i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
3f582262
AZ		 1480
1481 s->base = base;
1482 s->irq = irq;
1483 s->slave.event = pxa2xx_i2c_event;
1484 s->slave.recv = pxa2xx_i2c_rx;
1485 s->slave.send = pxa2xx_i2c_tx;
1486 s->bus = i2c_init_bus();
1487
2a163929
AZ		 1488 iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
1489 pxa2xx_i2c_writefn, s);
1490 cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
3f582262 1491
aa941b94
AZ		 1492 register_savevm("pxa2xx_i2c", base, 0,
1493 pxa2xx_i2c_save, pxa2xx_i2c_load, s);
1494
3f582262
AZ		 1495 return s;
1496}
1497
1498i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
1499{
1500 return s->bus;
1501}
1502
c1713132
AZ		 1503/* PXA Inter-IC Sound Controller */
1504static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1505{
1506 i2s->rx_len = 0;
1507 i2s->tx_len = 0;
1508 i2s->fifo_len = 0;
1509 i2s->clk = 0x1a;
1510 i2s->control[0] = 0x00;
1511 i2s->control[1] = 0x00;
1512 i2s->status = 0x00;
1513 i2s->mask = 0x00;
1514}
1515
1516#define SACR_TFTH(val) ((val >> 8) & 0xf)
1517#define SACR_RFTH(val) ((val >> 12) & 0xf)
1518#define SACR_DREC(val) (val & (1 << 3))
1519#define SACR_DPRL(val) (val & (1 << 4))
1520
1521static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1522{
1523 int rfs, tfs;
1524 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1525 !SACR_DREC(i2s->control[1]);
1526 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1527 i2s->enable && !SACR_DPRL(i2s->control[1]);
1528
1529 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1530 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1531
1532 i2s->status &= 0xe0;
1533 if (i2s->rx_len)
1534 i2s->status |= 1 << 1; /* RNE */
1535 if (i2s->enable)
1536 i2s->status |= 1 << 2; /* BSY */
1537 if (tfs)
1538 i2s->status |= 1 << 3; /* TFS */
1539 if (rfs)
1540 i2s->status |= 1 << 4; /* RFS */
1541 if (!(i2s->tx_len && i2s->enable))
1542 i2s->status |= i2s->fifo_len << 8; /* TFL */
1543 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1544
1545 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1546}
1547
1548#define SACR0 0x00 /* Serial Audio Global Control register */
1549#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1550#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1551#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1552#define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1553#define SADIV 0x60 /* Serial Audio Clock Divider register */
1554#define SADR 0x80 /* Serial Audio Data register */
1555
1556static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1557{
1558 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1559 addr -= s->base;
1560
1561 switch (addr) {
1562 case SACR0:
1563 return s->control[0];
1564 case SACR1:
1565 return s->control[1];
1566 case SASR0:
1567 return s->status;
1568 case SAIMR:
1569 return s->mask;
1570 case SAICR:
1571 return 0;
1572 case SADIV:
1573 return s->clk;
1574 case SADR:
1575 if (s->rx_len > 0) {
1576 s->rx_len --;
1577 pxa2xx_i2s_update(s);
1578 return s->codec_in(s->opaque);
1579 }
1580 return 0;
1581 default:
1582 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1583 break;
1584 }
1585 return 0;
1586}
1587
1588static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1589 uint32_t value)
1590{
1591 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1592 uint32_t *sample;
1593 addr -= s->base;
1594
1595 switch (addr) {
1596 case SACR0:
1597 if (value & (1 << 3)) /* RST */
1598 pxa2xx_i2s_reset(s);
1599 s->control[0] = value & 0xff3d;
1600 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1601 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1602 s->codec_out(s->opaque, *sample);
1603 s->status &= ~(1 << 7); /* I2SOFF */
1604 }
1605 if (value & (1 << 4)) /* EFWR */
1606 printf("%s: Attempt to use special function\n", __FUNCTION__);
1607 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1608 pxa2xx_i2s_update(s);
1609 break;
1610 case SACR1:
1611 s->control[1] = value & 0x0039;
1612 if (value & (1 << 5)) /* ENLBF */
1613 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1614 if (value & (1 << 4)) /* DPRL */
1615 s->fifo_len = 0;
1616 pxa2xx_i2s_update(s);
1617 break;
1618 case SAIMR:
1619 s->mask = value & 0x0078;
1620 pxa2xx_i2s_update(s);
1621 break;
1622 case SAICR:
1623 s->status &= ~(value & (3 << 5));
1624 pxa2xx_i2s_update(s);
1625 break;
1626 case SADIV:
1627 s->clk = value & 0x007f;
1628 break;
1629 case SADR:
1630 if (s->tx_len && s->enable) {
1631 s->tx_len --;
1632 pxa2xx_i2s_update(s);
1633 s->codec_out(s->opaque, value);
1634 } else if (s->fifo_len < 16) {
1635 s->fifo[s->fifo_len ++] = value;
1636 pxa2xx_i2s_update(s);
1637 }
1638 break;
1639 default:
1640 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1641 }
1642}
1643
1644static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1645 pxa2xx_i2s_read,
1646 pxa2xx_i2s_read,
1647 pxa2xx_i2s_read,
1648};
1649
1650static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1651 pxa2xx_i2s_write,
1652 pxa2xx_i2s_write,
1653 pxa2xx_i2s_write,
1654};
1655
aa941b94
AZ		 1656static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1657{
1658 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1659
1660 qemu_put_be32s(f, &s->control[0]);
1661 qemu_put_be32s(f, &s->control[1]);
1662 qemu_put_be32s(f, &s->status);
1663 qemu_put_be32s(f, &s->mask);
1664 qemu_put_be32s(f, &s->clk);
1665
1666 qemu_put_be32(f, s->enable);
1667 qemu_put_be32(f, s->rx_len);
1668 qemu_put_be32(f, s->tx_len);
1669 qemu_put_be32(f, s->fifo_len);
1670}
1671
1672static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1673{
1674 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1675
1676 qemu_get_be32s(f, &s->control[0]);
1677 qemu_get_be32s(f, &s->control[1]);
1678 qemu_get_be32s(f, &s->status);
1679 qemu_get_be32s(f, &s->mask);
1680 qemu_get_be32s(f, &s->clk);
1681
1682 s->enable = qemu_get_be32(f);
1683 s->rx_len = qemu_get_be32(f);
1684 s->tx_len = qemu_get_be32(f);
1685 s->fifo_len = qemu_get_be32(f);
1686
1687 return 0;
1688}
1689
c1713132
AZ		 1690static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1691{
1692 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1693 uint32_t *sample;
1694
1695 /* Signal FIFO errors */
1696 if (s->enable && s->tx_len)
1697 s->status |= 1 << 5; /* TUR */
1698 if (s->enable && s->rx_len)
1699 s->status |= 1 << 6; /* ROR */
1700
1701 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1702 * handle the cases where it makes a difference. */
1703 s->tx_len = tx - s->fifo_len;
1704 s->rx_len = rx;
1705 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1706 if (s->enable)
1707 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1708 s->codec_out(s->opaque, *sample);
1709 pxa2xx_i2s_update(s);
1710}
1711
1712static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1713 qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1714{
1715 int iomemtype;
1716 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1717 qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1718
1719 s->base = base;
1720 s->irq = irq;
1721 s->dma = dma;
1722 s->data_req = pxa2xx_i2s_data_req;
1723
1724 pxa2xx_i2s_reset(s);
1725
1726 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1727 pxa2xx_i2s_writefn, s);
187337f8 1728 cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
c1713132 1729
aa941b94
AZ		 1730 register_savevm("pxa2xx_i2s", base, 0,
1731 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1732
c1713132
AZ		 1733 return s;
1734}
1735
1736/* PXA Fast Infra-red Communications Port */
1737struct pxa2xx_fir_s {
1738 target_phys_addr_t base;
1739 qemu_irq irq;
1740 struct pxa2xx_dma_state_s *dma;
1741 int enable;
1742 CharDriverState *chr;
1743
1744 uint8_t control[3];
1745 uint8_t status[2];
1746
1747 int rx_len;
1748 int rx_start;
1749 uint8_t rx_fifo[64];
1750};
1751
1752static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1753{
1754 s->control[0] = 0x00;
1755 s->control[1] = 0x00;
1756 s->control[2] = 0x00;
1757 s->status[0] = 0x00;
1758 s->status[1] = 0x00;
1759 s->enable = 0;
1760}
1761
1762static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1763{
1764 static const int tresh[4] = { 8, 16, 32, 0 };
1765 int intr = 0;
1766 if ((s->control[0] & (1 << 4)) && /* RXE */
1767 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1768 s->status[0] |= 1 << 4; /* RFS */
1769 else
1770 s->status[0] &= ~(1 << 4); /* RFS */
1771 if (s->control[0] & (1 << 3)) /* TXE */
1772 s->status[0] |= 1 << 3; /* TFS */
1773 else
1774 s->status[0] &= ~(1 << 3); /* TFS */
1775 if (s->rx_len)
1776 s->status[1] |= 1 << 2; /* RNE */
1777 else
1778 s->status[1] &= ~(1 << 2); /* RNE */
1779 if (s->control[0] & (1 << 4)) /* RXE */
1780 s->status[1] |= 1 << 0; /* RSY */
1781 else
1782 s->status[1] &= ~(1 << 0); /* RSY */
1783
1784 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1785 (s->status[0] & (1 << 4)); /* RFS */
1786 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1787 (s->status[0] & (1 << 3)); /* TFS */
1788 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1789 (s->status[0] & (1 << 6)); /* EOC */
1790 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1791 (s->status[0] & (1 << 1)); /* TUR */
1792 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1793
1794 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1795 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1796
1797 qemu_set_irq(s->irq, intr && s->enable);
1798}
1799
1800#define ICCR0 0x00 /* FICP Control register 0 */
1801#define ICCR1 0x04 /* FICP Control register 1 */
1802#define ICCR2 0x08 /* FICP Control register 2 */
1803#define ICDR 0x0c /* FICP Data register */
1804#define ICSR0 0x14 /* FICP Status register 0 */
1805#define ICSR1 0x18 /* FICP Status register 1 */
1806#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1807
1808static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1809{
1810 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1811 uint8_t ret;
1812 addr -= s->base;
1813
1814 switch (addr) {
1815 case ICCR0:
1816 return s->control[0];
1817 case ICCR1:
1818 return s->control[1];
1819 case ICCR2:
1820 return s->control[2];
1821 case ICDR:
1822 s->status[0] &= ~0x01;
1823 s->status[1] &= ~0x72;
1824 if (s->rx_len) {
1825 s->rx_len --;
1826 ret = s->rx_fifo[s->rx_start ++];
1827 s->rx_start &= 63;
1828 pxa2xx_fir_update(s);
1829 return ret;
1830 }
1831 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1832 break;
1833 case ICSR0:
1834 return s->status[0];
1835 case ICSR1:
1836 return s->status[1] | (1 << 3); /* TNF */
1837 case ICFOR:
1838 return s->rx_len;
1839 default:
1840 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1841 break;
1842 }
1843 return 0;
1844}
1845
1846static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1847 uint32_t value)
1848{
1849 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1850 uint8_t ch;
1851 addr -= s->base;
1852
1853 switch (addr) {
1854 case ICCR0:
1855 s->control[0] = value;
1856 if (!(value & (1 << 4))) /* RXE */
1857 s->rx_len = s->rx_start = 0;
1858 if (!(value & (1 << 3))) /* TXE */
1859 /* Nop */;
1860 s->enable = value & 1; /* ITR */
1861 if (!s->enable)
1862 s->status[0] = 0;
1863 pxa2xx_fir_update(s);
1864 break;
1865 case ICCR1:
1866 s->control[1] = value;
1867 break;
1868 case ICCR2:
1869 s->control[2] = value & 0x3f;
1870 pxa2xx_fir_update(s);
1871 break;
1872 case ICDR:
1873 if (s->control[2] & (1 << 2)) /* TXP */
1874 ch = value;
1875 else
1876 ch = ~value;
1877 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1878 qemu_chr_write(s->chr, &ch, 1);
1879 break;
1880 case ICSR0:
1881 s->status[0] &= ~(value & 0x66);
1882 pxa2xx_fir_update(s);
1883 break;
1884 case ICFOR:
1885 break;
1886 default:
1887 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1888 }
1889}
1890
1891static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1892 pxa2xx_fir_read,
1893 pxa2xx_fir_read,
1894 pxa2xx_fir_read,
1895};
1896
1897static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1898 pxa2xx_fir_write,
1899 pxa2xx_fir_write,
1900 pxa2xx_fir_write,
1901};
1902
1903static int pxa2xx_fir_is_empty(void *opaque)
1904{
1905 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1906 return (s->rx_len < 64);
1907}
1908
1909static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1910{
1911 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1912 if (!(s->control[0] & (1 << 4))) /* RXE */
1913 return;
1914
1915 while (size --) {
1916 s->status[1] |= 1 << 4; /* EOF */
1917 if (s->rx_len >= 64) {
1918 s->status[1] |= 1 << 6; /* ROR */
1919 break;
1920 }
1921
1922 if (s->control[2] & (1 << 3)) /* RXP */
1923 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1924 else
1925 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1926 }
1927
1928 pxa2xx_fir_update(s);
1929}
1930
1931static void pxa2xx_fir_event(void *opaque, int event)
1932{
1933}
1934
aa941b94
AZ		 1935static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1936{
1937 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1938 int i;
1939
1940 qemu_put_be32(f, s->enable);
1941
1942 qemu_put_8s(f, &s->control[0]);
1943 qemu_put_8s(f, &s->control[1]);
1944 qemu_put_8s(f, &s->control[2]);
1945 qemu_put_8s(f, &s->status[0]);
1946 qemu_put_8s(f, &s->status[1]);
1947
1948 qemu_put_byte(f, s->rx_len);
1949 for (i = 0; i < s->rx_len; i ++)
1950 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1951}
1952
1953static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1954{
1955 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1956 int i;
1957
1958 s->enable = qemu_get_be32(f);
1959
1960 qemu_get_8s(f, &s->control[0]);
1961 qemu_get_8s(f, &s->control[1]);
1962 qemu_get_8s(f, &s->control[2]);
1963 qemu_get_8s(f, &s->status[0]);
1964 qemu_get_8s(f, &s->status[1]);
1965
1966 s->rx_len = qemu_get_byte(f);
1967 s->rx_start = 0;
1968 for (i = 0; i < s->rx_len; i ++)
1969 s->rx_fifo[i] = qemu_get_byte(f);
1970
1971 return 0;
1972}
1973
c1713132
AZ		 1974static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1975 qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1976 CharDriverState *chr)
1977{
1978 int iomemtype;
1979 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1980 qemu_mallocz(sizeof(struct pxa2xx_fir_s));
1981
1982 s->base = base;
1983 s->irq = irq;
1984 s->dma = dma;
1985 s->chr = chr;
1986
1987 pxa2xx_fir_reset(s);
1988
1989 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
1990 pxa2xx_fir_writefn, s);
187337f8 1991 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
c1713132
AZ		 1992
1993 if (chr)
1994 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
1995 pxa2xx_fir_rx, pxa2xx_fir_event, s);
1996
aa941b94
AZ		 1997 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
1998
c1713132
AZ		 1999 return s;
2000}
2001
2002void pxa2xx_reset(int line, int level, void *opaque)
2003{
2004 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
2005 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2006 cpu_reset(s->env);
2007 /* TODO: reset peripherals */
2008 }
2009}
2010
2011/* Initialise a PXA270 integrated chip (ARM based core). */
d95b2f8d
AZ		 2012struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2013 DisplayState *ds, const char *revision)
c1713132
AZ		 2014{
2015 struct pxa2xx_state_s *s;
2016 struct pxa2xx_ssp_s *ssp;
c1713132
AZ		 2017 int iomemtype, i;
2018 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2019
4207117c
AZ		 2020 if (revision && strncmp(revision, "pxa27", 5)) {
2021 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2022 exit(1);
2023 }
2024
c1713132 2025 s->env = cpu_init();
4207117c 2026 cpu_arm_set_model(s->env, revision ?: "pxa270");
aa941b94 2027 register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
c1713132 2028
d95b2f8d
AZ		 2029 /* SDRAM & Internal Memory Storage */
2030 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2031 sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2032 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2033 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
2034
c1713132
AZ		 2035 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2036
2037 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2038
a171fe39 2039 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
3f582262 2040 s->pic[PXA27X_PIC_OST_4_11]);
a171fe39 2041
c1713132
AZ		 2042 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2043
a171fe39
AZ		 2044 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
2045
c1713132
AZ		 2046 for (i = 0; pxa270_serial[i].io_base; i ++)
2047 if (serial_hds[i])
2048 serial_mm_init(pxa270_serial[i].io_base, 2,
2049 s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
2050 else
2051 break;
2052 if (serial_hds[i])
2053 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2054 s->dma, serial_hds[i]);
2055
a171fe39
AZ		 2056 if (ds)
2057 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2058
c1713132 2059 s->cm_base = 0x41300000;
82d17978 2060 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
c1713132
AZ		 2061 s->clkcfg = 0x00000009; /* Turbo mode active */
2062 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2063 pxa2xx_cm_writefn, s);
187337f8 2064 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
aa941b94 2065 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
c1713132
AZ		 2066
2067 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2068
2069 s->mm_base = 0x48000000;
2070 s->mm_regs[MDMRS >> 2] = 0x00020002;
2071 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2072 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2073 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2074 pxa2xx_mm_writefn, s);
187337f8 2075 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
aa941b94 2076 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
c1713132 2077
2a163929
AZ		 2078 s->pm_base = 0x40f00000;
2079 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2080 pxa2xx_pm_writefn, s);
187337f8 2081 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2a163929
AZ		 2082 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2083
c1713132
AZ		 2084 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2085 s->ssp = (struct pxa2xx_ssp_s **)
2086 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2087 ssp = (struct pxa2xx_ssp_s *)
2088 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2089 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2090 s->ssp[i] = &ssp[i];
2091 ssp[i].base = pxa27x_ssp[i].io_base;
2092 ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
2093
2094 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2095 pxa2xx_ssp_writefn, &ssp[i]);
187337f8 2096 cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
aa941b94
AZ		 2097 register_savevm("pxa2xx_ssp", i, 0,
2098 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
c1713132
AZ		 2099 }
2100
a171fe39
AZ		 2101 if (usb_enabled) {
2102 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2103 }
2104
2105 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2106 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2107
c1713132
AZ		 2108 s->rtc_base = 0x40900000;
2109 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2110 pxa2xx_rtc_writefn, s);
187337f8 2111 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
aa941b94
AZ		 2112 pxa2xx_rtc_init(s);
2113 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
c1713132 2114
2a163929
AZ		 2115 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2116 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
c1713132
AZ		 2117
2118 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2119
2120 /* GPIO1 resets the processor */
fe8f096b 2121 /* The handler can be overridden by board-specific code */
c1713132
AZ		 2122 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
2123 return s;
2124}
2125
2126/* Initialise a PXA255 integrated chip (ARM based core). */
d95b2f8d
AZ		 2127struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2128 DisplayState *ds)
c1713132
AZ		 2129{
2130 struct pxa2xx_state_s *s;
2131 struct pxa2xx_ssp_s *ssp;
2132 int iomemtype, i;
2133 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2134
2135 s->env = cpu_init();
2136 cpu_arm_set_model(s->env, "pxa255");
aa941b94 2137 register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
c1713132 2138
d95b2f8d 2139 /* SDRAM & Internal Memory Storage */
a07dec22
AZ		 2140 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2141 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2142 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2143 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
d95b2f8d 2144
c1713132
AZ		 2145 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2146
2147 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2148
3f582262 2149 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
a171fe39 2150
3bdd58a4 2151 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
c1713132 2152
a171fe39
AZ		 2153 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
2154
c1713132
AZ		 2155 for (i = 0; pxa255_serial[i].io_base; i ++)
2156 if (serial_hds[i])
2157 serial_mm_init(pxa255_serial[i].io_base, 2,
2158 s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
2159 else
2160 break;
2161 if (serial_hds[i])
2162 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2163 s->dma, serial_hds[i]);
2164
a171fe39
AZ		 2165 if (ds)
2166 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2167
c1713132 2168 s->cm_base = 0x41300000;
82d17978 2169 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
c1713132
AZ		 2170 s->clkcfg = 0x00000009; /* Turbo mode active */
2171 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2172 pxa2xx_cm_writefn, s);
187337f8 2173 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
aa941b94 2174 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
c1713132
AZ		 2175
2176 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2177
2178 s->mm_base = 0x48000000;
2179 s->mm_regs[MDMRS >> 2] = 0x00020002;
2180 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2181 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2182 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2183 pxa2xx_mm_writefn, s);
187337f8 2184 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
aa941b94 2185 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
c1713132 2186
2a163929
AZ		 2187 s->pm_base = 0x40f00000;
2188 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2189 pxa2xx_pm_writefn, s);
187337f8 2190 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2a163929
AZ		 2191 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2192
c1713132
AZ		 2193 for (i = 0; pxa255_ssp[i].io_base; i ++);
2194 s->ssp = (struct pxa2xx_ssp_s **)
2195 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2196 ssp = (struct pxa2xx_ssp_s *)
2197 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2198 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2199 s->ssp[i] = &ssp[i];
2200 ssp[i].base = pxa255_ssp[i].io_base;
2201 ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
2202
2203 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2204 pxa2xx_ssp_writefn, &ssp[i]);
187337f8 2205 cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
aa941b94
AZ		 2206 register_savevm("pxa2xx_ssp", i, 0,
2207 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
c1713132
AZ		 2208 }
2209
a171fe39
AZ		 2210 if (usb_enabled) {
2211 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2212 }
2213
2214 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2215 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2216
c1713132
AZ		 2217 s->rtc_base = 0x40900000;
2218 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2219 pxa2xx_rtc_writefn, s);
187337f8 2220 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
aa941b94
AZ		 2221 pxa2xx_rtc_init(s);
2222 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
c1713132 2223
2a163929
AZ		 2224 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2225 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
c1713132
AZ		 2226
2227 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2228
2229 /* GPIO1 resets the processor */
fe8f096b 2230 /* The handler can be overridden by board-specific code */
c1713132
AZ		 2231 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
2232 return s;
2233}
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