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isa: always use provided ISA bus when creating an isa device
[mirror_qemu.git] / hw / pxa2xx_lcd.c
CommitLineData
a171fe39
AZ		 1/*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "console.h"
12#include "pxa.h"
e27f01ef 13#include "pixel_ops.h"
87ecb68b
PB		 14/* FIXME: For graphic_rotate. Should probably be done in common code. */
15#include "sysemu.h"
714fa308 16#include "framebuffer.h"
a171fe39 17
2b7251e0
JQ		 18struct DMAChannel {
19 target_phys_addr_t branch;
46995409 20 uint8_t up;
2b7251e0
JQ		 21 uint8_t palette[1024];
22 uint8_t pbuffer[1024];
23 void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
24 int *miny, int *maxy);
25
26 target_phys_addr_t descriptor;
27 target_phys_addr_t source;
28 uint32_t id;
29 uint32_t command;
30};
31
bc24a225 32struct PXA2xxLCDState {
5a6fdd91 33 MemoryRegion iomem;
a171fe39
AZ		 34 qemu_irq irq;
35 int irqlevel;
36
37 int invalidated;
38 DisplayState *ds;
39 drawfn *line_fn[2];
40 int dest_width;
41 int xres, yres;
42 int pal_for;
43 int transp;
44 enum {
45 pxa_lcdc_2bpp = 1,
46 pxa_lcdc_4bpp = 2,
47 pxa_lcdc_8bpp = 3,
48 pxa_lcdc_16bpp = 4,
49 pxa_lcdc_18bpp = 5,
50 pxa_lcdc_18pbpp = 6,
51 pxa_lcdc_19bpp = 7,
52 pxa_lcdc_19pbpp = 8,
53 pxa_lcdc_24bpp = 9,
54 pxa_lcdc_25bpp = 10,
55 } bpp;
56
57 uint32_t control[6];
58 uint32_t status[2];
59 uint32_t ovl1c[2];
60 uint32_t ovl2c[2];
61 uint32_t ccr;
62 uint32_t cmdcr;
63 uint32_t trgbr;
64 uint32_t tcr;
65 uint32_t liidr;
66 uint8_t bscntr;
67
2b7251e0 68 struct DMAChannel dma_ch[7];
a171fe39 69
38641a52 70 qemu_irq vsync_cb;
a171fe39
AZ		 71 int orientation;
72};
73
541dc0d4 74typedef struct QEMU_PACKED {
a171fe39
AZ		 75 uint32_t fdaddr;
76 uint32_t fsaddr;
77 uint32_t fidr;
78 uint32_t ldcmd;
bc24a225 79} PXAFrameDescriptor;
a171fe39
AZ		 80
81#define LCCR0 0x000 /* LCD Controller Control register 0 */
82#define LCCR1 0x004 /* LCD Controller Control register 1 */
83#define LCCR2 0x008 /* LCD Controller Control register 2 */
84#define LCCR3 0x00c /* LCD Controller Control register 3 */
85#define LCCR4 0x010 /* LCD Controller Control register 4 */
86#define LCCR5 0x014 /* LCD Controller Control register 5 */
87
88#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
89#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
90#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
91#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
92#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
93#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
94#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
95
96#define LCSR1 0x034 /* LCD Controller Status register 1 */
97#define LCSR0 0x038 /* LCD Controller Status register 0 */
98#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
99
100#define TRGBR 0x040 /* TMED RGB Seed register */
101#define TCR 0x044 /* TMED Control register */
102
103#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
104#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
105#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
106#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
107#define CCR 0x090 /* Cursor Control register */
108
109#define CMDCR 0x100 /* Command Control register */
110#define PRSR 0x104 /* Panel Read Status register */
111
112#define PXA_LCDDMA_CHANS 7
113#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
114#define DMA_FSADR 0x04 /* Frame Source Address register */
115#define DMA_FIDR 0x08 /* Frame ID register */
116#define DMA_LDCMD 0x0c /* Command register */
117
118/* LCD Buffer Strength Control register */
119#define BSCNTR 0x04000054
120
121/* Bitfield masks */
122#define LCCR0_ENB (1 << 0)
123#define LCCR0_CMS (1 << 1)
124#define LCCR0_SDS (1 << 2)
125#define LCCR0_LDM (1 << 3)
126#define LCCR0_SOFM0 (1 << 4)
127#define LCCR0_IUM (1 << 5)
128#define LCCR0_EOFM0 (1 << 6)
129#define LCCR0_PAS (1 << 7)
130#define LCCR0_DPD (1 << 9)
131#define LCCR0_DIS (1 << 10)
132#define LCCR0_QDM (1 << 11)
133#define LCCR0_PDD (0xff << 12)
134#define LCCR0_BSM0 (1 << 20)
135#define LCCR0_OUM (1 << 21)
136#define LCCR0_LCDT (1 << 22)
137#define LCCR0_RDSTM (1 << 23)
138#define LCCR0_CMDIM (1 << 24)
139#define LCCR0_OUC (1 << 25)
140#define LCCR0_LDDALT (1 << 26)
141#define LCCR1_PPL(x) ((x) & 0x3ff)
142#define LCCR2_LPP(x) ((x) & 0x3ff)
143#define LCCR3_API (15 << 16)
144#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
145#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
146#define LCCR4_K1(x) (((x) >> 0) & 7)
147#define LCCR4_K2(x) (((x) >> 3) & 7)
148#define LCCR4_K3(x) (((x) >> 6) & 7)
149#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
150#define LCCR5_SOFM(ch) (1 << (ch - 1))
151#define LCCR5_EOFM(ch) (1 << (ch + 7))
152#define LCCR5_BSM(ch) (1 << (ch + 15))
153#define LCCR5_IUM(ch) (1 << (ch + 23))
154#define OVLC1_EN (1 << 31)
155#define CCR_CEN (1 << 31)
156#define FBR_BRA (1 << 0)
157#define FBR_BINT (1 << 1)
158#define FBR_SRCADDR (0xfffffff << 4)
159#define LCSR0_LDD (1 << 0)
160#define LCSR0_SOF0 (1 << 1)
161#define LCSR0_BER (1 << 2)
162#define LCSR0_ABC (1 << 3)
163#define LCSR0_IU0 (1 << 4)
164#define LCSR0_IU1 (1 << 5)
165#define LCSR0_OU (1 << 6)
166#define LCSR0_QD (1 << 7)
167#define LCSR0_EOF0 (1 << 8)
168#define LCSR0_BS0 (1 << 9)
169#define LCSR0_SINT (1 << 10)
170#define LCSR0_RDST (1 << 11)
171#define LCSR0_CMDINT (1 << 12)
172#define LCSR0_BERCH(x) (((x) & 7) << 28)
173#define LCSR1_SOF(ch) (1 << (ch - 1))
174#define LCSR1_EOF(ch) (1 << (ch + 7))
175#define LCSR1_BS(ch) (1 << (ch + 15))
176#define LCSR1_IU(ch) (1 << (ch + 23))
177#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
178#define LDCMD_EOFINT (1 << 21)
179#define LDCMD_SOFINT (1 << 22)
180#define LDCMD_PAL (1 << 26)
181
182/* Route internal interrupt lines to the global IC */
bc24a225 183static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
a171fe39
AZ		 184{
185 int level = 0;
186 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
187 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
188 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
189 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
190 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
191 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
192 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
193 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
194 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
195 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
196 level |= (s->status[1] & ~s->control[5]);
197
198 qemu_set_irq(s->irq, !!level);
199 s->irqlevel = level;
200}
201
202/* Set Branch Status interrupt high and poke associated registers */
bc24a225 203static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 204{
205 int unmasked;
206 if (ch == 0) {
207 s->status[0] |= LCSR0_BS0;
208 unmasked = !(s->control[0] & LCCR0_BSM0);
209 } else {
210 s->status[1] |= LCSR1_BS(ch);
211 unmasked = !(s->control[5] & LCCR5_BSM(ch));
212 }
213
214 if (unmasked) {
215 if (s->irqlevel)
216 s->status[0] |= LCSR0_SINT;
217 else
218 s->liidr = s->dma_ch[ch].id;
219 }
220}
221
222/* Set Start Of Frame Status interrupt high and poke associated registers */
bc24a225 223static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 224{
225 int unmasked;
226 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
227 return;
228
229 if (ch == 0) {
230 s->status[0] |= LCSR0_SOF0;
231 unmasked = !(s->control[0] & LCCR0_SOFM0);
232 } else {
233 s->status[1] |= LCSR1_SOF(ch);
234 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
235 }
236
237 if (unmasked) {
238 if (s->irqlevel)
239 s->status[0] |= LCSR0_SINT;
240 else
241 s->liidr = s->dma_ch[ch].id;
242 }
243}
244
245/* Set End Of Frame Status interrupt high and poke associated registers */
bc24a225 246static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 247{
248 int unmasked;
249 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
250 return;
251
252 if (ch == 0) {
253 s->status[0] |= LCSR0_EOF0;
254 unmasked = !(s->control[0] & LCCR0_EOFM0);
255 } else {
256 s->status[1] |= LCSR1_EOF(ch);
257 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
258 }
259
260 if (unmasked) {
261 if (s->irqlevel)
262 s->status[0] |= LCSR0_SINT;
263 else
264 s->liidr = s->dma_ch[ch].id;
265 }
266}
267
268/* Set Bus Error Status interrupt high and poke associated registers */
bc24a225 269static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 270{
271 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
272 if (s->irqlevel)
273 s->status[0] |= LCSR0_SINT;
274 else
275 s->liidr = s->dma_ch[ch].id;
276}
277
278/* Set Read Status interrupt high and poke associated registers */
bc24a225 279static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
a171fe39
AZ		 280{
281 s->status[0] |= LCSR0_RDST;
282 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
283 s->status[0] |= LCSR0_SINT;
284}
285
286/* Load new Frame Descriptors from DMA */
bc24a225 287static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
a171fe39 288{
bc24a225 289 PXAFrameDescriptor desc;
c227f099 290 target_phys_addr_t descptr;
a171fe39
AZ		 291 int i;
292
293 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
a171fe39
AZ		 294 s->dma_ch[i].source = 0;
295
296 if (!s->dma_ch[i].up)
297 continue;
298
299 if (s->dma_ch[i].branch & FBR_BRA) {
300 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
301 if (s->dma_ch[i].branch & FBR_BINT)
302 pxa2xx_dma_bs_set(s, i);
303 s->dma_ch[i].branch &= ~FBR_BRA;
304 } else
305 descptr = s->dma_ch[i].descriptor;
306
d95b2f8d 307 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
b0457b69 308 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
a171fe39
AZ		 309 continue;
310
d7585251
PB		 311 cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
312 s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
313 s->dma_ch[i].source = tswap32(desc.fsaddr);
314 s->dma_ch[i].id = tswap32(desc.fidr);
315 s->dma_ch[i].command = tswap32(desc.ldcmd);
a171fe39
AZ		 316 }
317}
318
5a6fdd91
BC		 319static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
320 unsigned size)
a171fe39 321{
bc24a225 322 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 323 int ch;
a171fe39
AZ		 324
325 switch (offset) {
326 case LCCR0:
327 return s->control[0];
328 case LCCR1:
329 return s->control[1];
330 case LCCR2:
331 return s->control[2];
332 case LCCR3:
333 return s->control[3];
334 case LCCR4:
335 return s->control[4];
336 case LCCR5:
337 return s->control[5];
338
339 case OVL1C1:
340 return s->ovl1c[0];
341 case OVL1C2:
342 return s->ovl1c[1];
343 case OVL2C1:
344 return s->ovl2c[0];
345 case OVL2C2:
346 return s->ovl2c[1];
347
348 case CCR:
349 return s->ccr;
350
351 case CMDCR:
352 return s->cmdcr;
353
354 case TRGBR:
355 return s->trgbr;
356 case TCR:
357 return s->tcr;
358
359 case 0x200 ... 0x1000: /* DMA per-channel registers */
360 ch = (offset - 0x200) >> 4;
361 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
362 goto fail;
363
364 switch (offset & 0xf) {
365 case DMA_FDADR:
366 return s->dma_ch[ch].descriptor;
367 case DMA_FSADR:
368 return s->dma_ch[ch].source;
369 case DMA_FIDR:
370 return s->dma_ch[ch].id;
371 case DMA_LDCMD:
372 return s->dma_ch[ch].command;
373 default:
374 goto fail;
375 }
376
377 case FBR0:
378 return s->dma_ch[0].branch;
379 case FBR1:
380 return s->dma_ch[1].branch;
381 case FBR2:
382 return s->dma_ch[2].branch;
383 case FBR3:
384 return s->dma_ch[3].branch;
385 case FBR4:
386 return s->dma_ch[4].branch;
387 case FBR5:
388 return s->dma_ch[5].branch;
389 case FBR6:
390 return s->dma_ch[6].branch;
391
392 case BSCNTR:
393 return s->bscntr;
394
395 case PRSR:
396 return 0;
397
398 case LCSR0:
399 return s->status[0];
400 case LCSR1:
401 return s->status[1];
402 case LIIDR:
403 return s->liidr;
404
405 default:
406 fail:
2ac71179 407 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39
AZ		 408 }
409
410 return 0;
411}
412
5a6fdd91
BC		 413static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
414 uint64_t value, unsigned size)
a171fe39 415{
bc24a225 416 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 417 int ch;
a171fe39
AZ		 418
419 switch (offset) {
420 case LCCR0:
421 /* ACK Quick Disable done */
422 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
423 s->status[0] |= LCSR0_QD;
424
425 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
426 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
427
428 if ((s->control[3] & LCCR3_API) &&
429 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
430 s->status[0] |= LCSR0_ABC;
431
432 s->control[0] = value & 0x07ffffff;
433 pxa2xx_lcdc_int_update(s);
434
435 s->dma_ch[0].up = !!(value & LCCR0_ENB);
436 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
437 break;
438
439 case LCCR1:
440 s->control[1] = value;
441 break;
442
443 case LCCR2:
444 s->control[2] = value;
445 break;
446
447 case LCCR3:
448 s->control[3] = value & 0xefffffff;
449 s->bpp = LCCR3_BPP(value);
450 break;
451
452 case LCCR4:
453 s->control[4] = value & 0x83ff81ff;
454 break;
455
456 case LCCR5:
457 s->control[5] = value & 0x3f3f3f3f;
458 break;
459
460 case OVL1C1:
461 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
462 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
463
464 s->ovl1c[0] = value & 0x80ffffff;
465 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
466 break;
467
468 case OVL1C2:
469 s->ovl1c[1] = value & 0x000fffff;
470 break;
471
472 case OVL2C1:
473 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
474 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
475
476 s->ovl2c[0] = value & 0x80ffffff;
477 s->dma_ch[2].up = !!(value & OVLC1_EN);
478 s->dma_ch[3].up = !!(value & OVLC1_EN);
479 s->dma_ch[4].up = !!(value & OVLC1_EN);
480 break;
481
482 case OVL2C2:
483 s->ovl2c[1] = value & 0x007fffff;
484 break;
485
486 case CCR:
487 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
488 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
489
490 s->ccr = value & 0x81ffffe7;
491 s->dma_ch[5].up = !!(value & CCR_CEN);
492 break;
493
494 case CMDCR:
495 s->cmdcr = value & 0xff;
496 break;
497
498 case TRGBR:
499 s->trgbr = value & 0x00ffffff;
500 break;
501
502 case TCR:
503 s->tcr = value & 0x7fff;
504 break;
505
506 case 0x200 ... 0x1000: /* DMA per-channel registers */
507 ch = (offset - 0x200) >> 4;
508 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
509 goto fail;
510
511 switch (offset & 0xf) {
512 case DMA_FDADR:
513 s->dma_ch[ch].descriptor = value & 0xfffffff0;
514 break;
515
516 default:
517 goto fail;
518 }
519 break;
520
521 case FBR0:
522 s->dma_ch[0].branch = value & 0xfffffff3;
523 break;
524 case FBR1:
525 s->dma_ch[1].branch = value & 0xfffffff3;
526 break;
527 case FBR2:
528 s->dma_ch[2].branch = value & 0xfffffff3;
529 break;
530 case FBR3:
531 s->dma_ch[3].branch = value & 0xfffffff3;
532 break;
533 case FBR4:
534 s->dma_ch[4].branch = value & 0xfffffff3;
535 break;
536 case FBR5:
537 s->dma_ch[5].branch = value & 0xfffffff3;
538 break;
539 case FBR6:
540 s->dma_ch[6].branch = value & 0xfffffff3;
541 break;
542
543 case BSCNTR:
544 s->bscntr = value & 0xf;
545 break;
546
547 case PRSR:
548 break;
549
550 case LCSR0:
551 s->status[0] &= ~(value & 0xfff);
552 if (value & LCSR0_BER)
553 s->status[0] &= ~LCSR0_BERCH(7);
554 break;
555
556 case LCSR1:
557 s->status[1] &= ~(value & 0x3e3f3f);
558 break;
559
560 default:
561 fail:
2ac71179 562 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39
AZ		 563 }
564}
565
5a6fdd91
BC		 566static const MemoryRegionOps pxa2xx_lcdc_ops = {
567 .read = pxa2xx_lcdc_read,
568 .write = pxa2xx_lcdc_write,
569 .endianness = DEVICE_NATIVE_ENDIAN,
a171fe39
AZ		 570};
571
a171fe39 572/* Load new palette for a given DMA channel, convert to internal format */
bc24a225 573static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
a171fe39
AZ		 574{
575 int i, n, format, r, g, b, alpha;
576 uint32_t *dest, *src;
577 s->pal_for = LCCR4_PALFOR(s->control[4]);
578 format = s->pal_for;
579
580 switch (bpp) {
581 case pxa_lcdc_2bpp:
582 n = 4;
583 break;
584 case pxa_lcdc_4bpp:
585 n = 16;
586 break;
587 case pxa_lcdc_8bpp:
588 n = 256;
589 break;
590 default:
591 format = 0;
592 return;
593 }
594
595 src = (uint32_t *) s->dma_ch[ch].pbuffer;
596 dest = (uint32_t *) s->dma_ch[ch].palette;
597 alpha = r = g = b = 0;
598
599 for (i = 0; i < n; i ++) {
600 switch (format) {
601 case 0: /* 16 bpp, no transparency */
602 alpha = 0;
603 if (s->control[0] & LCCR0_CMS)
604 r = g = b = *src & 0xff;
605 else {
606 r = (*src & 0xf800) >> 8;
607 g = (*src & 0x07e0) >> 3;
608 b = (*src & 0x001f) << 3;
609 }
610 break;
611 case 1: /* 16 bpp plus transparency */
612 alpha = *src & (1 << 24);
613 if (s->control[0] & LCCR0_CMS)
614 r = g = b = *src & 0xff;
615 else {
616 r = (*src & 0xf800) >> 8;
617 g = (*src & 0x07e0) >> 3;
618 b = (*src & 0x001f) << 3;
619 }
620 break;
621 case 2: /* 18 bpp plus transparency */
622 alpha = *src & (1 << 24);
623 if (s->control[0] & LCCR0_CMS)
624 r = g = b = *src & 0xff;
625 else {
626 r = (*src & 0xf80000) >> 16;
627 g = (*src & 0x00fc00) >> 8;
628 b = (*src & 0x0000f8);
629 }
630 break;
631 case 3: /* 24 bpp plus transparency */
632 alpha = *src & (1 << 24);
633 if (s->control[0] & LCCR0_CMS)
634 r = g = b = *src & 0xff;
635 else {
636 r = (*src & 0xff0000) >> 16;
637 g = (*src & 0x00ff00) >> 8;
638 b = (*src & 0x0000ff);
639 }
640 break;
641 }
0e1f5a0c 642 switch (ds_get_bits_per_pixel(s->ds)) {
a171fe39
AZ		 643 case 8:
644 *dest = rgb_to_pixel8(r, g, b) | alpha;
645 break;
646 case 15:
647 *dest = rgb_to_pixel15(r, g, b) | alpha;
648 break;
649 case 16:
650 *dest = rgb_to_pixel16(r, g, b) | alpha;
651 break;
652 case 24:
653 *dest = rgb_to_pixel24(r, g, b) | alpha;
654 break;
655 case 32:
656 *dest = rgb_to_pixel32(r, g, b) | alpha;
657 break;
658 }
659 src ++;
660 dest ++;
661 }
662}
663
9312805d 664static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
c227f099 665 target_phys_addr_t addr, int *miny, int *maxy)
a171fe39 666{
714fa308 667 int src_width, dest_width;
b9d38e95 668 drawfn fn = NULL;
a171fe39
AZ		 669 if (s->dest_width)
670 fn = s->line_fn[s->transp][s->bpp];
671 if (!fn)
672 return;
673
a171fe39
AZ		 674 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
675 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
676 src_width *= 3;
677 else if (s->bpp > pxa_lcdc_16bpp)
678 src_width *= 4;
679 else if (s->bpp > pxa_lcdc_8bpp)
680 src_width *= 2;
681
a171fe39 682 dest_width = s->xres * s->dest_width;
714fa308
PB		 683 *miny = 0;
684 framebuffer_update_display(s->ds,
685 addr, s->xres, s->yres,
686 src_width, dest_width, s->dest_width,
687 s->invalidated,
688 fn, s->dma_ch[0].palette, miny, maxy);
a171fe39
AZ		 689}
690
9312805d 691static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
c227f099 692 target_phys_addr_t addr, int *miny, int *maxy)
a171fe39 693{
714fa308 694 int src_width, dest_width;
b9d38e95 695 drawfn fn = NULL;
a171fe39
AZ		 696 if (s->dest_width)
697 fn = s->line_fn[s->transp][s->bpp];
698 if (!fn)
699 return;
700
a171fe39
AZ		 701 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
702 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
703 src_width *= 3;
704 else if (s->bpp > pxa_lcdc_16bpp)
705 src_width *= 4;
706 else if (s->bpp > pxa_lcdc_8bpp)
707 src_width *= 2;
708
709 dest_width = s->yres * s->dest_width;
714fa308
PB		 710 *miny = 0;
711 framebuffer_update_display(s->ds,
712 addr, s->xres, s->yres,
713 src_width, s->dest_width, -dest_width,
714 s->invalidated,
715 fn, s->dma_ch[0].palette,
716 miny, maxy);
a171fe39
AZ		 717}
718
9312805d
VK		 719static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
720 target_phys_addr_t addr, int *miny, int *maxy)
721{
722 int src_width, dest_width;
723 drawfn fn = NULL;
724 if (s->dest_width) {
725 fn = s->line_fn[s->transp][s->bpp];
726 }
727 if (!fn) {
728 return;
729 }
730
731 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
732 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
733 src_width *= 3;
734 } else if (s->bpp > pxa_lcdc_16bpp) {
735 src_width *= 4;
736 } else if (s->bpp > pxa_lcdc_8bpp) {
737 src_width *= 2;
738 }
739
740 dest_width = s->xres * s->dest_width;
741 *miny = 0;
742 framebuffer_update_display(s->ds,
743 addr, s->xres, s->yres,
744 src_width, -dest_width, -s->dest_width,
745 s->invalidated,
746 fn, s->dma_ch[0].palette, miny, maxy);
747}
748
749static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
750 target_phys_addr_t addr, int *miny, int *maxy)
751{
752 int src_width, dest_width;
753 drawfn fn = NULL;
754 if (s->dest_width) {
755 fn = s->line_fn[s->transp][s->bpp];
756 }
757 if (!fn) {
758 return;
759 }
760
761 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
762 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
763 src_width *= 3;
764 } else if (s->bpp > pxa_lcdc_16bpp) {
765 src_width *= 4;
766 } else if (s->bpp > pxa_lcdc_8bpp) {
767 src_width *= 2;
768 }
769
770 dest_width = s->yres * s->dest_width;
771 *miny = 0;
772 framebuffer_update_display(s->ds,
773 addr, s->xres, s->yres,
774 src_width, -s->dest_width, dest_width,
775 s->invalidated,
776 fn, s->dma_ch[0].palette,
777 miny, maxy);
778}
779
bc24a225 780static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
a171fe39
AZ		 781{
782 int width, height;
783 if (!(s->control[0] & LCCR0_ENB))
784 return;
785
786 width = LCCR1_PPL(s->control[1]) + 1;
787 height = LCCR2_LPP(s->control[2]) + 1;
788
789 if (width != s->xres || height != s->yres) {
9312805d 790 if (s->orientation == 90 || s->orientation == 270) {
3023f332 791 qemu_console_resize(s->ds, height, width);
9312805d 792 } else {
3023f332 793 qemu_console_resize(s->ds, width, height);
9312805d 794 }
a171fe39
AZ		 795 s->invalidated = 1;
796 s->xres = width;
797 s->yres = height;
798 }
799}
800
801static void pxa2xx_update_display(void *opaque)
802{
bc24a225 803 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
c227f099 804 target_phys_addr_t fbptr;
a171fe39
AZ		 805 int miny, maxy;
806 int ch;
807 if (!(s->control[0] & LCCR0_ENB))
808 return;
809
810 pxa2xx_descriptor_load(s);
811
812 pxa2xx_lcdc_resize(s);
813 miny = s->yres;
814 maxy = 0;
815 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
816 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
817 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
818 if (s->dma_ch[ch].up) {
819 if (!s->dma_ch[ch].source) {
820 pxa2xx_dma_ber_set(s, ch);
821 continue;
822 }
823 fbptr = s->dma_ch[ch].source;
d95b2f8d 824 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
b0457b69 825 fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
a171fe39
AZ		 826 pxa2xx_dma_ber_set(s, ch);
827 continue;
828 }
a171fe39
AZ		 829
830 if (s->dma_ch[ch].command & LDCMD_PAL) {
714fa308
PB		 831 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
832 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
833 sizeof(s->dma_ch[ch].pbuffer)));
a171fe39
AZ		 834 pxa2xx_palette_parse(s, ch, s->bpp);
835 } else {
836 /* Do we need to reparse palette */
837 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
838 pxa2xx_palette_parse(s, ch, s->bpp);
839
840 /* ACK frame start */
841 pxa2xx_dma_sof_set(s, ch);
842
714fa308 843 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
a171fe39
AZ		 844 s->invalidated = 0;
845
846 /* ACK frame completed */
847 pxa2xx_dma_eof_set(s, ch);
848 }
849 }
850
851 if (s->control[0] & LCCR0_DIS) {
852 /* ACK last frame completed */
853 s->control[0] &= ~LCCR0_ENB;
854 s->status[0] |= LCSR0_LDD;
855 }
856
714fa308 857 if (miny >= 0) {
9312805d
VK		 858 switch (s->orientation) {
859 case 0:
860 dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
861 break;
862 case 90:
863 dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
864 break;
865 case 180:
866 maxy = s->yres - maxy - 1;
867 miny = s->yres - miny - 1;
868 dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
869 break;
870 case 270:
871 maxy = s->yres - maxy - 1;
872 miny = s->yres - miny - 1;
873 dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
874 break;
875 }
714fa308 876 }
a171fe39
AZ		 877 pxa2xx_lcdc_int_update(s);
878
38641a52 879 qemu_irq_raise(s->vsync_cb);
a171fe39
AZ		 880}
881
882static void pxa2xx_invalidate_display(void *opaque)
883{
bc24a225 884 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39
AZ		 885 s->invalidated = 1;
886}
887
888static void pxa2xx_screen_dump(void *opaque, const char *filename)
889{
890 /* TODO */
891}
892
9596ebb7 893static void pxa2xx_lcdc_orientation(void *opaque, int angle)
a171fe39 894{
bc24a225 895 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 896
9312805d
VK		 897 switch (angle) {
898 case 0:
899 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
900 break;
901 case 90:
902 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
903 break;
904 case 180:
905 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
906 break;
907 case 270:
908 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
909 break;
a171fe39
AZ		 910 }
911
912 s->orientation = angle;
913 s->xres = s->yres = -1;
914 pxa2xx_lcdc_resize(s);
915}
916
99838363
JQ		 917static const VMStateDescription vmstate_dma_channel = {
918 .name = "dma_channel",
919 .version_id = 0,
920 .minimum_version_id = 0,
921 .minimum_version_id_old = 0,
922 .fields = (VMStateField[]) {
923 VMSTATE_UINTTL(branch, struct DMAChannel),
924 VMSTATE_UINT8(up, struct DMAChannel),
925 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
926 VMSTATE_UINTTL(descriptor, struct DMAChannel),
927 VMSTATE_UINTTL(source, struct DMAChannel),
928 VMSTATE_UINT32(id, struct DMAChannel),
929 VMSTATE_UINT32(command, struct DMAChannel),
930 VMSTATE_END_OF_LIST()
aa941b94 931 }
99838363 932};
aa941b94 933
99838363 934static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
aa941b94 935{
99838363 936 PXA2xxLCDState *s = opaque;
aa941b94
AZ		 937
938 s->bpp = LCCR3_BPP(s->control[3]);
939 s->xres = s->yres = s->pal_for = -1;
940
941 return 0;
942}
943
99838363
JQ		 944static const VMStateDescription vmstate_pxa2xx_lcdc = {
945 .name = "pxa2xx_lcdc",
946 .version_id = 0,
947 .minimum_version_id = 0,
948 .minimum_version_id_old = 0,
949 .post_load = pxa2xx_lcdc_post_load,
950 .fields = (VMStateField[]) {
951 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
952 VMSTATE_INT32(transp, PXA2xxLCDState),
953 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
954 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
955 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
956 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
957 VMSTATE_UINT32(ccr, PXA2xxLCDState),
958 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
959 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
960 VMSTATE_UINT32(tcr, PXA2xxLCDState),
961 VMSTATE_UINT32(liidr, PXA2xxLCDState),
962 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
963 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
964 vmstate_dma_channel, struct DMAChannel),
965 VMSTATE_END_OF_LIST()
966 }
967};
968
a171fe39
AZ		 969#define BITS 8
970#include "pxa2xx_template.h"
971#define BITS 15
972#include "pxa2xx_template.h"
973#define BITS 16
974#include "pxa2xx_template.h"
975#define BITS 24
976#include "pxa2xx_template.h"
977#define BITS 32
978#include "pxa2xx_template.h"
979
5a6fdd91
BC		 980PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
981 target_phys_addr_t base, qemu_irq irq)
a171fe39 982{
bc24a225 983 PXA2xxLCDState *s;
a171fe39 984
7267c094 985 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
a171fe39
AZ		 986 s->invalidated = 1;
987 s->irq = irq;
a171fe39
AZ		 988
989 pxa2xx_lcdc_orientation(s, graphic_rotate);
990
5a6fdd91
BC		 991 memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
992 "pxa2xx-lcd-controller", 0x00100000);
993 memory_region_add_subregion(sysmem, base, &s->iomem);
a171fe39 994
3023f332
AL		 995 s->ds = graphic_console_init(pxa2xx_update_display,
996 pxa2xx_invalidate_display,
997 pxa2xx_screen_dump, NULL, s);
a171fe39 998
0e1f5a0c 999 switch (ds_get_bits_per_pixel(s->ds)) {
a171fe39
AZ		 1000 case 0:
1001 s->dest_width = 0;
1002 break;
1003 case 8:
1004 s->line_fn[0] = pxa2xx_draw_fn_8;
1005 s->line_fn[1] = pxa2xx_draw_fn_8t;
1006 s->dest_width = 1;
1007 break;
1008 case 15:
1009 s->line_fn[0] = pxa2xx_draw_fn_15;
1010 s->line_fn[1] = pxa2xx_draw_fn_15t;
1011 s->dest_width = 2;
1012 break;
1013 case 16:
1014 s->line_fn[0] = pxa2xx_draw_fn_16;
1015 s->line_fn[1] = pxa2xx_draw_fn_16t;
1016 s->dest_width = 2;
1017 break;
1018 case 24:
1019 s->line_fn[0] = pxa2xx_draw_fn_24;
1020 s->line_fn[1] = pxa2xx_draw_fn_24t;
1021 s->dest_width = 3;
1022 break;
1023 case 32:
1024 s->line_fn[0] = pxa2xx_draw_fn_32;
1025 s->line_fn[1] = pxa2xx_draw_fn_32t;
1026 s->dest_width = 4;
1027 break;
1028 default:
1029 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1030 exit(1);
1031 }
aa941b94 1032
99838363 1033 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
aa941b94 1034
a171fe39
AZ		 1035 return s;
1036}
1037
bc24a225 1038void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
38641a52
AZ		 1039{
1040 s->vsync_cb = handler;
a171fe39 1041}
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