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a171fe39 AZ |
1 | /* |
2 | * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
6 | * | |
7 | * This code is licensed under the GPLv2. | |
8 | */ | |
9 | ||
10 | #include "vl.h" | |
11 | #include "sd.h" | |
12 | ||
13 | struct pxa2xx_mmci_s { | |
14 | target_phys_addr_t base; | |
15 | qemu_irq irq; | |
16 | void *dma; | |
17 | ||
18 | SDState *card; | |
19 | ||
20 | uint32_t status; | |
21 | uint32_t clkrt; | |
22 | uint32_t spi; | |
23 | uint32_t cmdat; | |
24 | uint32_t resp_tout; | |
25 | uint32_t read_tout; | |
26 | int blklen; | |
27 | int numblk; | |
28 | uint32_t intmask; | |
29 | uint32_t intreq; | |
30 | int cmd; | |
31 | uint32_t arg; | |
32 | ||
33 | int active; | |
34 | int bytesleft; | |
35 | uint8_t tx_fifo[64]; | |
36 | int tx_start; | |
37 | int tx_len; | |
38 | uint8_t rx_fifo[32]; | |
39 | int rx_start; | |
40 | int rx_len; | |
41 | uint16_t resp_fifo[9]; | |
42 | int resp_len; | |
43 | ||
44 | int cmdreq; | |
45 | int ac_width; | |
46 | }; | |
47 | ||
48 | #define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ | |
49 | #define MMC_STAT 0x04 /* MMC Status register */ | |
50 | #define MMC_CLKRT 0x08 /* MMC Clock Rate register */ | |
51 | #define MMC_SPI 0x0c /* MMC SPI Mode register */ | |
52 | #define MMC_CMDAT 0x10 /* MMC Command/Data register */ | |
53 | #define MMC_RESTO 0x14 /* MMC Response Time-Out register */ | |
54 | #define MMC_RDTO 0x18 /* MMC Read Time-Out register */ | |
55 | #define MMC_BLKLEN 0x1c /* MMC Block Length register */ | |
56 | #define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */ | |
57 | #define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */ | |
58 | #define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */ | |
59 | #define MMC_I_REG 0x2c /* MMC Interrupt Request register */ | |
60 | #define MMC_CMD 0x30 /* MMC Command register */ | |
61 | #define MMC_ARGH 0x34 /* MMC Argument High register */ | |
62 | #define MMC_ARGL 0x38 /* MMC Argument Low register */ | |
63 | #define MMC_RES 0x3c /* MMC Response FIFO */ | |
64 | #define MMC_RXFIFO 0x40 /* MMC Receive FIFO */ | |
65 | #define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */ | |
66 | #define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */ | |
67 | #define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */ | |
68 | ||
69 | /* Bitfield masks */ | |
70 | #define STRPCL_STOP_CLK (1 << 0) | |
71 | #define STRPCL_STRT_CLK (1 << 1) | |
72 | #define STAT_TOUT_RES (1 << 1) | |
73 | #define STAT_CLK_EN (1 << 8) | |
74 | #define STAT_DATA_DONE (1 << 11) | |
75 | #define STAT_PRG_DONE (1 << 12) | |
76 | #define STAT_END_CMDRES (1 << 13) | |
77 | #define SPI_SPI_MODE (1 << 0) | |
78 | #define CMDAT_RES_TYPE (3 << 0) | |
79 | #define CMDAT_DATA_EN (1 << 2) | |
80 | #define CMDAT_WR_RD (1 << 3) | |
81 | #define CMDAT_DMA_EN (1 << 7) | |
82 | #define CMDAT_STOP_TRAN (1 << 10) | |
83 | #define INT_DATA_DONE (1 << 0) | |
84 | #define INT_PRG_DONE (1 << 1) | |
85 | #define INT_END_CMD (1 << 2) | |
86 | #define INT_STOP_CMD (1 << 3) | |
87 | #define INT_CLK_OFF (1 << 4) | |
88 | #define INT_RXFIFO_REQ (1 << 5) | |
89 | #define INT_TXFIFO_REQ (1 << 6) | |
90 | #define INT_TINT (1 << 7) | |
91 | #define INT_DAT_ERR (1 << 8) | |
92 | #define INT_RES_ERR (1 << 9) | |
93 | #define INT_RD_STALLED (1 << 10) | |
94 | #define INT_SDIO_INT (1 << 11) | |
95 | #define INT_SDIO_SACK (1 << 12) | |
96 | #define PRTBUF_PRT_BUF (1 << 0) | |
97 | ||
98 | /* Route internal interrupt lines to the global IC and DMA */ | |
99 | static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s) | |
100 | { | |
101 | uint32_t mask = s->intmask; | |
102 | if (s->cmdat & CMDAT_DMA_EN) { | |
103 | mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ; | |
104 | ||
105 | pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma, | |
106 | PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ)); | |
107 | pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma, | |
108 | PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ)); | |
109 | } | |
110 | ||
111 | qemu_set_irq(s->irq, !!(s->intreq & ~mask)); | |
112 | } | |
113 | ||
114 | static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s) | |
115 | { | |
116 | if (!s->active) | |
117 | return; | |
118 | ||
119 | if (s->cmdat & CMDAT_WR_RD) { | |
120 | while (s->bytesleft && s->tx_len) { | |
121 | sd_write_data(s->card, s->tx_fifo[s->tx_start ++]); | |
122 | s->tx_start &= 0x1f; | |
123 | s->tx_len --; | |
124 | s->bytesleft --; | |
125 | } | |
126 | if (s->bytesleft) | |
127 | s->intreq |= INT_TXFIFO_REQ; | |
128 | } else | |
129 | while (s->bytesleft && s->rx_len < 32) { | |
130 | s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] = | |
131 | sd_read_data(s->card); | |
132 | s->bytesleft --; | |
133 | s->intreq |= INT_RXFIFO_REQ; | |
134 | } | |
135 | ||
136 | if (!s->bytesleft) { | |
137 | s->active = 0; | |
138 | s->intreq |= INT_DATA_DONE; | |
139 | s->status |= STAT_DATA_DONE; | |
140 | ||
141 | if (s->cmdat & CMDAT_WR_RD) { | |
142 | s->intreq |= INT_PRG_DONE; | |
143 | s->status |= STAT_PRG_DONE; | |
144 | } | |
145 | } | |
146 | ||
147 | pxa2xx_mmci_int_update(s); | |
148 | } | |
149 | ||
150 | static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s) | |
151 | { | |
152 | int rsplen, i; | |
153 | struct sd_request_s request; | |
154 | uint8_t response[16]; | |
155 | ||
156 | s->active = 1; | |
157 | s->rx_len = 0; | |
158 | s->tx_len = 0; | |
159 | s->cmdreq = 0; | |
160 | ||
161 | request.cmd = s->cmd; | |
162 | request.arg = s->arg; | |
163 | request.crc = 0; /* FIXME */ | |
164 | ||
165 | rsplen = sd_do_command(s->card, &request, response); | |
166 | s->intreq |= INT_END_CMD; | |
167 | ||
168 | memset(s->resp_fifo, 0, sizeof(s->resp_fifo)); | |
169 | switch (s->cmdat & CMDAT_RES_TYPE) { | |
170 | #define PXAMMCI_RESP(wd, value0, value1) \ | |
171 | s->resp_fifo[(wd) + 0] |= (value0); \ | |
172 | s->resp_fifo[(wd) + 1] |= (value1) << 8; | |
173 | case 0: /* No response */ | |
174 | goto complete; | |
175 | ||
176 | case 1: /* R1, R4, R5 or R6 */ | |
177 | if (rsplen < 4) | |
178 | goto timeout; | |
179 | goto complete; | |
180 | ||
181 | case 2: /* R2 */ | |
182 | if (rsplen < 16) | |
183 | goto timeout; | |
184 | goto complete; | |
185 | ||
186 | case 3: /* R3 */ | |
187 | if (rsplen < 4) | |
188 | goto timeout; | |
189 | goto complete; | |
190 | ||
191 | complete: | |
192 | for (i = 0; rsplen > 0; i ++, rsplen -= 2) { | |
193 | PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]); | |
194 | } | |
195 | s->status |= STAT_END_CMDRES; | |
196 | ||
197 | if (!(s->cmdat & CMDAT_DATA_EN)) | |
198 | s->active = 0; | |
199 | else | |
200 | s->bytesleft = s->numblk * s->blklen; | |
201 | ||
202 | s->resp_len = 0; | |
203 | break; | |
204 | ||
205 | timeout: | |
206 | s->active = 0; | |
207 | s->status |= STAT_TOUT_RES; | |
208 | break; | |
209 | } | |
210 | ||
211 | pxa2xx_mmci_fifo_update(s); | |
212 | } | |
213 | ||
214 | static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) | |
215 | { | |
216 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
217 | uint32_t ret; | |
218 | offset -= s->base; | |
219 | ||
220 | switch (offset) { | |
221 | case MMC_STRPCL: | |
222 | return 0; | |
223 | case MMC_STAT: | |
224 | return s->status; | |
225 | case MMC_CLKRT: | |
226 | return s->clkrt; | |
227 | case MMC_SPI: | |
228 | return s->spi; | |
229 | case MMC_CMDAT: | |
230 | return s->cmdat; | |
231 | case MMC_RESTO: | |
232 | return s->resp_tout; | |
233 | case MMC_RDTO: | |
234 | return s->read_tout; | |
235 | case MMC_BLKLEN: | |
236 | return s->blklen; | |
237 | case MMC_NUMBLK: | |
238 | return s->numblk; | |
239 | case MMC_PRTBUF: | |
240 | return 0; | |
241 | case MMC_I_MASK: | |
242 | return s->intmask; | |
243 | case MMC_I_REG: | |
244 | return s->intreq; | |
245 | case MMC_CMD: | |
246 | return s->cmd | 0x40; | |
247 | case MMC_ARGH: | |
248 | return s->arg >> 16; | |
249 | case MMC_ARGL: | |
250 | return s->arg & 0xffff; | |
251 | case MMC_RES: | |
252 | if (s->resp_len < 9) | |
253 | return s->resp_fifo[s->resp_len ++]; | |
254 | return 0; | |
255 | case MMC_RXFIFO: | |
256 | ret = 0; | |
257 | while (s->ac_width -- && s->rx_len) { | |
258 | ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3); | |
259 | s->rx_start &= 0x1f; | |
260 | s->rx_len --; | |
261 | } | |
262 | s->intreq &= ~INT_RXFIFO_REQ; | |
263 | pxa2xx_mmci_fifo_update(s); | |
264 | return ret; | |
265 | case MMC_RDWAIT: | |
266 | return 0; | |
267 | case MMC_BLKS_REM: | |
268 | return s->numblk; | |
269 | default: | |
270 | cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n", | |
271 | __FUNCTION__, offset); | |
272 | } | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | static void pxa2xx_mmci_write(void *opaque, | |
278 | target_phys_addr_t offset, uint32_t value) | |
279 | { | |
280 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
281 | offset -= s->base; | |
282 | ||
283 | switch (offset) { | |
284 | case MMC_STRPCL: | |
285 | if (value & STRPCL_STRT_CLK) { | |
286 | s->status |= STAT_CLK_EN; | |
287 | s->intreq &= ~INT_CLK_OFF; | |
288 | ||
289 | if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) { | |
290 | s->status &= STAT_CLK_EN; | |
291 | pxa2xx_mmci_wakequeues(s); | |
292 | } | |
293 | } | |
294 | ||
295 | if (value & STRPCL_STOP_CLK) { | |
296 | s->status &= ~STAT_CLK_EN; | |
297 | s->intreq |= INT_CLK_OFF; | |
298 | s->active = 0; | |
299 | } | |
300 | ||
301 | pxa2xx_mmci_int_update(s); | |
302 | break; | |
303 | ||
304 | case MMC_CLKRT: | |
305 | s->clkrt = value & 7; | |
306 | break; | |
307 | ||
308 | case MMC_SPI: | |
309 | s->spi = value & 0xf; | |
310 | if (value & SPI_SPI_MODE) | |
311 | printf("%s: attempted to use card in SPI mode\n", __FUNCTION__); | |
312 | break; | |
313 | ||
314 | case MMC_CMDAT: | |
315 | s->cmdat = value & 0x3dff; | |
316 | s->active = 0; | |
317 | s->cmdreq = 1; | |
318 | if (!(value & CMDAT_STOP_TRAN)) { | |
319 | s->status &= STAT_CLK_EN; | |
320 | ||
321 | if (s->status & STAT_CLK_EN) | |
322 | pxa2xx_mmci_wakequeues(s); | |
323 | } | |
324 | ||
325 | pxa2xx_mmci_int_update(s); | |
326 | break; | |
327 | ||
328 | case MMC_RESTO: | |
329 | s->resp_tout = value & 0x7f; | |
330 | break; | |
331 | ||
332 | case MMC_RDTO: | |
333 | s->read_tout = value & 0xffff; | |
334 | break; | |
335 | ||
336 | case MMC_BLKLEN: | |
337 | s->blklen = value & 0xfff; | |
338 | break; | |
339 | ||
340 | case MMC_NUMBLK: | |
341 | s->numblk = value & 0xffff; | |
342 | break; | |
343 | ||
344 | case MMC_PRTBUF: | |
345 | if (value & PRTBUF_PRT_BUF) { | |
346 | s->tx_start ^= 32; | |
347 | s->tx_len = 0; | |
348 | } | |
349 | pxa2xx_mmci_fifo_update(s); | |
350 | break; | |
351 | ||
352 | case MMC_I_MASK: | |
353 | s->intmask = value & 0x1fff; | |
354 | pxa2xx_mmci_int_update(s); | |
355 | break; | |
356 | ||
357 | case MMC_CMD: | |
358 | s->cmd = value & 0x3f; | |
359 | break; | |
360 | ||
361 | case MMC_ARGH: | |
362 | s->arg &= 0x0000ffff; | |
363 | s->arg |= value << 16; | |
364 | break; | |
365 | ||
366 | case MMC_ARGL: | |
367 | s->arg &= 0xffff0000; | |
368 | s->arg |= value & 0x0000ffff; | |
369 | break; | |
370 | ||
371 | case MMC_TXFIFO: | |
372 | while (s->ac_width -- && s->tx_len < 0x20) | |
373 | s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] = | |
374 | (value >> (s->ac_width << 3)) & 0xff; | |
375 | s->intreq &= ~INT_TXFIFO_REQ; | |
376 | pxa2xx_mmci_fifo_update(s); | |
377 | break; | |
378 | ||
379 | case MMC_RDWAIT: | |
380 | case MMC_BLKS_REM: | |
381 | break; | |
382 | ||
383 | default: | |
384 | cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n", | |
385 | __FUNCTION__, offset); | |
386 | } | |
387 | } | |
388 | ||
389 | static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset) | |
390 | { | |
391 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
392 | s->ac_width = 1; | |
393 | return pxa2xx_mmci_read(opaque, offset); | |
394 | } | |
395 | ||
396 | static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset) | |
397 | { | |
398 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
399 | s->ac_width = 2; | |
400 | return pxa2xx_mmci_read(opaque, offset); | |
401 | } | |
402 | ||
403 | static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset) | |
404 | { | |
405 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
406 | s->ac_width = 4; | |
407 | return pxa2xx_mmci_read(opaque, offset); | |
408 | } | |
409 | ||
410 | static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = { | |
411 | pxa2xx_mmci_readb, | |
412 | pxa2xx_mmci_readh, | |
413 | pxa2xx_mmci_readw | |
414 | }; | |
415 | ||
416 | static void pxa2xx_mmci_writeb(void *opaque, | |
417 | target_phys_addr_t offset, uint32_t value) | |
418 | { | |
419 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
420 | s->ac_width = 1; | |
421 | pxa2xx_mmci_write(opaque, offset, value); | |
422 | } | |
423 | ||
424 | static void pxa2xx_mmci_writeh(void *opaque, | |
425 | target_phys_addr_t offset, uint32_t value) | |
426 | { | |
427 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
428 | s->ac_width = 2; | |
429 | pxa2xx_mmci_write(opaque, offset, value); | |
430 | } | |
431 | ||
432 | static void pxa2xx_mmci_writew(void *opaque, | |
433 | target_phys_addr_t offset, uint32_t value) | |
434 | { | |
435 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
436 | s->ac_width = 4; | |
437 | pxa2xx_mmci_write(opaque, offset, value); | |
438 | } | |
439 | ||
440 | static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = { | |
441 | pxa2xx_mmci_writeb, | |
442 | pxa2xx_mmci_writeh, | |
443 | pxa2xx_mmci_writew | |
444 | }; | |
445 | ||
aa941b94 AZ |
446 | static void pxa2xx_mmci_save(QEMUFile *f, void *opaque) |
447 | { | |
448 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
449 | int i; | |
450 | ||
451 | qemu_put_be32s(f, &s->status); | |
452 | qemu_put_be32s(f, &s->clkrt); | |
453 | qemu_put_be32s(f, &s->spi); | |
454 | qemu_put_be32s(f, &s->cmdat); | |
455 | qemu_put_be32s(f, &s->resp_tout); | |
456 | qemu_put_be32s(f, &s->read_tout); | |
457 | qemu_put_be32(f, s->blklen); | |
458 | qemu_put_be32(f, s->numblk); | |
459 | qemu_put_be32s(f, &s->intmask); | |
460 | qemu_put_be32s(f, &s->intreq); | |
461 | qemu_put_be32(f, s->cmd); | |
462 | qemu_put_be32s(f, &s->arg); | |
463 | qemu_put_be32(f, s->cmdreq); | |
464 | qemu_put_be32(f, s->active); | |
465 | qemu_put_be32(f, s->bytesleft); | |
466 | ||
467 | qemu_put_byte(f, s->tx_len); | |
468 | for (i = 0; i < s->tx_len; i ++) | |
469 | qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]); | |
470 | ||
471 | qemu_put_byte(f, s->rx_len); | |
472 | for (i = 0; i < s->rx_len; i ++) | |
473 | qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]); | |
474 | ||
475 | qemu_put_byte(f, s->resp_len); | |
476 | for (i = s->resp_len; i < 9; i ++) | |
477 | qemu_put_be16s(f, &s->resp_fifo[i]); | |
478 | } | |
479 | ||
480 | static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) | |
481 | { | |
482 | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; | |
483 | int i; | |
484 | ||
485 | qemu_get_be32s(f, &s->status); | |
486 | qemu_get_be32s(f, &s->clkrt); | |
487 | qemu_get_be32s(f, &s->spi); | |
488 | qemu_get_be32s(f, &s->cmdat); | |
489 | qemu_get_be32s(f, &s->resp_tout); | |
490 | qemu_get_be32s(f, &s->read_tout); | |
491 | s->blklen = qemu_get_be32(f); | |
492 | s->numblk = qemu_get_be32(f); | |
493 | qemu_get_be32s(f, &s->intmask); | |
494 | qemu_get_be32s(f, &s->intreq); | |
495 | s->cmd = qemu_get_be32(f); | |
496 | qemu_get_be32s(f, &s->arg); | |
497 | s->cmdreq = qemu_get_be32(f); | |
498 | s->active = qemu_get_be32(f); | |
499 | s->bytesleft = qemu_get_be32(f); | |
500 | ||
501 | s->tx_len = qemu_get_byte(f); | |
502 | s->tx_start = 0; | |
503 | if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0) | |
504 | return -EINVAL; | |
505 | for (i = 0; i < s->tx_len; i ++) | |
506 | s->tx_fifo[i] = qemu_get_byte(f); | |
507 | ||
508 | s->rx_len = qemu_get_byte(f); | |
509 | s->rx_start = 0; | |
510 | if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0) | |
511 | return -EINVAL; | |
512 | for (i = 0; i < s->rx_len; i ++) | |
513 | s->rx_fifo[i] = qemu_get_byte(f); | |
514 | ||
515 | s->resp_len = qemu_get_byte(f); | |
516 | if (s->resp_len > 9 || s->resp_len < 0) | |
517 | return -EINVAL; | |
518 | for (i = s->resp_len; i < 9; i ++) | |
519 | qemu_get_be16s(f, &s->resp_fifo[i]); | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
a171fe39 AZ |
524 | struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, |
525 | qemu_irq irq, void *dma) | |
526 | { | |
527 | int iomemtype; | |
528 | struct pxa2xx_mmci_s *s; | |
529 | ||
530 | s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s)); | |
531 | s->base = base; | |
532 | s->irq = irq; | |
533 | s->dma = dma; | |
534 | ||
535 | iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn, | |
536 | pxa2xx_mmci_writefn, s); | |
187337f8 | 537 | cpu_register_physical_memory(base, 0x00100000, iomemtype); |
a171fe39 AZ |
538 | |
539 | /* Instantiate the actual storage */ | |
540 | s->card = sd_init(sd_bdrv); | |
541 | ||
aa941b94 AZ |
542 | register_savevm("pxa2xx_mmci", 0, 0, |
543 | pxa2xx_mmci_save, pxa2xx_mmci_load, s); | |
544 | ||
a171fe39 AZ |
545 | return s; |
546 | } | |
547 | ||
548 | void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque, | |
549 | void (*readonly_cb)(void *, int), | |
550 | void (*coverswitch_cb)(void *, int)) | |
551 | { | |
552 | sd_set_cb(s->card, opaque, readonly_cb, coverswitch_cb); | |
553 | } |