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a19cbfb3 GH |
1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann | |
5 | * maintained by Gerd Hoffmann <kraxel@redhat.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
a639ab04 AL |
21 | #include <zlib.h> |
22 | ||
a19cbfb3 | 23 | #include "qemu-common.h" |
1de7afc9 PB |
24 | #include "qemu/timer.h" |
25 | #include "qemu/queue.h" | |
83c9089e | 26 | #include "monitor/monitor.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
c480bb7d | 28 | #include "trace.h" |
a19cbfb3 GH |
29 | |
30 | #include "qxl.h" | |
31 | ||
0b81c478 AL |
32 | /* |
33 | * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as | |
34 | * such can be changed by the guest, so to avoid a guest trigerrable | |
0a530548 | 35 | * abort we just qxl_set_guest_bug and set the return to NULL. Still |
0b81c478 AL |
36 | * it may happen as a result of emulator bug as well. |
37 | */ | |
a19cbfb3 | 38 | #undef SPICE_RING_PROD_ITEM |
0b81c478 | 39 | #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ |
a19cbfb3 GH |
40 | typeof(r) start = r; \ |
41 | typeof(r) end = r + 1; \ | |
42 | uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ | |
43 | typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \ | |
44 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
0a530548 | 45 | qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ |
0b81c478 AL |
46 | "! %p <= %p < %p", (uint8_t *)start, \ |
47 | (uint8_t *)m_item, (uint8_t *)end); \ | |
48 | ret = NULL; \ | |
49 | } else { \ | |
50 | ret = &m_item->el; \ | |
a19cbfb3 | 51 | } \ |
a19cbfb3 GH |
52 | } |
53 | ||
54 | #undef SPICE_RING_CONS_ITEM | |
0b81c478 | 55 | #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ |
a19cbfb3 GH |
56 | typeof(r) start = r; \ |
57 | typeof(r) end = r + 1; \ | |
58 | uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ | |
59 | typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \ | |
60 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
0a530548 | 61 | qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ |
0b81c478 AL |
62 | "! %p <= %p < %p", (uint8_t *)start, \ |
63 | (uint8_t *)m_item, (uint8_t *)end); \ | |
64 | ret = NULL; \ | |
65 | } else { \ | |
66 | ret = &m_item->el; \ | |
a19cbfb3 | 67 | } \ |
a19cbfb3 GH |
68 | } |
69 | ||
70 | #undef ALIGN | |
71 | #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) | |
72 | ||
73 | #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" | |
74 | ||
75 | #define QXL_MODE(_x, _y, _b, _o) \ | |
76 | { .x_res = _x, \ | |
77 | .y_res = _y, \ | |
78 | .bits = _b, \ | |
79 | .stride = (_x) * (_b) / 8, \ | |
80 | .x_mili = PIXEL_SIZE * (_x), \ | |
81 | .y_mili = PIXEL_SIZE * (_y), \ | |
82 | .orientation = _o, \ | |
83 | } | |
84 | ||
85 | #define QXL_MODE_16_32(x_res, y_res, orientation) \ | |
86 | QXL_MODE(x_res, y_res, 16, orientation), \ | |
87 | QXL_MODE(x_res, y_res, 32, orientation) | |
88 | ||
89 | #define QXL_MODE_EX(x_res, y_res) \ | |
90 | QXL_MODE_16_32(x_res, y_res, 0), \ | |
91 | QXL_MODE_16_32(y_res, x_res, 1), \ | |
92 | QXL_MODE_16_32(x_res, y_res, 2), \ | |
93 | QXL_MODE_16_32(y_res, x_res, 3) | |
94 | ||
95 | static QXLMode qxl_modes[] = { | |
96 | QXL_MODE_EX(640, 480), | |
97 | QXL_MODE_EX(800, 480), | |
98 | QXL_MODE_EX(800, 600), | |
99 | QXL_MODE_EX(832, 624), | |
100 | QXL_MODE_EX(960, 640), | |
101 | QXL_MODE_EX(1024, 600), | |
102 | QXL_MODE_EX(1024, 768), | |
103 | QXL_MODE_EX(1152, 864), | |
104 | QXL_MODE_EX(1152, 870), | |
105 | QXL_MODE_EX(1280, 720), | |
106 | QXL_MODE_EX(1280, 760), | |
107 | QXL_MODE_EX(1280, 768), | |
108 | QXL_MODE_EX(1280, 800), | |
109 | QXL_MODE_EX(1280, 960), | |
110 | QXL_MODE_EX(1280, 1024), | |
111 | QXL_MODE_EX(1360, 768), | |
112 | QXL_MODE_EX(1366, 768), | |
113 | QXL_MODE_EX(1400, 1050), | |
114 | QXL_MODE_EX(1440, 900), | |
115 | QXL_MODE_EX(1600, 900), | |
116 | QXL_MODE_EX(1600, 1200), | |
117 | QXL_MODE_EX(1680, 1050), | |
118 | QXL_MODE_EX(1920, 1080), | |
a19cbfb3 GH |
119 | /* these modes need more than 8 MB video memory */ |
120 | QXL_MODE_EX(1920, 1200), | |
121 | QXL_MODE_EX(1920, 1440), | |
122 | QXL_MODE_EX(2048, 1536), | |
123 | QXL_MODE_EX(2560, 1440), | |
124 | QXL_MODE_EX(2560, 1600), | |
a19cbfb3 GH |
125 | /* these modes need more than 16 MB video memory */ |
126 | QXL_MODE_EX(2560, 2048), | |
127 | QXL_MODE_EX(2800, 2100), | |
128 | QXL_MODE_EX(3200, 2400), | |
a19cbfb3 GH |
129 | }; |
130 | ||
131 | static PCIQXLDevice *qxl0; | |
132 | ||
133 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events); | |
5ff4e36c | 134 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); |
a19cbfb3 GH |
135 | static void qxl_reset_memslots(PCIQXLDevice *d); |
136 | static void qxl_reset_surfaces(PCIQXLDevice *d); | |
137 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl); | |
138 | ||
0a530548 | 139 | void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
2bce0400 | 140 | { |
917ae08c | 141 | trace_qxl_set_guest_bug(qxl->id); |
2bce0400 | 142 | qxl_send_events(qxl, QXL_INTERRUPT_ERROR); |
087e6a42 | 143 | qxl->guest_bug = 1; |
2bce0400 | 144 | if (qxl->guestdebug) { |
7635392c AL |
145 | va_list ap; |
146 | va_start(ap, msg); | |
147 | fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); | |
148 | vfprintf(stderr, msg, ap); | |
149 | fprintf(stderr, "\n"); | |
150 | va_end(ap); | |
2bce0400 GH |
151 | } |
152 | } | |
153 | ||
087e6a42 AL |
154 | static void qxl_clear_guest_bug(PCIQXLDevice *qxl) |
155 | { | |
156 | qxl->guest_bug = 0; | |
157 | } | |
aee32bf3 GH |
158 | |
159 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, | |
160 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
161 | uint32_t num_dirty_rects, | |
5ff4e36c | 162 | uint32_t clear_dirty_region, |
2e1a98c9 | 163 | qxl_async_io async, struct QXLCookie *cookie) |
aee32bf3 | 164 | { |
c480bb7d AL |
165 | trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, |
166 | area->top, area->bottom); | |
167 | trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, | |
168 | clear_dirty_region); | |
5ff4e36c AL |
169 | if (async == QXL_SYNC) { |
170 | qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, | |
171 | dirty_rects, num_dirty_rects, clear_dirty_region); | |
172 | } else { | |
2e1a98c9 | 173 | assert(cookie != NULL); |
5ff4e36c | 174 | spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, |
5dba0d45 | 175 | clear_dirty_region, (uintptr_t)cookie); |
5ff4e36c | 176 | } |
aee32bf3 GH |
177 | } |
178 | ||
5ff4e36c AL |
179 | static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, |
180 | uint32_t id) | |
aee32bf3 | 181 | { |
c480bb7d | 182 | trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); |
14898cf6 | 183 | qemu_mutex_lock(&qxl->track_lock); |
14898cf6 GH |
184 | qxl->guest_surfaces.cmds[id] = 0; |
185 | qxl->guest_surfaces.count--; | |
186 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
187 | } |
188 | ||
5ff4e36c AL |
189 | static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, |
190 | qxl_async_io async) | |
191 | { | |
2e1a98c9 AL |
192 | QXLCookie *cookie; |
193 | ||
c480bb7d | 194 | trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); |
5ff4e36c | 195 | if (async) { |
2e1a98c9 AL |
196 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
197 | QXL_IO_DESTROY_SURFACE_ASYNC); | |
198 | cookie->u.surface_id = id; | |
5dba0d45 | 199 | spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); |
5ff4e36c AL |
200 | } else { |
201 | qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); | |
753b8b0d | 202 | qxl_spice_destroy_surface_wait_complete(qxl, id); |
5ff4e36c AL |
203 | } |
204 | } | |
205 | ||
3e16b9c5 AL |
206 | static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) |
207 | { | |
c480bb7d AL |
208 | trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, |
209 | qxl->num_free_res); | |
2e1a98c9 | 210 | spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
211 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
212 | QXL_IO_FLUSH_SURFACES_ASYNC)); | |
3e16b9c5 | 213 | } |
3e16b9c5 | 214 | |
aee32bf3 GH |
215 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
216 | uint32_t count) | |
217 | { | |
c480bb7d | 218 | trace_qxl_spice_loadvm_commands(qxl->id, ext, count); |
aee32bf3 GH |
219 | qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); |
220 | } | |
221 | ||
222 | void qxl_spice_oom(PCIQXLDevice *qxl) | |
223 | { | |
c480bb7d | 224 | trace_qxl_spice_oom(qxl->id); |
aee32bf3 GH |
225 | qxl->ssd.worker->oom(qxl->ssd.worker); |
226 | } | |
227 | ||
228 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl) | |
229 | { | |
c480bb7d | 230 | trace_qxl_spice_reset_memslots(qxl->id); |
aee32bf3 GH |
231 | qxl->ssd.worker->reset_memslots(qxl->ssd.worker); |
232 | } | |
233 | ||
5ff4e36c | 234 | static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) |
aee32bf3 | 235 | { |
c480bb7d | 236 | trace_qxl_spice_destroy_surfaces_complete(qxl->id); |
14898cf6 | 237 | qemu_mutex_lock(&qxl->track_lock); |
ddd8fdc7 GH |
238 | memset(qxl->guest_surfaces.cmds, 0, |
239 | sizeof(qxl->guest_surfaces.cmds) * qxl->ssd.num_surfaces); | |
14898cf6 GH |
240 | qxl->guest_surfaces.count = 0; |
241 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
242 | } |
243 | ||
5ff4e36c AL |
244 | static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) |
245 | { | |
c480bb7d | 246 | trace_qxl_spice_destroy_surfaces(qxl->id, async); |
5ff4e36c | 247 | if (async) { |
2e1a98c9 | 248 | spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
249 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
250 | QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); | |
5ff4e36c AL |
251 | } else { |
252 | qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); | |
253 | qxl_spice_destroy_surfaces_complete(qxl); | |
254 | } | |
255 | } | |
256 | ||
020af1c4 AL |
257 | static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) |
258 | { | |
259 | trace_qxl_spice_monitors_config(qxl->id); | |
020af1c4 AL |
260 | if (replay) { |
261 | /* | |
262 | * don't use QXL_COOKIE_TYPE_IO: | |
263 | * - we are not running yet (post_load), we will assert | |
264 | * in send_events | |
265 | * - this is not a guest io, but a reply, so async_io isn't set. | |
266 | */ | |
267 | spice_qxl_monitors_config_async(&qxl->ssd.qxl, | |
268 | qxl->guest_monitors_config, | |
269 | MEMSLOT_GROUP_GUEST, | |
270 | (uintptr_t)qxl_cookie_new( | |
271 | QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, | |
272 | 0)); | |
273 | } else { | |
274 | qxl->guest_monitors_config = qxl->ram->monitors_config; | |
275 | spice_qxl_monitors_config_async(&qxl->ssd.qxl, | |
276 | qxl->ram->monitors_config, | |
277 | MEMSLOT_GROUP_GUEST, | |
278 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
279 | QXL_IO_MONITORS_CONFIG_ASYNC)); | |
280 | } | |
020af1c4 AL |
281 | } |
282 | ||
aee32bf3 GH |
283 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) |
284 | { | |
c480bb7d | 285 | trace_qxl_spice_reset_image_cache(qxl->id); |
aee32bf3 GH |
286 | qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); |
287 | } | |
288 | ||
289 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl) | |
290 | { | |
c480bb7d | 291 | trace_qxl_spice_reset_cursor(qxl->id); |
aee32bf3 | 292 | qxl->ssd.worker->reset_cursor(qxl->ssd.worker); |
30f6da66 YH |
293 | qemu_mutex_lock(&qxl->track_lock); |
294 | qxl->guest_cursor = 0; | |
295 | qemu_mutex_unlock(&qxl->track_lock); | |
958c2bce GH |
296 | if (qxl->ssd.cursor) { |
297 | cursor_put(qxl->ssd.cursor); | |
298 | } | |
299 | qxl->ssd.cursor = cursor_builtin_hidden(); | |
aee32bf3 GH |
300 | } |
301 | ||
302 | ||
a19cbfb3 GH |
303 | static inline uint32_t msb_mask(uint32_t val) |
304 | { | |
305 | uint32_t mask; | |
306 | ||
307 | do { | |
308 | mask = ~(val - 1) & val; | |
309 | val &= ~mask; | |
310 | } while (mask < val); | |
311 | ||
312 | return mask; | |
313 | } | |
314 | ||
315 | static ram_addr_t qxl_rom_size(void) | |
316 | { | |
317 | uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes); | |
13d1fd44 | 318 | |
a19cbfb3 GH |
319 | rom_size = MAX(rom_size, TARGET_PAGE_SIZE); |
320 | rom_size = msb_mask(rom_size * 2 - 1); | |
321 | return rom_size; | |
322 | } | |
323 | ||
324 | static void init_qxl_rom(PCIQXLDevice *d) | |
325 | { | |
b1950430 | 326 | QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); |
a19cbfb3 GH |
327 | QXLModes *modes = (QXLModes *)(rom + 1); |
328 | uint32_t ram_header_size; | |
329 | uint32_t surface0_area_size; | |
330 | uint32_t num_pages; | |
13d1fd44 AL |
331 | uint32_t fb; |
332 | int i, n; | |
a19cbfb3 GH |
333 | |
334 | memset(rom, 0, d->rom_size); | |
335 | ||
336 | rom->magic = cpu_to_le32(QXL_ROM_MAGIC); | |
337 | rom->id = cpu_to_le32(d->id); | |
338 | rom->log_level = cpu_to_le32(d->guestdebug); | |
339 | rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); | |
340 | ||
341 | rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; | |
342 | rom->slot_id_bits = MEMSLOT_SLOT_BITS; | |
343 | rom->slots_start = 1; | |
344 | rom->slots_end = NUM_MEMSLOTS - 1; | |
ddd8fdc7 | 345 | rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); |
a19cbfb3 | 346 | |
13d1fd44 | 347 | for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { |
a19cbfb3 | 348 | fb = qxl_modes[i].y_res * qxl_modes[i].stride; |
13d1fd44 AL |
349 | if (fb > d->vgamem_size) { |
350 | continue; | |
a19cbfb3 | 351 | } |
13d1fd44 AL |
352 | modes->modes[n].id = cpu_to_le32(i); |
353 | modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); | |
354 | modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); | |
355 | modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); | |
356 | modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); | |
357 | modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); | |
358 | modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); | |
359 | modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); | |
360 | n++; | |
361 | } | |
362 | modes->n_modes = cpu_to_le32(n); | |
a19cbfb3 GH |
363 | |
364 | ram_header_size = ALIGN(sizeof(QXLRam), 4096); | |
13d1fd44 | 365 | surface0_area_size = ALIGN(d->vgamem_size, 4096); |
a19cbfb3 GH |
366 | num_pages = d->vga.vram_size; |
367 | num_pages -= ram_header_size; | |
368 | num_pages -= surface0_area_size; | |
369 | num_pages = num_pages / TARGET_PAGE_SIZE; | |
370 | ||
371 | rom->draw_area_offset = cpu_to_le32(0); | |
372 | rom->surface0_area_size = cpu_to_le32(surface0_area_size); | |
373 | rom->pages_offset = cpu_to_le32(surface0_area_size); | |
374 | rom->num_pages = cpu_to_le32(num_pages); | |
375 | rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); | |
376 | ||
377 | d->shadow_rom = *rom; | |
378 | d->rom = rom; | |
379 | d->modes = modes; | |
380 | } | |
381 | ||
382 | static void init_qxl_ram(PCIQXLDevice *d) | |
383 | { | |
384 | uint8_t *buf; | |
385 | uint64_t *item; | |
386 | ||
387 | buf = d->vga.vram_ptr; | |
388 | d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); | |
389 | d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); | |
390 | d->ram->int_pending = cpu_to_le32(0); | |
391 | d->ram->int_mask = cpu_to_le32(0); | |
9f0f352d | 392 | d->ram->update_surface = 0; |
a19cbfb3 GH |
393 | SPICE_RING_INIT(&d->ram->cmd_ring); |
394 | SPICE_RING_INIT(&d->ram->cursor_ring); | |
395 | SPICE_RING_INIT(&d->ram->release_ring); | |
0b81c478 AL |
396 | SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); |
397 | assert(item); | |
a19cbfb3 GH |
398 | *item = 0; |
399 | qxl_ring_set_dirty(d); | |
400 | } | |
401 | ||
402 | /* can be called from spice server thread context */ | |
b1950430 | 403 | static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) |
a19cbfb3 | 404 | { |
fd4aa979 | 405 | memory_region_set_dirty(mr, addr, end - addr); |
a19cbfb3 GH |
406 | } |
407 | ||
408 | static void qxl_rom_set_dirty(PCIQXLDevice *qxl) | |
409 | { | |
b1950430 | 410 | qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); |
a19cbfb3 GH |
411 | } |
412 | ||
413 | /* called from spice server thread context only */ | |
414 | static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) | |
415 | { | |
a19cbfb3 GH |
416 | void *base = qxl->vga.vram_ptr; |
417 | intptr_t offset; | |
418 | ||
419 | offset = ptr - base; | |
420 | offset &= ~(TARGET_PAGE_SIZE-1); | |
421 | assert(offset < qxl->vga.vram_size); | |
b1950430 | 422 | qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); |
a19cbfb3 GH |
423 | } |
424 | ||
425 | /* can be called from spice server thread context */ | |
426 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl) | |
427 | { | |
b1950430 AK |
428 | ram_addr_t addr = qxl->shadow_rom.ram_header_offset; |
429 | ram_addr_t end = qxl->vga.vram_size; | |
430 | qxl_set_dirty(&qxl->vga.vram, addr, end); | |
a19cbfb3 GH |
431 | } |
432 | ||
433 | /* | |
434 | * keep track of some command state, for savevm/loadvm. | |
435 | * called from spice server thread context only | |
436 | */ | |
fae2afb1 | 437 | static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) |
a19cbfb3 GH |
438 | { |
439 | switch (le32_to_cpu(ext->cmd.type)) { | |
440 | case QXL_CMD_SURFACE: | |
441 | { | |
442 | QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
443 | |
444 | if (!cmd) { | |
445 | return 1; | |
446 | } | |
a19cbfb3 | 447 | uint32_t id = le32_to_cpu(cmd->surface_id); |
47eddfbf | 448 | |
ddd8fdc7 | 449 | if (id >= qxl->ssd.num_surfaces) { |
0a530548 | 450 | qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, |
ddd8fdc7 | 451 | qxl->ssd.num_surfaces); |
47eddfbf AL |
452 | return 1; |
453 | } | |
48f4ba67 AL |
454 | if (cmd->type == QXL_SURFACE_CMD_CREATE && |
455 | (cmd->u.surface_create.stride & 0x03) != 0) { | |
456 | qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", | |
457 | cmd->u.surface_create.stride); | |
458 | return 1; | |
459 | } | |
14898cf6 | 460 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 GH |
461 | if (cmd->type == QXL_SURFACE_CMD_CREATE) { |
462 | qxl->guest_surfaces.cmds[id] = ext->cmd.data; | |
463 | qxl->guest_surfaces.count++; | |
464 | if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) | |
465 | qxl->guest_surfaces.max = qxl->guest_surfaces.count; | |
466 | } | |
467 | if (cmd->type == QXL_SURFACE_CMD_DESTROY) { | |
468 | qxl->guest_surfaces.cmds[id] = 0; | |
469 | qxl->guest_surfaces.count--; | |
470 | } | |
14898cf6 | 471 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
472 | break; |
473 | } | |
474 | case QXL_CMD_CURSOR: | |
475 | { | |
476 | QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
477 | |
478 | if (!cmd) { | |
479 | return 1; | |
480 | } | |
a19cbfb3 | 481 | if (cmd->type == QXL_CURSOR_SET) { |
30f6da66 | 482 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 | 483 | qxl->guest_cursor = ext->cmd.data; |
30f6da66 | 484 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
485 | } |
486 | break; | |
487 | } | |
488 | } | |
fae2afb1 | 489 | return 0; |
a19cbfb3 GH |
490 | } |
491 | ||
492 | /* spice display interface callbacks */ | |
493 | ||
494 | static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) | |
495 | { | |
496 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
497 | ||
c480bb7d | 498 | trace_qxl_interface_attach_worker(qxl->id); |
a19cbfb3 GH |
499 | qxl->ssd.worker = qxl_worker; |
500 | } | |
501 | ||
502 | static void interface_set_compression_level(QXLInstance *sin, int level) | |
503 | { | |
504 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
505 | ||
c480bb7d | 506 | trace_qxl_interface_set_compression_level(qxl->id, level); |
a19cbfb3 GH |
507 | qxl->shadow_rom.compression_level = cpu_to_le32(level); |
508 | qxl->rom->compression_level = cpu_to_le32(level); | |
509 | qxl_rom_set_dirty(qxl); | |
510 | } | |
511 | ||
512 | static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) | |
513 | { | |
514 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
515 | ||
c480bb7d | 516 | trace_qxl_interface_set_mm_time(qxl->id, mm_time); |
a19cbfb3 GH |
517 | qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); |
518 | qxl->rom->mm_clock = cpu_to_le32(mm_time); | |
519 | qxl_rom_set_dirty(qxl); | |
520 | } | |
521 | ||
522 | static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) | |
523 | { | |
524 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
525 | ||
c480bb7d | 526 | trace_qxl_interface_get_init_info(qxl->id); |
a19cbfb3 GH |
527 | info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; |
528 | info->memslot_id_bits = MEMSLOT_SLOT_BITS; | |
529 | info->num_memslots = NUM_MEMSLOTS; | |
530 | info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; | |
531 | info->internal_groupslot_id = 0; | |
532 | info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; | |
ddd8fdc7 | 533 | info->n_surfaces = qxl->ssd.num_surfaces; |
a19cbfb3 GH |
534 | } |
535 | ||
5b77870c AL |
536 | static const char *qxl_mode_to_string(int mode) |
537 | { | |
538 | switch (mode) { | |
539 | case QXL_MODE_COMPAT: | |
540 | return "compat"; | |
541 | case QXL_MODE_NATIVE: | |
542 | return "native"; | |
543 | case QXL_MODE_UNDEFINED: | |
544 | return "undefined"; | |
545 | case QXL_MODE_VGA: | |
546 | return "vga"; | |
547 | } | |
548 | return "INVALID"; | |
549 | } | |
550 | ||
8b92e298 AL |
551 | static const char *io_port_to_string(uint32_t io_port) |
552 | { | |
553 | if (io_port >= QXL_IO_RANGE_SIZE) { | |
554 | return "out of range"; | |
555 | } | |
556 | static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { | |
557 | [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", | |
558 | [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", | |
559 | [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", | |
560 | [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", | |
561 | [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", | |
562 | [QXL_IO_RESET] = "QXL_IO_RESET", | |
563 | [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", | |
564 | [QXL_IO_LOG] = "QXL_IO_LOG", | |
565 | [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", | |
566 | [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", | |
567 | [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", | |
568 | [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", | |
569 | [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", | |
570 | [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", | |
571 | [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", | |
572 | [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", | |
8b92e298 AL |
573 | [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", |
574 | [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", | |
575 | [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", | |
576 | [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", | |
577 | [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", | |
578 | [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] | |
579 | = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", | |
580 | [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", | |
581 | [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", | |
020af1c4 | 582 | [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", |
8b92e298 AL |
583 | }; |
584 | return io_port_to_string[io_port]; | |
585 | } | |
586 | ||
a19cbfb3 GH |
587 | /* called from spice server thread context only */ |
588 | static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
589 | { | |
590 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
591 | SimpleSpiceUpdate *update; | |
592 | QXLCommandRing *ring; | |
593 | QXLCommand *cmd; | |
e0c64d08 | 594 | int notify, ret; |
a19cbfb3 | 595 | |
c480bb7d AL |
596 | trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
597 | ||
a19cbfb3 GH |
598 | switch (qxl->mode) { |
599 | case QXL_MODE_VGA: | |
e0c64d08 GH |
600 | ret = false; |
601 | qemu_mutex_lock(&qxl->ssd.lock); | |
b1af98ba GH |
602 | update = QTAILQ_FIRST(&qxl->ssd.updates); |
603 | if (update != NULL) { | |
604 | QTAILQ_REMOVE(&qxl->ssd.updates, update, next); | |
e0c64d08 GH |
605 | *ext = update->ext; |
606 | ret = true; | |
a19cbfb3 | 607 | } |
e0c64d08 | 608 | qemu_mutex_unlock(&qxl->ssd.lock); |
212496c9 | 609 | if (ret) { |
c480bb7d | 610 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
212496c9 AL |
611 | qxl_log_command(qxl, "vga", ext); |
612 | } | |
e0c64d08 | 613 | return ret; |
a19cbfb3 GH |
614 | case QXL_MODE_COMPAT: |
615 | case QXL_MODE_NATIVE: | |
616 | case QXL_MODE_UNDEFINED: | |
a19cbfb3 | 617 | ring = &qxl->ram->cmd_ring; |
087e6a42 | 618 | if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { |
a19cbfb3 GH |
619 | return false; |
620 | } | |
0b81c478 AL |
621 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
622 | if (!cmd) { | |
623 | return false; | |
624 | } | |
a19cbfb3 GH |
625 | ext->cmd = *cmd; |
626 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
627 | ext->flags = qxl->cmdflags; | |
628 | SPICE_RING_POP(ring, notify); | |
629 | qxl_ring_set_dirty(qxl); | |
630 | if (notify) { | |
631 | qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); | |
632 | } | |
633 | qxl->guest_primary.commands++; | |
634 | qxl_track_command(qxl, ext); | |
635 | qxl_log_command(qxl, "cmd", ext); | |
0b81c478 | 636 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
637 | return true; |
638 | default: | |
639 | return false; | |
640 | } | |
641 | } | |
642 | ||
643 | /* called from spice server thread context only */ | |
644 | static int interface_req_cmd_notification(QXLInstance *sin) | |
645 | { | |
646 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
647 | int wait = 1; | |
648 | ||
c480bb7d | 649 | trace_qxl_ring_command_req_notification(qxl->id); |
a19cbfb3 GH |
650 | switch (qxl->mode) { |
651 | case QXL_MODE_COMPAT: | |
652 | case QXL_MODE_NATIVE: | |
653 | case QXL_MODE_UNDEFINED: | |
654 | SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); | |
655 | qxl_ring_set_dirty(qxl); | |
656 | break; | |
657 | default: | |
658 | /* nothing */ | |
659 | break; | |
660 | } | |
661 | return wait; | |
662 | } | |
663 | ||
664 | /* called from spice server thread context only */ | |
665 | static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) | |
666 | { | |
667 | QXLReleaseRing *ring = &d->ram->release_ring; | |
668 | uint64_t *item; | |
669 | int notify; | |
670 | ||
671 | #define QXL_FREE_BUNCH_SIZE 32 | |
672 | ||
673 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
674 | /* ring full -- can't push */ | |
675 | return; | |
676 | } | |
677 | if (!flush && d->oom_running) { | |
678 | /* collect everything from oom handler before pushing */ | |
679 | return; | |
680 | } | |
681 | if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { | |
682 | /* collect a bit more before pushing */ | |
683 | return; | |
684 | } | |
685 | ||
686 | SPICE_RING_PUSH(ring, notify); | |
c480bb7d AL |
687 | trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), |
688 | d->guest_surfaces.count, d->num_free_res, | |
689 | d->last_release, notify ? "yes" : "no"); | |
690 | trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, | |
691 | ring->num_items, ring->prod, ring->cons); | |
a19cbfb3 GH |
692 | if (notify) { |
693 | qxl_send_events(d, QXL_INTERRUPT_DISPLAY); | |
694 | } | |
0b81c478 AL |
695 | SPICE_RING_PROD_ITEM(d, ring, item); |
696 | if (!item) { | |
697 | return; | |
698 | } | |
a19cbfb3 GH |
699 | *item = 0; |
700 | d->num_free_res = 0; | |
701 | d->last_release = NULL; | |
702 | qxl_ring_set_dirty(d); | |
703 | } | |
704 | ||
705 | /* called from spice server thread context only */ | |
706 | static void interface_release_resource(QXLInstance *sin, | |
707 | struct QXLReleaseInfoExt ext) | |
708 | { | |
709 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
710 | QXLReleaseRing *ring; | |
711 | uint64_t *item, id; | |
712 | ||
713 | if (ext.group_id == MEMSLOT_GROUP_HOST) { | |
714 | /* host group -> vga mode update request */ | |
f4a8a424 | 715 | qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id); |
a19cbfb3 GH |
716 | return; |
717 | } | |
718 | ||
719 | /* | |
720 | * ext->info points into guest-visible memory | |
721 | * pci bar 0, $command.release_info | |
722 | */ | |
723 | ring = &qxl->ram->release_ring; | |
0b81c478 AL |
724 | SPICE_RING_PROD_ITEM(qxl, ring, item); |
725 | if (!item) { | |
726 | return; | |
727 | } | |
a19cbfb3 GH |
728 | if (*item == 0) { |
729 | /* stick head into the ring */ | |
730 | id = ext.info->id; | |
731 | ext.info->next = 0; | |
732 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
733 | *item = id; | |
734 | qxl_ring_set_dirty(qxl); | |
735 | } else { | |
736 | /* append item to the list */ | |
737 | qxl->last_release->next = ext.info->id; | |
738 | qxl_ram_set_dirty(qxl, &qxl->last_release->next); | |
739 | ext.info->next = 0; | |
740 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
741 | } | |
742 | qxl->last_release = ext.info; | |
743 | qxl->num_free_res++; | |
c480bb7d | 744 | trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); |
a19cbfb3 GH |
745 | qxl_push_free_res(qxl, 0); |
746 | } | |
747 | ||
748 | /* called from spice server thread context only */ | |
749 | static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
750 | { | |
751 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
752 | QXLCursorRing *ring; | |
753 | QXLCommand *cmd; | |
754 | int notify; | |
755 | ||
c480bb7d AL |
756 | trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
757 | ||
a19cbfb3 GH |
758 | switch (qxl->mode) { |
759 | case QXL_MODE_COMPAT: | |
760 | case QXL_MODE_NATIVE: | |
761 | case QXL_MODE_UNDEFINED: | |
762 | ring = &qxl->ram->cursor_ring; | |
763 | if (SPICE_RING_IS_EMPTY(ring)) { | |
764 | return false; | |
765 | } | |
0b81c478 AL |
766 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
767 | if (!cmd) { | |
768 | return false; | |
769 | } | |
a19cbfb3 GH |
770 | ext->cmd = *cmd; |
771 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
772 | ext->flags = qxl->cmdflags; | |
773 | SPICE_RING_POP(ring, notify); | |
774 | qxl_ring_set_dirty(qxl); | |
775 | if (notify) { | |
776 | qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); | |
777 | } | |
778 | qxl->guest_primary.commands++; | |
779 | qxl_track_command(qxl, ext); | |
780 | qxl_log_command(qxl, "csr", ext); | |
781 | if (qxl->id == 0) { | |
782 | qxl_render_cursor(qxl, ext); | |
783 | } | |
c480bb7d | 784 | trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
785 | return true; |
786 | default: | |
787 | return false; | |
788 | } | |
789 | } | |
790 | ||
791 | /* called from spice server thread context only */ | |
792 | static int interface_req_cursor_notification(QXLInstance *sin) | |
793 | { | |
794 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
795 | int wait = 1; | |
796 | ||
c480bb7d | 797 | trace_qxl_ring_cursor_req_notification(qxl->id); |
a19cbfb3 GH |
798 | switch (qxl->mode) { |
799 | case QXL_MODE_COMPAT: | |
800 | case QXL_MODE_NATIVE: | |
801 | case QXL_MODE_UNDEFINED: | |
802 | SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); | |
803 | qxl_ring_set_dirty(qxl); | |
804 | break; | |
805 | default: | |
806 | /* nothing */ | |
807 | break; | |
808 | } | |
809 | return wait; | |
810 | } | |
811 | ||
812 | /* called from spice server thread context */ | |
813 | static void interface_notify_update(QXLInstance *sin, uint32_t update_id) | |
814 | { | |
baeae407 AL |
815 | /* |
816 | * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in | |
817 | * use by xf86-video-qxl and is defined out in the qxl windows driver. | |
818 | * Probably was at some earlier version that is prior to git start (2009), | |
819 | * and is still guest trigerrable. | |
820 | */ | |
821 | fprintf(stderr, "%s: deprecated\n", __func__); | |
a19cbfb3 GH |
822 | } |
823 | ||
824 | /* called from spice server thread context only */ | |
825 | static int interface_flush_resources(QXLInstance *sin) | |
826 | { | |
827 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
828 | int ret; | |
829 | ||
a19cbfb3 GH |
830 | ret = qxl->num_free_res; |
831 | if (ret) { | |
832 | qxl_push_free_res(qxl, 1); | |
833 | } | |
834 | return ret; | |
835 | } | |
836 | ||
5ff4e36c AL |
837 | static void qxl_create_guest_primary_complete(PCIQXLDevice *d); |
838 | ||
5ff4e36c | 839 | /* called from spice server thread context only */ |
2e1a98c9 | 840 | static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) |
5ff4e36c | 841 | { |
5ff4e36c AL |
842 | uint32_t current_async; |
843 | ||
844 | qemu_mutex_lock(&qxl->async_lock); | |
845 | current_async = qxl->current_async; | |
846 | qxl->current_async = QXL_UNDEFINED_IO; | |
847 | qemu_mutex_unlock(&qxl->async_lock); | |
848 | ||
c480bb7d | 849 | trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); |
2e1a98c9 AL |
850 | if (!cookie) { |
851 | fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); | |
852 | return; | |
853 | } | |
854 | if (cookie && current_async != cookie->io) { | |
855 | fprintf(stderr, | |
2fce7edf AL |
856 | "qxl: %s: error: current_async = %d != %" |
857 | PRId64 " = cookie->io\n", __func__, current_async, cookie->io); | |
2e1a98c9 | 858 | } |
5ff4e36c | 859 | switch (current_async) { |
81fb6f15 AL |
860 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
861 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
862 | case QXL_IO_UPDATE_AREA_ASYNC: | |
863 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
020af1c4 | 864 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
81fb6f15 | 865 | break; |
5ff4e36c AL |
866 | case QXL_IO_CREATE_PRIMARY_ASYNC: |
867 | qxl_create_guest_primary_complete(qxl); | |
868 | break; | |
869 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
870 | qxl_spice_destroy_surfaces_complete(qxl); | |
871 | break; | |
872 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
2e1a98c9 | 873 | qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); |
5ff4e36c | 874 | break; |
81fb6f15 AL |
875 | default: |
876 | fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, | |
877 | current_async); | |
5ff4e36c AL |
878 | } |
879 | qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); | |
880 | } | |
881 | ||
81fb6f15 AL |
882 | /* called from spice server thread context only */ |
883 | static void interface_update_area_complete(QXLInstance *sin, | |
884 | uint32_t surface_id, | |
885 | QXLRect *dirty, uint32_t num_updated_rects) | |
886 | { | |
887 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
888 | int i; | |
889 | int qxl_i; | |
890 | ||
891 | qemu_mutex_lock(&qxl->ssd.lock); | |
892 | if (surface_id != 0 || !qxl->render_update_cookie_num) { | |
893 | qemu_mutex_unlock(&qxl->ssd.lock); | |
894 | return; | |
895 | } | |
c480bb7d AL |
896 | trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, |
897 | dirty->right, dirty->top, dirty->bottom); | |
898 | trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); | |
81fb6f15 AL |
899 | if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { |
900 | /* | |
901 | * overflow - treat this as a full update. Not expected to be common. | |
902 | */ | |
c480bb7d AL |
903 | trace_qxl_interface_update_area_complete_overflow(qxl->id, |
904 | QXL_NUM_DIRTY_RECTS); | |
81fb6f15 AL |
905 | qxl->guest_primary.resized = 1; |
906 | } | |
907 | if (qxl->guest_primary.resized) { | |
908 | /* | |
909 | * Don't bother copying or scheduling the bh since we will flip | |
910 | * the whole area anyway on completion of the update_area async call | |
911 | */ | |
912 | qemu_mutex_unlock(&qxl->ssd.lock); | |
913 | return; | |
914 | } | |
915 | qxl_i = qxl->num_dirty_rects; | |
916 | for (i = 0; i < num_updated_rects; i++) { | |
917 | qxl->dirty[qxl_i++] = dirty[i]; | |
918 | } | |
919 | qxl->num_dirty_rects += num_updated_rects; | |
c480bb7d AL |
920 | trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, |
921 | qxl->num_dirty_rects); | |
81fb6f15 AL |
922 | qemu_bh_schedule(qxl->update_area_bh); |
923 | qemu_mutex_unlock(&qxl->ssd.lock); | |
924 | } | |
925 | ||
2e1a98c9 AL |
926 | /* called from spice server thread context only */ |
927 | static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) | |
928 | { | |
929 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
5dba0d45 | 930 | QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; |
2e1a98c9 AL |
931 | |
932 | switch (cookie->type) { | |
933 | case QXL_COOKIE_TYPE_IO: | |
934 | interface_async_complete_io(qxl, cookie); | |
81fb6f15 AL |
935 | g_free(cookie); |
936 | break; | |
937 | case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: | |
938 | qxl_render_update_area_done(qxl, cookie); | |
2e1a98c9 | 939 | break; |
020af1c4 AL |
940 | case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: |
941 | break; | |
2e1a98c9 AL |
942 | default: |
943 | fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", | |
944 | __func__, cookie->type); | |
81fb6f15 | 945 | g_free(cookie); |
2e1a98c9 | 946 | } |
2e1a98c9 AL |
947 | } |
948 | ||
c10018d6 SSP |
949 | /* called from spice server thread context only */ |
950 | static void interface_set_client_capabilities(QXLInstance *sin, | |
951 | uint8_t client_present, | |
952 | uint8_t caps[58]) | |
953 | { | |
954 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
955 | ||
ab902981 HG |
956 | if (runstate_check(RUN_STATE_INMIGRATE) || |
957 | runstate_check(RUN_STATE_POSTMIGRATE)) { | |
958 | return; | |
959 | } | |
960 | ||
c10018d6 SSP |
961 | qxl->shadow_rom.client_present = client_present; |
962 | memcpy(qxl->shadow_rom.client_capabilities, caps, sizeof(caps)); | |
963 | qxl->rom->client_present = client_present; | |
964 | memcpy(qxl->rom->client_capabilities, caps, sizeof(caps)); | |
965 | qxl_rom_set_dirty(qxl); | |
966 | ||
967 | qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); | |
968 | } | |
969 | ||
a639ab04 AL |
970 | static uint32_t qxl_crc32(const uint8_t *p, unsigned len) |
971 | { | |
972 | /* | |
973 | * zlib xors the seed with 0xffffffff, and xors the result | |
974 | * again with 0xffffffff; Both are not done with linux's crc32, | |
975 | * which we want to be compatible with, so undo that. | |
976 | */ | |
977 | return crc32(0xffffffff, p, len) ^ 0xffffffff; | |
978 | } | |
979 | ||
980 | /* called from main context only */ | |
981 | static int interface_client_monitors_config(QXLInstance *sin, | |
982 | VDAgentMonitorsConfig *monitors_config) | |
983 | { | |
984 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
985 | QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); | |
986 | int i; | |
987 | ||
988 | /* | |
989 | * Older windows drivers set int_mask to 0 when their ISR is called, | |
990 | * then later set it to ~0. So it doesn't relate to the actual interrupts | |
991 | * handled. However, they are old, so clearly they don't support this | |
992 | * interrupt | |
993 | */ | |
994 | if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || | |
995 | !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { | |
996 | trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, | |
997 | qxl->ram->int_mask, | |
998 | monitors_config); | |
999 | return 0; | |
1000 | } | |
1001 | if (!monitors_config) { | |
1002 | return 1; | |
1003 | } | |
1004 | memset(&rom->client_monitors_config, 0, | |
1005 | sizeof(rom->client_monitors_config)); | |
1006 | rom->client_monitors_config.count = monitors_config->num_of_monitors; | |
1007 | /* monitors_config->flags ignored */ | |
1008 | if (rom->client_monitors_config.count >= | |
1009 | ARRAY_SIZE(rom->client_monitors_config.heads)) { | |
1010 | trace_qxl_client_monitors_config_capped(qxl->id, | |
1011 | monitors_config->num_of_monitors, | |
1012 | ARRAY_SIZE(rom->client_monitors_config.heads)); | |
1013 | rom->client_monitors_config.count = | |
1014 | ARRAY_SIZE(rom->client_monitors_config.heads); | |
1015 | } | |
1016 | for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { | |
1017 | VDAgentMonConfig *monitor = &monitors_config->monitors[i]; | |
1018 | QXLURect *rect = &rom->client_monitors_config.heads[i]; | |
1019 | /* monitor->depth ignored */ | |
1020 | rect->left = monitor->x; | |
1021 | rect->top = monitor->y; | |
1022 | rect->right = monitor->x + monitor->width; | |
1023 | rect->bottom = monitor->y + monitor->height; | |
1024 | } | |
1025 | rom->client_monitors_config_crc = qxl_crc32( | |
1026 | (const uint8_t *)&rom->client_monitors_config, | |
1027 | sizeof(rom->client_monitors_config)); | |
1028 | trace_qxl_client_monitors_config_crc(qxl->id, | |
1029 | sizeof(rom->client_monitors_config), | |
1030 | rom->client_monitors_config_crc); | |
1031 | ||
1032 | trace_qxl_interrupt_client_monitors_config(qxl->id, | |
1033 | rom->client_monitors_config.count, | |
1034 | rom->client_monitors_config.heads); | |
1035 | qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); | |
1036 | return 1; | |
1037 | } | |
a639ab04 | 1038 | |
a19cbfb3 GH |
1039 | static const QXLInterface qxl_interface = { |
1040 | .base.type = SPICE_INTERFACE_QXL, | |
1041 | .base.description = "qxl gpu", | |
1042 | .base.major_version = SPICE_INTERFACE_QXL_MAJOR, | |
1043 | .base.minor_version = SPICE_INTERFACE_QXL_MINOR, | |
1044 | ||
1045 | .attache_worker = interface_attach_worker, | |
1046 | .set_compression_level = interface_set_compression_level, | |
1047 | .set_mm_time = interface_set_mm_time, | |
1048 | .get_init_info = interface_get_init_info, | |
1049 | ||
1050 | /* the callbacks below are called from spice server thread context */ | |
1051 | .get_command = interface_get_command, | |
1052 | .req_cmd_notification = interface_req_cmd_notification, | |
1053 | .release_resource = interface_release_resource, | |
1054 | .get_cursor_command = interface_get_cursor_command, | |
1055 | .req_cursor_notification = interface_req_cursor_notification, | |
1056 | .notify_update = interface_notify_update, | |
1057 | .flush_resources = interface_flush_resources, | |
5ff4e36c | 1058 | .async_complete = interface_async_complete, |
81fb6f15 | 1059 | .update_area_complete = interface_update_area_complete, |
c10018d6 | 1060 | .set_client_capabilities = interface_set_client_capabilities, |
a639ab04 | 1061 | .client_monitors_config = interface_client_monitors_config, |
a19cbfb3 GH |
1062 | }; |
1063 | ||
1064 | static void qxl_enter_vga_mode(PCIQXLDevice *d) | |
1065 | { | |
1066 | if (d->mode == QXL_MODE_VGA) { | |
1067 | return; | |
1068 | } | |
c480bb7d | 1069 | trace_qxl_enter_vga_mode(d->id); |
a19cbfb3 GH |
1070 | qemu_spice_create_host_primary(&d->ssd); |
1071 | d->mode = QXL_MODE_VGA; | |
e32c25b5 | 1072 | dpy_gfx_resize(d->ssd.ds); |
0f7bfd81 | 1073 | vga_dirty_log_start(&d->vga); |
a19cbfb3 GH |
1074 | } |
1075 | ||
1076 | static void qxl_exit_vga_mode(PCIQXLDevice *d) | |
1077 | { | |
1078 | if (d->mode != QXL_MODE_VGA) { | |
1079 | return; | |
1080 | } | |
c480bb7d | 1081 | trace_qxl_exit_vga_mode(d->id); |
0f7bfd81 | 1082 | vga_dirty_log_stop(&d->vga); |
5ff4e36c | 1083 | qxl_destroy_primary(d, QXL_SYNC); |
a19cbfb3 GH |
1084 | } |
1085 | ||
40010aea | 1086 | static void qxl_update_irq(PCIQXLDevice *d) |
a19cbfb3 GH |
1087 | { |
1088 | uint32_t pending = le32_to_cpu(d->ram->int_pending); | |
1089 | uint32_t mask = le32_to_cpu(d->ram->int_mask); | |
1090 | int level = !!(pending & mask); | |
1091 | qemu_set_irq(d->pci.irq[0], level); | |
1092 | qxl_ring_set_dirty(d); | |
1093 | } | |
1094 | ||
a19cbfb3 GH |
1095 | static void qxl_check_state(PCIQXLDevice *d) |
1096 | { | |
1097 | QXLRam *ram = d->ram; | |
71d388d4 | 1098 | int spice_display_running = qemu_spice_display_is_running(&d->ssd); |
a19cbfb3 | 1099 | |
71d388d4 YH |
1100 | assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
1101 | assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); | |
a19cbfb3 GH |
1102 | } |
1103 | ||
1104 | static void qxl_reset_state(PCIQXLDevice *d) | |
1105 | { | |
a19cbfb3 GH |
1106 | QXLRom *rom = d->rom; |
1107 | ||
be48e995 | 1108 | qxl_check_state(d); |
a19cbfb3 GH |
1109 | d->shadow_rom.update_id = cpu_to_le32(0); |
1110 | *rom = d->shadow_rom; | |
1111 | qxl_rom_set_dirty(d); | |
1112 | init_qxl_ram(d); | |
1113 | d->num_free_res = 0; | |
1114 | d->last_release = NULL; | |
1115 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
1116 | } | |
1117 | ||
1118 | static void qxl_soft_reset(PCIQXLDevice *d) | |
1119 | { | |
c480bb7d | 1120 | trace_qxl_soft_reset(d->id); |
a19cbfb3 | 1121 | qxl_check_state(d); |
087e6a42 | 1122 | qxl_clear_guest_bug(d); |
a5f68c22 | 1123 | d->current_async = QXL_UNDEFINED_IO; |
a19cbfb3 GH |
1124 | |
1125 | if (d->id == 0) { | |
1126 | qxl_enter_vga_mode(d); | |
1127 | } else { | |
1128 | d->mode = QXL_MODE_UNDEFINED; | |
1129 | } | |
1130 | } | |
1131 | ||
1132 | static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) | |
1133 | { | |
c480bb7d | 1134 | trace_qxl_hard_reset(d->id, loadvm); |
a19cbfb3 | 1135 | |
aee32bf3 GH |
1136 | qxl_spice_reset_cursor(d); |
1137 | qxl_spice_reset_image_cache(d); | |
a19cbfb3 GH |
1138 | qxl_reset_surfaces(d); |
1139 | qxl_reset_memslots(d); | |
1140 | ||
1141 | /* pre loadvm reset must not touch QXLRam. This lives in | |
1142 | * device memory, is migrated together with RAM and thus | |
1143 | * already loaded at this point */ | |
1144 | if (!loadvm) { | |
1145 | qxl_reset_state(d); | |
1146 | } | |
1147 | qemu_spice_create_host_memslot(&d->ssd); | |
1148 | qxl_soft_reset(d); | |
a19cbfb3 GH |
1149 | } |
1150 | ||
1151 | static void qxl_reset_handler(DeviceState *dev) | |
1152 | { | |
1153 | PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); | |
c480bb7d | 1154 | |
a19cbfb3 GH |
1155 | qxl_hard_reset(d, 0); |
1156 | } | |
1157 | ||
1158 | static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | |
1159 | { | |
1160 | VGACommonState *vga = opaque; | |
1161 | PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); | |
1162 | ||
c480bb7d | 1163 | trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); |
a19cbfb3 | 1164 | if (qxl->mode != QXL_MODE_VGA) { |
5ff4e36c | 1165 | qxl_destroy_primary(qxl, QXL_SYNC); |
a19cbfb3 GH |
1166 | qxl_soft_reset(qxl); |
1167 | } | |
1168 | vga_ioport_write(opaque, addr, val); | |
1169 | } | |
1170 | ||
f67ab77a GH |
1171 | static const MemoryRegionPortio qxl_vga_portio_list[] = { |
1172 | { 0x04, 2, 1, .read = vga_ioport_read, | |
1173 | .write = qxl_vga_ioport_write }, /* 3b4 */ | |
1174 | { 0x0a, 1, 1, .read = vga_ioport_read, | |
1175 | .write = qxl_vga_ioport_write }, /* 3ba */ | |
1176 | { 0x10, 16, 1, .read = vga_ioport_read, | |
1177 | .write = qxl_vga_ioport_write }, /* 3c0 */ | |
1178 | { 0x24, 2, 1, .read = vga_ioport_read, | |
1179 | .write = qxl_vga_ioport_write }, /* 3d4 */ | |
1180 | { 0x2a, 1, 1, .read = vga_ioport_read, | |
1181 | .write = qxl_vga_ioport_write }, /* 3da */ | |
1182 | PORTIO_END_OF_LIST(), | |
1183 | }; | |
1184 | ||
e954ea28 AL |
1185 | static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, |
1186 | qxl_async_io async) | |
a19cbfb3 GH |
1187 | { |
1188 | static const int regions[] = { | |
1189 | QXL_RAM_RANGE_INDEX, | |
1190 | QXL_VRAM_RANGE_INDEX, | |
6f2b175a | 1191 | QXL_VRAM64_RANGE_INDEX, |
a19cbfb3 GH |
1192 | }; |
1193 | uint64_t guest_start; | |
1194 | uint64_t guest_end; | |
1195 | int pci_region; | |
1196 | pcibus_t pci_start; | |
1197 | pcibus_t pci_end; | |
1198 | intptr_t virt_start; | |
1199 | QXLDevMemSlot memslot; | |
1200 | int i; | |
1201 | ||
1202 | guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); | |
1203 | guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); | |
1204 | ||
c480bb7d | 1205 | trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); |
a19cbfb3 | 1206 | |
e954ea28 | 1207 | if (slot_id >= NUM_MEMSLOTS) { |
0a530548 | 1208 | qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, |
e954ea28 AL |
1209 | slot_id, NUM_MEMSLOTS); |
1210 | return 1; | |
1211 | } | |
1212 | if (guest_start > guest_end) { | |
0a530548 | 1213 | qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 |
e954ea28 AL |
1214 | " > 0x%" PRIx64, __func__, guest_start, guest_end); |
1215 | return 1; | |
1216 | } | |
a19cbfb3 GH |
1217 | |
1218 | for (i = 0; i < ARRAY_SIZE(regions); i++) { | |
1219 | pci_region = regions[i]; | |
1220 | pci_start = d->pci.io_regions[pci_region].addr; | |
1221 | pci_end = pci_start + d->pci.io_regions[pci_region].size; | |
1222 | /* mapped? */ | |
1223 | if (pci_start == -1) { | |
1224 | continue; | |
1225 | } | |
1226 | /* start address in range ? */ | |
1227 | if (guest_start < pci_start || guest_start > pci_end) { | |
1228 | continue; | |
1229 | } | |
1230 | /* end address in range ? */ | |
1231 | if (guest_end > pci_end) { | |
1232 | continue; | |
1233 | } | |
1234 | /* passed */ | |
1235 | break; | |
1236 | } | |
e954ea28 | 1237 | if (i == ARRAY_SIZE(regions)) { |
0a530548 | 1238 | qxl_set_guest_bug(d, "%s: finished loop without match", __func__); |
e954ea28 AL |
1239 | return 1; |
1240 | } | |
a19cbfb3 GH |
1241 | |
1242 | switch (pci_region) { | |
1243 | case QXL_RAM_RANGE_INDEX: | |
b1950430 | 1244 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); |
a19cbfb3 GH |
1245 | break; |
1246 | case QXL_VRAM_RANGE_INDEX: | |
6f2b175a | 1247 | case 4 /* vram 64bit */: |
b1950430 | 1248 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); |
a19cbfb3 GH |
1249 | break; |
1250 | default: | |
1251 | /* should not happen */ | |
0a530548 | 1252 | qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); |
e954ea28 | 1253 | return 1; |
a19cbfb3 GH |
1254 | } |
1255 | ||
1256 | memslot.slot_id = slot_id; | |
1257 | memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ | |
1258 | memslot.virt_start = virt_start + (guest_start - pci_start); | |
1259 | memslot.virt_end = virt_start + (guest_end - pci_start); | |
1260 | memslot.addr_delta = memslot.virt_start - delta; | |
1261 | memslot.generation = d->rom->slot_generation = 0; | |
1262 | qxl_rom_set_dirty(d); | |
1263 | ||
5ff4e36c | 1264 | qemu_spice_add_memslot(&d->ssd, &memslot, async); |
a19cbfb3 GH |
1265 | d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; |
1266 | d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; | |
1267 | d->guest_slots[slot_id].delta = delta; | |
1268 | d->guest_slots[slot_id].active = 1; | |
e954ea28 | 1269 | return 0; |
a19cbfb3 GH |
1270 | } |
1271 | ||
1272 | static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) | |
1273 | { | |
5c59d118 | 1274 | qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
a19cbfb3 GH |
1275 | d->guest_slots[slot_id].active = 0; |
1276 | } | |
1277 | ||
1278 | static void qxl_reset_memslots(PCIQXLDevice *d) | |
1279 | { | |
aee32bf3 | 1280 | qxl_spice_reset_memslots(d); |
a19cbfb3 GH |
1281 | memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
1282 | } | |
1283 | ||
1284 | static void qxl_reset_surfaces(PCIQXLDevice *d) | |
1285 | { | |
c480bb7d | 1286 | trace_qxl_reset_surfaces(d->id); |
a19cbfb3 | 1287 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1288 | qxl_spice_destroy_surfaces(d, QXL_SYNC); |
a19cbfb3 GH |
1289 | } |
1290 | ||
e25139b3 | 1291 | /* can be also called from spice server thread context */ |
a19cbfb3 GH |
1292 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
1293 | { | |
1294 | uint64_t phys = le64_to_cpu(pqxl); | |
1295 | uint32_t slot = (phys >> (64 - 8)) & 0xff; | |
1296 | uint64_t offset = phys & 0xffffffffffff; | |
1297 | ||
1298 | switch (group_id) { | |
1299 | case MEMSLOT_GROUP_HOST: | |
f4a8a424 | 1300 | return (void *)(intptr_t)offset; |
a19cbfb3 | 1301 | case MEMSLOT_GROUP_GUEST: |
4b635c59 | 1302 | if (slot >= NUM_MEMSLOTS) { |
0a530548 AL |
1303 | qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, |
1304 | NUM_MEMSLOTS); | |
4b635c59 AL |
1305 | return NULL; |
1306 | } | |
1307 | if (!qxl->guest_slots[slot].active) { | |
0a530548 | 1308 | qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); |
4b635c59 AL |
1309 | return NULL; |
1310 | } | |
1311 | if (offset < qxl->guest_slots[slot].delta) { | |
0a530548 AL |
1312 | qxl_set_guest_bug(qxl, |
1313 | "slot %d offset %"PRIu64" < delta %"PRIu64"\n", | |
4b635c59 AL |
1314 | slot, offset, qxl->guest_slots[slot].delta); |
1315 | return NULL; | |
1316 | } | |
a19cbfb3 | 1317 | offset -= qxl->guest_slots[slot].delta; |
4b635c59 | 1318 | if (offset > qxl->guest_slots[slot].size) { |
0a530548 AL |
1319 | qxl_set_guest_bug(qxl, |
1320 | "slot %d offset %"PRIu64" > size %"PRIu64"\n", | |
4b635c59 AL |
1321 | slot, offset, qxl->guest_slots[slot].size); |
1322 | return NULL; | |
1323 | } | |
a19cbfb3 | 1324 | return qxl->guest_slots[slot].ptr + offset; |
a19cbfb3 | 1325 | } |
4b635c59 | 1326 | return NULL; |
a19cbfb3 GH |
1327 | } |
1328 | ||
5ff4e36c AL |
1329 | static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) |
1330 | { | |
1331 | /* for local rendering */ | |
1332 | qxl_render_resize(qxl); | |
1333 | } | |
1334 | ||
1335 | static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, | |
1336 | qxl_async_io async) | |
a19cbfb3 GH |
1337 | { |
1338 | QXLDevSurfaceCreate surface; | |
1339 | QXLSurfaceCreate *sc = &qxl->guest_primary.surface; | |
13d1fd44 AL |
1340 | int size; |
1341 | int requested_height = le32_to_cpu(sc->height); | |
1342 | int requested_stride = le32_to_cpu(sc->stride); | |
1343 | ||
1344 | size = abs(requested_stride) * requested_height; | |
1345 | if (size > qxl->vgamem_size) { | |
1346 | qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer" | |
1347 | " size", __func__); | |
1348 | return; | |
1349 | } | |
a19cbfb3 | 1350 | |
ddf9f4b7 | 1351 | if (qxl->mode == QXL_MODE_NATIVE) { |
0a530548 | 1352 | qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", |
ddf9f4b7 AL |
1353 | __func__); |
1354 | } | |
a19cbfb3 GH |
1355 | qxl_exit_vga_mode(qxl); |
1356 | ||
a19cbfb3 GH |
1357 | surface.format = le32_to_cpu(sc->format); |
1358 | surface.height = le32_to_cpu(sc->height); | |
1359 | surface.mem = le64_to_cpu(sc->mem); | |
1360 | surface.position = le32_to_cpu(sc->position); | |
1361 | surface.stride = le32_to_cpu(sc->stride); | |
1362 | surface.width = le32_to_cpu(sc->width); | |
1363 | surface.type = le32_to_cpu(sc->type); | |
1364 | surface.flags = le32_to_cpu(sc->flags); | |
c480bb7d AL |
1365 | trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, |
1366 | sc->format, sc->position); | |
1367 | trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, | |
1368 | sc->flags); | |
a19cbfb3 | 1369 | |
48f4ba67 AL |
1370 | if ((surface.stride & 0x3) != 0) { |
1371 | qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", | |
1372 | surface.stride); | |
1373 | return; | |
1374 | } | |
1375 | ||
a19cbfb3 GH |
1376 | surface.mouse_mode = true; |
1377 | surface.group_id = MEMSLOT_GROUP_GUEST; | |
1378 | if (loadvm) { | |
1379 | surface.flags |= QXL_SURF_FLAG_KEEP_DATA; | |
1380 | } | |
1381 | ||
1382 | qxl->mode = QXL_MODE_NATIVE; | |
1383 | qxl->cmdflags = 0; | |
5ff4e36c | 1384 | qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); |
a19cbfb3 | 1385 | |
5ff4e36c AL |
1386 | if (async == QXL_SYNC) { |
1387 | qxl_create_guest_primary_complete(qxl); | |
1388 | } | |
a19cbfb3 GH |
1389 | } |
1390 | ||
5ff4e36c AL |
1391 | /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or |
1392 | * done (in QXL_SYNC case), 0 otherwise. */ | |
1393 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) | |
a19cbfb3 GH |
1394 | { |
1395 | if (d->mode == QXL_MODE_UNDEFINED) { | |
5ff4e36c | 1396 | return 0; |
a19cbfb3 | 1397 | } |
c480bb7d | 1398 | trace_qxl_destroy_primary(d->id); |
a19cbfb3 | 1399 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1400 | qemu_spice_destroy_primary_surface(&d->ssd, 0, async); |
30f6da66 | 1401 | qxl_spice_reset_cursor(d); |
5ff4e36c | 1402 | return 1; |
a19cbfb3 GH |
1403 | } |
1404 | ||
1405 | static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) | |
1406 | { | |
1407 | pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1408 | pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; | |
1409 | QXLMode *mode = d->modes->modes + modenr; | |
1410 | uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1411 | QXLMemSlot slot = { | |
1412 | .mem_start = start, | |
1413 | .mem_end = end | |
1414 | }; | |
1415 | QXLSurfaceCreate surface = { | |
1416 | .width = mode->x_res, | |
1417 | .height = mode->y_res, | |
1418 | .stride = -mode->x_res * 4, | |
1419 | .format = SPICE_SURFACE_FMT_32_xRGB, | |
1420 | .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, | |
1421 | .mouse_mode = true, | |
1422 | .mem = devmem + d->shadow_rom.draw_area_offset, | |
1423 | }; | |
1424 | ||
c480bb7d AL |
1425 | trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, |
1426 | devmem); | |
a19cbfb3 GH |
1427 | if (!loadvm) { |
1428 | qxl_hard_reset(d, 0); | |
1429 | } | |
1430 | ||
1431 | d->guest_slots[0].slot = slot; | |
e954ea28 | 1432 | assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); |
a19cbfb3 GH |
1433 | |
1434 | d->guest_primary.surface = surface; | |
5ff4e36c | 1435 | qxl_create_guest_primary(d, 0, QXL_SYNC); |
a19cbfb3 GH |
1436 | |
1437 | d->mode = QXL_MODE_COMPAT; | |
1438 | d->cmdflags = QXL_COMMAND_FLAG_COMPAT; | |
a19cbfb3 GH |
1439 | if (mode->bits == 16) { |
1440 | d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; | |
1441 | } | |
a19cbfb3 GH |
1442 | d->shadow_rom.mode = cpu_to_le32(modenr); |
1443 | d->rom->mode = cpu_to_le32(modenr); | |
1444 | qxl_rom_set_dirty(d); | |
1445 | } | |
1446 | ||
a8170e5e | 1447 | static void ioport_write(void *opaque, hwaddr addr, |
b1950430 | 1448 | uint64_t val, unsigned size) |
a19cbfb3 GH |
1449 | { |
1450 | PCIQXLDevice *d = opaque; | |
b1950430 | 1451 | uint32_t io_port = addr; |
5ff4e36c | 1452 | qxl_async_io async = QXL_SYNC; |
5ff4e36c | 1453 | uint32_t orig_io_port = io_port; |
a19cbfb3 | 1454 | |
d96aafca | 1455 | if (d->guest_bug && io_port != QXL_IO_RESET) { |
087e6a42 AL |
1456 | return; |
1457 | } | |
1458 | ||
020af1c4 | 1459 | if (d->revision <= QXL_REVISION_STABLE_V10 && |
ffe01e59 | 1460 | io_port > QXL_IO_FLUSH_RELEASE) { |
020af1c4 AL |
1461 | qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", |
1462 | io_port, d->revision); | |
1463 | return; | |
1464 | } | |
1465 | ||
a19cbfb3 GH |
1466 | switch (io_port) { |
1467 | case QXL_IO_RESET: | |
1468 | case QXL_IO_SET_MODE: | |
1469 | case QXL_IO_MEMSLOT_ADD: | |
1470 | case QXL_IO_MEMSLOT_DEL: | |
1471 | case QXL_IO_CREATE_PRIMARY: | |
81144d1a | 1472 | case QXL_IO_UPDATE_IRQ: |
a3d14054 | 1473 | case QXL_IO_LOG: |
5ff4e36c AL |
1474 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
1475 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
a19cbfb3 GH |
1476 | break; |
1477 | default: | |
e21a298a | 1478 | if (d->mode != QXL_MODE_VGA) { |
a19cbfb3 | 1479 | break; |
e21a298a | 1480 | } |
c480bb7d | 1481 | trace_qxl_io_unexpected_vga_mode(d->id, |
917ae08c | 1482 | addr, val, io_port_to_string(io_port)); |
5ff4e36c AL |
1483 | /* be nice to buggy guest drivers */ |
1484 | if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && | |
020af1c4 | 1485 | io_port < QXL_IO_RANGE_SIZE) { |
5ff4e36c AL |
1486 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); |
1487 | } | |
a19cbfb3 GH |
1488 | return; |
1489 | } | |
1490 | ||
5ff4e36c AL |
1491 | /* we change the io_port to avoid ifdeffery in the main switch */ |
1492 | orig_io_port = io_port; | |
1493 | switch (io_port) { | |
1494 | case QXL_IO_UPDATE_AREA_ASYNC: | |
1495 | io_port = QXL_IO_UPDATE_AREA; | |
1496 | goto async_common; | |
1497 | case QXL_IO_MEMSLOT_ADD_ASYNC: | |
1498 | io_port = QXL_IO_MEMSLOT_ADD; | |
1499 | goto async_common; | |
1500 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
1501 | io_port = QXL_IO_CREATE_PRIMARY; | |
1502 | goto async_common; | |
1503 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
1504 | io_port = QXL_IO_DESTROY_PRIMARY; | |
1505 | goto async_common; | |
1506 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
1507 | io_port = QXL_IO_DESTROY_SURFACE_WAIT; | |
1508 | goto async_common; | |
1509 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
1510 | io_port = QXL_IO_DESTROY_ALL_SURFACES; | |
3e16b9c5 AL |
1511 | goto async_common; |
1512 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
020af1c4 | 1513 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
5ff4e36c AL |
1514 | async_common: |
1515 | async = QXL_ASYNC; | |
1516 | qemu_mutex_lock(&d->async_lock); | |
1517 | if (d->current_async != QXL_UNDEFINED_IO) { | |
0a530548 | 1518 | qxl_set_guest_bug(d, "%d async started before last (%d) complete", |
5ff4e36c AL |
1519 | io_port, d->current_async); |
1520 | qemu_mutex_unlock(&d->async_lock); | |
1521 | return; | |
1522 | } | |
1523 | d->current_async = orig_io_port; | |
1524 | qemu_mutex_unlock(&d->async_lock); | |
5ff4e36c AL |
1525 | break; |
1526 | default: | |
1527 | break; | |
1528 | } | |
c480bb7d AL |
1529 | trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size, |
1530 | async); | |
5ff4e36c | 1531 | |
a19cbfb3 GH |
1532 | switch (io_port) { |
1533 | case QXL_IO_UPDATE_AREA: | |
1534 | { | |
81fb6f15 | 1535 | QXLCookie *cookie = NULL; |
a19cbfb3 | 1536 | QXLRect update = d->ram->update_area; |
81fb6f15 | 1537 | |
ddd8fdc7 | 1538 | if (d->ram->update_surface > d->ssd.num_surfaces) { |
511b13e2 AL |
1539 | qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", |
1540 | d->ram->update_surface); | |
36a03e0b | 1541 | break; |
511b13e2 | 1542 | } |
36a03e0b MT |
1543 | if (update.left >= update.right || update.top >= update.bottom || |
1544 | update.left < 0 || update.top < 0) { | |
511b13e2 AL |
1545 | qxl_set_guest_bug(d, |
1546 | "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", | |
1547 | update.left, update.top, update.right, update.bottom); | |
ccc2960d DH |
1548 | break; |
1549 | } | |
81fb6f15 AL |
1550 | if (async == QXL_ASYNC) { |
1551 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
1552 | QXL_IO_UPDATE_AREA_ASYNC); | |
1553 | cookie->u.area = update; | |
1554 | } | |
aee32bf3 | 1555 | qxl_spice_update_area(d, d->ram->update_surface, |
81fb6f15 AL |
1556 | cookie ? &cookie->u.area : &update, |
1557 | NULL, 0, 0, async, cookie); | |
a19cbfb3 GH |
1558 | break; |
1559 | } | |
1560 | case QXL_IO_NOTIFY_CMD: | |
5c59d118 | 1561 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1562 | break; |
1563 | case QXL_IO_NOTIFY_CURSOR: | |
5c59d118 | 1564 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1565 | break; |
1566 | case QXL_IO_UPDATE_IRQ: | |
40010aea | 1567 | qxl_update_irq(d); |
a19cbfb3 GH |
1568 | break; |
1569 | case QXL_IO_NOTIFY_OOM: | |
a19cbfb3 GH |
1570 | if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { |
1571 | break; | |
1572 | } | |
1573 | d->oom_running = 1; | |
aee32bf3 | 1574 | qxl_spice_oom(d); |
a19cbfb3 GH |
1575 | d->oom_running = 0; |
1576 | break; | |
1577 | case QXL_IO_SET_MODE: | |
a19cbfb3 GH |
1578 | qxl_set_mode(d, val, 0); |
1579 | break; | |
1580 | case QXL_IO_LOG: | |
1a1bc085 | 1581 | trace_qxl_io_log(d->id, d->ram->log_buf); |
a19cbfb3 | 1582 | if (d->guestdebug) { |
a680f7e7 | 1583 | fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, |
6ebebb55 | 1584 | qemu_get_clock_ns(vm_clock), d->ram->log_buf); |
a19cbfb3 GH |
1585 | } |
1586 | break; | |
1587 | case QXL_IO_RESET: | |
a19cbfb3 GH |
1588 | qxl_hard_reset(d, 0); |
1589 | break; | |
1590 | case QXL_IO_MEMSLOT_ADD: | |
2bce0400 | 1591 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1592 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); |
2bce0400 GH |
1593 | break; |
1594 | } | |
1595 | if (d->guest_slots[val].active) { | |
0a530548 AL |
1596 | qxl_set_guest_bug(d, |
1597 | "QXL_IO_MEMSLOT_ADD: memory slot already active"); | |
2bce0400 GH |
1598 | break; |
1599 | } | |
a19cbfb3 | 1600 | d->guest_slots[val].slot = d->ram->mem_slot; |
5ff4e36c | 1601 | qxl_add_memslot(d, val, 0, async); |
a19cbfb3 GH |
1602 | break; |
1603 | case QXL_IO_MEMSLOT_DEL: | |
2bce0400 | 1604 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1605 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); |
2bce0400 GH |
1606 | break; |
1607 | } | |
a19cbfb3 GH |
1608 | qxl_del_memslot(d, val); |
1609 | break; | |
1610 | case QXL_IO_CREATE_PRIMARY: | |
2bce0400 | 1611 | if (val != 0) { |
0a530548 | 1612 | qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1613 | async); |
1614 | goto cancel_async; | |
2bce0400 | 1615 | } |
a19cbfb3 | 1616 | d->guest_primary.surface = d->ram->create_surface; |
5ff4e36c | 1617 | qxl_create_guest_primary(d, 0, async); |
a19cbfb3 GH |
1618 | break; |
1619 | case QXL_IO_DESTROY_PRIMARY: | |
2bce0400 | 1620 | if (val != 0) { |
0a530548 | 1621 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1622 | async); |
1623 | goto cancel_async; | |
1624 | } | |
5ff4e36c | 1625 | if (!qxl_destroy_primary(d, async)) { |
c480bb7d AL |
1626 | trace_qxl_io_destroy_primary_ignored(d->id, |
1627 | qxl_mode_to_string(d->mode)); | |
5ff4e36c | 1628 | goto cancel_async; |
2bce0400 | 1629 | } |
a19cbfb3 GH |
1630 | break; |
1631 | case QXL_IO_DESTROY_SURFACE_WAIT: | |
ddd8fdc7 | 1632 | if (val >= d->ssd.num_surfaces) { |
0a530548 | 1633 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" |
5f8daf2e | 1634 | "%" PRIu64 " >= NUM_SURFACES", async, val); |
5ff4e36c AL |
1635 | goto cancel_async; |
1636 | } | |
1637 | qxl_spice_destroy_surface_wait(d, val, async); | |
a19cbfb3 | 1638 | break; |
3e16b9c5 AL |
1639 | case QXL_IO_FLUSH_RELEASE: { |
1640 | QXLReleaseRing *ring = &d->ram->release_ring; | |
1641 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
1642 | fprintf(stderr, | |
1643 | "ERROR: no flush, full release ring [p%d,%dc]\n", | |
1644 | ring->prod, ring->cons); | |
1645 | } | |
1646 | qxl_push_free_res(d, 1 /* flush */); | |
3e16b9c5 AL |
1647 | break; |
1648 | } | |
1649 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
3e16b9c5 AL |
1650 | qxl_spice_flush_surfaces_async(d); |
1651 | break; | |
a19cbfb3 | 1652 | case QXL_IO_DESTROY_ALL_SURFACES: |
5ff4e36c AL |
1653 | d->mode = QXL_MODE_UNDEFINED; |
1654 | qxl_spice_destroy_surfaces(d, async); | |
a19cbfb3 | 1655 | break; |
020af1c4 AL |
1656 | case QXL_IO_MONITORS_CONFIG_ASYNC: |
1657 | qxl_spice_monitors_config_async(d, 0); | |
1658 | break; | |
a19cbfb3 | 1659 | default: |
0a530548 | 1660 | qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); |
a19cbfb3 | 1661 | } |
5ff4e36c AL |
1662 | return; |
1663 | cancel_async: | |
5ff4e36c AL |
1664 | if (async) { |
1665 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); | |
1666 | qemu_mutex_lock(&d->async_lock); | |
1667 | d->current_async = QXL_UNDEFINED_IO; | |
1668 | qemu_mutex_unlock(&d->async_lock); | |
1669 | } | |
a19cbfb3 GH |
1670 | } |
1671 | ||
a8170e5e | 1672 | static uint64_t ioport_read(void *opaque, hwaddr addr, |
b1950430 | 1673 | unsigned size) |
a19cbfb3 | 1674 | { |
917ae08c | 1675 | PCIQXLDevice *qxl = opaque; |
a19cbfb3 | 1676 | |
917ae08c | 1677 | trace_qxl_io_read_unexpected(qxl->id); |
a19cbfb3 GH |
1678 | return 0xff; |
1679 | } | |
1680 | ||
b1950430 AK |
1681 | static const MemoryRegionOps qxl_io_ops = { |
1682 | .read = ioport_read, | |
1683 | .write = ioport_write, | |
1684 | .valid = { | |
1685 | .min_access_size = 1, | |
1686 | .max_access_size = 1, | |
1687 | }, | |
1688 | }; | |
a19cbfb3 GH |
1689 | |
1690 | static void pipe_read(void *opaque) | |
1691 | { | |
1692 | PCIQXLDevice *d = opaque; | |
1693 | char dummy; | |
1694 | int len; | |
1695 | ||
1696 | do { | |
1697 | len = read(d->pipe[0], &dummy, sizeof(dummy)); | |
1698 | } while (len == sizeof(dummy)); | |
40010aea | 1699 | qxl_update_irq(d); |
a19cbfb3 GH |
1700 | } |
1701 | ||
a19cbfb3 GH |
1702 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
1703 | { | |
1704 | uint32_t old_pending; | |
1705 | uint32_t le_events = cpu_to_le32(events); | |
1706 | ||
917ae08c | 1707 | trace_qxl_send_events(d->id, events); |
511aefb0 AL |
1708 | if (!qemu_spice_display_is_running(&d->ssd)) { |
1709 | /* spice-server tracks guest running state and should not do this */ | |
1710 | fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", | |
1711 | __func__); | |
1712 | trace_qxl_send_events_vm_stopped(d->id, events); | |
1713 | return; | |
1714 | } | |
a19cbfb3 GH |
1715 | old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); |
1716 | if ((old_pending & le_events) == le_events) { | |
1717 | return; | |
1718 | } | |
691f5c7b | 1719 | if (qemu_thread_is_self(&d->main)) { |
40010aea | 1720 | qxl_update_irq(d); |
a19cbfb3 GH |
1721 | } else { |
1722 | if (write(d->pipe[1], d, 1) != 1) { | |
75fe0d7b | 1723 | dprint(d, 1, "%s: write to pipe failed\n", __func__); |
a19cbfb3 GH |
1724 | } |
1725 | } | |
1726 | } | |
1727 | ||
1728 | static void init_pipe_signaling(PCIQXLDevice *d) | |
1729 | { | |
aa3db423 AL |
1730 | if (pipe(d->pipe) < 0) { |
1731 | fprintf(stderr, "%s:%s: qxl pipe creation failed\n", | |
1732 | __FILE__, __func__); | |
1733 | exit(1); | |
1734 | } | |
1735 | fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); | |
1736 | fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); | |
1737 | fcntl(d->pipe[0], F_SETOWN, getpid()); | |
1738 | ||
1739 | qemu_thread_get_self(&d->main); | |
1740 | qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); | |
a19cbfb3 GH |
1741 | } |
1742 | ||
1743 | /* graphics console */ | |
1744 | ||
1745 | static void qxl_hw_update(void *opaque) | |
1746 | { | |
1747 | PCIQXLDevice *qxl = opaque; | |
1748 | VGACommonState *vga = &qxl->vga; | |
1749 | ||
1750 | switch (qxl->mode) { | |
1751 | case QXL_MODE_VGA: | |
1752 | vga->update(vga); | |
1753 | break; | |
1754 | case QXL_MODE_COMPAT: | |
1755 | case QXL_MODE_NATIVE: | |
1756 | qxl_render_update(qxl); | |
1757 | break; | |
1758 | default: | |
1759 | break; | |
1760 | } | |
1761 | } | |
1762 | ||
1763 | static void qxl_hw_invalidate(void *opaque) | |
1764 | { | |
1765 | PCIQXLDevice *qxl = opaque; | |
1766 | VGACommonState *vga = &qxl->vga; | |
1767 | ||
1768 | vga->invalidate(vga); | |
1769 | } | |
1770 | ||
d7098135 LC |
1771 | static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch, |
1772 | Error **errp) | |
a19cbfb3 GH |
1773 | { |
1774 | PCIQXLDevice *qxl = opaque; | |
1775 | VGACommonState *vga = &qxl->vga; | |
1776 | ||
1777 | switch (qxl->mode) { | |
1778 | case QXL_MODE_COMPAT: | |
1779 | case QXL_MODE_NATIVE: | |
1780 | qxl_render_update(qxl); | |
d663174d | 1781 | ppm_save(filename, qxl->ssd.ds->surface, errp); |
a19cbfb3 GH |
1782 | break; |
1783 | case QXL_MODE_VGA: | |
d7098135 | 1784 | vga->screen_dump(vga, filename, cswitch, errp); |
a19cbfb3 GH |
1785 | break; |
1786 | default: | |
1787 | break; | |
1788 | } | |
1789 | } | |
1790 | ||
1791 | static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) | |
1792 | { | |
1793 | PCIQXLDevice *qxl = opaque; | |
1794 | VGACommonState *vga = &qxl->vga; | |
1795 | ||
1796 | if (qxl->mode == QXL_MODE_VGA) { | |
1797 | vga->text_update(vga, chardata); | |
1798 | return; | |
1799 | } | |
1800 | } | |
1801 | ||
e25139b3 YH |
1802 | static void qxl_dirty_surfaces(PCIQXLDevice *qxl) |
1803 | { | |
c5825ac6 | 1804 | uintptr_t vram_start; |
e25139b3 YH |
1805 | int i; |
1806 | ||
2aa9e85c | 1807 | if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { |
e25139b3 YH |
1808 | return; |
1809 | } | |
1810 | ||
1811 | /* dirty the primary surface */ | |
1812 | qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, | |
1813 | qxl->shadow_rom.surface0_area_size); | |
1814 | ||
c5825ac6 | 1815 | vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); |
e25139b3 YH |
1816 | |
1817 | /* dirty the off-screen surfaces */ | |
ddd8fdc7 | 1818 | for (i = 0; i < qxl->ssd.num_surfaces; i++) { |
e25139b3 YH |
1819 | QXLSurfaceCmd *cmd; |
1820 | intptr_t surface_offset; | |
1821 | int surface_size; | |
1822 | ||
1823 | if (qxl->guest_surfaces.cmds[i] == 0) { | |
1824 | continue; | |
1825 | } | |
1826 | ||
1827 | cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], | |
1828 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1829 | assert(cmd); |
e25139b3 YH |
1830 | assert(cmd->type == QXL_SURFACE_CMD_CREATE); |
1831 | surface_offset = (intptr_t)qxl_phys2virt(qxl, | |
1832 | cmd->u.surface_create.data, | |
1833 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1834 | assert(surface_offset); |
e25139b3 YH |
1835 | surface_offset -= vram_start; |
1836 | surface_size = cmd->u.surface_create.height * | |
1837 | abs(cmd->u.surface_create.stride); | |
c480bb7d | 1838 | trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); |
e25139b3 YH |
1839 | qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); |
1840 | } | |
1841 | } | |
1842 | ||
1dfb4dd9 LC |
1843 | static void qxl_vm_change_state_handler(void *opaque, int running, |
1844 | RunState state) | |
a19cbfb3 GH |
1845 | { |
1846 | PCIQXLDevice *qxl = opaque; | |
a19cbfb3 | 1847 | |
efbf2950 YH |
1848 | if (running) { |
1849 | /* | |
1850 | * if qxl_send_events was called from spice server context before | |
40010aea | 1851 | * migration ended, qxl_update_irq for these events might not have been |
efbf2950 YH |
1852 | * called |
1853 | */ | |
40010aea | 1854 | qxl_update_irq(qxl); |
e25139b3 YH |
1855 | } else { |
1856 | /* make sure surfaces are saved before migration */ | |
1857 | qxl_dirty_surfaces(qxl); | |
a19cbfb3 GH |
1858 | } |
1859 | } | |
1860 | ||
1861 | /* display change listener */ | |
1862 | ||
1863 | static void display_update(struct DisplayState *ds, int x, int y, int w, int h) | |
1864 | { | |
1865 | if (qxl0->mode == QXL_MODE_VGA) { | |
1866 | qemu_spice_display_update(&qxl0->ssd, x, y, w, h); | |
1867 | } | |
1868 | } | |
1869 | ||
1870 | static void display_resize(struct DisplayState *ds) | |
1871 | { | |
1872 | if (qxl0->mode == QXL_MODE_VGA) { | |
1873 | qemu_spice_display_resize(&qxl0->ssd); | |
1874 | } | |
1875 | } | |
1876 | ||
1877 | static void display_refresh(struct DisplayState *ds) | |
1878 | { | |
1879 | if (qxl0->mode == QXL_MODE_VGA) { | |
1880 | qemu_spice_display_refresh(&qxl0->ssd); | |
bb5a8cd5 AL |
1881 | } else { |
1882 | qemu_mutex_lock(&qxl0->ssd.lock); | |
1883 | qemu_spice_cursor_refresh_unlocked(&qxl0->ssd); | |
1884 | qemu_mutex_unlock(&qxl0->ssd.lock); | |
a19cbfb3 GH |
1885 | } |
1886 | } | |
1887 | ||
1888 | static DisplayChangeListener display_listener = { | |
a93a4a22 GH |
1889 | .dpy_gfx_update = display_update, |
1890 | .dpy_gfx_resize = display_resize, | |
a19cbfb3 GH |
1891 | .dpy_refresh = display_refresh, |
1892 | }; | |
1893 | ||
13d1fd44 | 1894 | static void qxl_init_ramsize(PCIQXLDevice *qxl) |
a974192c | 1895 | { |
13d1fd44 AL |
1896 | /* vga mode framebuffer / primary surface (bar 0, first part) */ |
1897 | if (qxl->vgamem_size_mb < 8) { | |
1898 | qxl->vgamem_size_mb = 8; | |
1899 | } | |
1900 | qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; | |
1901 | ||
1902 | /* vga ram (bar 0, total) */ | |
017438ee GH |
1903 | if (qxl->ram_size_mb != -1) { |
1904 | qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; | |
1905 | } | |
13d1fd44 AL |
1906 | if (qxl->vga.vram_size < qxl->vgamem_size * 2) { |
1907 | qxl->vga.vram_size = qxl->vgamem_size * 2; | |
a974192c GH |
1908 | } |
1909 | ||
6f2b175a GH |
1910 | /* vram32 (surfaces, 32bit, bar 1) */ |
1911 | if (qxl->vram32_size_mb != -1) { | |
1912 | qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; | |
1913 | } | |
1914 | if (qxl->vram32_size < 4096) { | |
1915 | qxl->vram32_size = 4096; | |
1916 | } | |
1917 | ||
1918 | /* vram (surfaces, 64bit, bar 4+5) */ | |
017438ee GH |
1919 | if (qxl->vram_size_mb != -1) { |
1920 | qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; | |
1921 | } | |
6f2b175a GH |
1922 | if (qxl->vram_size < qxl->vram32_size) { |
1923 | qxl->vram_size = qxl->vram32_size; | |
a974192c | 1924 | } |
6f2b175a | 1925 | |
a974192c | 1926 | if (qxl->revision == 1) { |
6f2b175a | 1927 | qxl->vram32_size = 4096; |
a974192c GH |
1928 | qxl->vram_size = 4096; |
1929 | } | |
13d1fd44 | 1930 | qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1); |
a974192c | 1931 | qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
6f2b175a | 1932 | qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); |
a974192c GH |
1933 | qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); |
1934 | } | |
1935 | ||
a19cbfb3 GH |
1936 | static int qxl_init_common(PCIQXLDevice *qxl) |
1937 | { | |
1938 | uint8_t* config = qxl->pci.config; | |
a19cbfb3 GH |
1939 | uint32_t pci_device_rev; |
1940 | uint32_t io_size; | |
1941 | ||
1942 | qxl->mode = QXL_MODE_UNDEFINED; | |
1943 | qxl->generation = 1; | |
1944 | qxl->num_memslots = NUM_MEMSLOTS; | |
14898cf6 | 1945 | qemu_mutex_init(&qxl->track_lock); |
5ff4e36c AL |
1946 | qemu_mutex_init(&qxl->async_lock); |
1947 | qxl->current_async = QXL_UNDEFINED_IO; | |
087e6a42 | 1948 | qxl->guest_bug = 0; |
a19cbfb3 GH |
1949 | |
1950 | switch (qxl->revision) { | |
1951 | case 1: /* spice 0.4 -- qxl-1 */ | |
a19cbfb3 | 1952 | pci_device_rev = QXL_REVISION_STABLE_V04; |
3f6297b9 | 1953 | io_size = 8; |
a19cbfb3 GH |
1954 | break; |
1955 | case 2: /* spice 0.6 -- qxl-2 */ | |
a19cbfb3 | 1956 | pci_device_rev = QXL_REVISION_STABLE_V06; |
3f6297b9 | 1957 | io_size = 16; |
a19cbfb3 | 1958 | break; |
9197a7c8 | 1959 | case 3: /* qxl-3 */ |
020af1c4 AL |
1960 | pci_device_rev = QXL_REVISION_STABLE_V10; |
1961 | io_size = 32; /* PCI region size must be pow2 */ | |
1962 | break; | |
020af1c4 AL |
1963 | case 4: /* qxl-4 */ |
1964 | pci_device_rev = QXL_REVISION_STABLE_V12; | |
3f6297b9 | 1965 | io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); |
9197a7c8 | 1966 | break; |
36839d35 AL |
1967 | default: |
1968 | error_report("Invalid revision %d for qxl device (max %d)", | |
1969 | qxl->revision, QXL_DEFAULT_REVISION); | |
1970 | return -1; | |
a19cbfb3 GH |
1971 | } |
1972 | ||
a19cbfb3 GH |
1973 | pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1974 | pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); | |
1975 | ||
1976 | qxl->rom_size = qxl_rom_size(); | |
c5705a77 AK |
1977 | memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size); |
1978 | vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); | |
a19cbfb3 GH |
1979 | init_qxl_rom(qxl); |
1980 | init_qxl_ram(qxl); | |
1981 | ||
ddd8fdc7 | 1982 | qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); |
c5705a77 AK |
1983 | memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size); |
1984 | vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); | |
6f2b175a GH |
1985 | memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar, |
1986 | 0, qxl->vram32_size); | |
a19cbfb3 | 1987 | |
b1950430 AK |
1988 | memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, |
1989 | "qxl-ioports", io_size); | |
1990 | if (qxl->id == 0) { | |
1991 | vga_dirty_log_start(&qxl->vga); | |
1992 | } | |
bd8f2f5d | 1993 | memory_region_set_flush_coalesced(&qxl->io_bar); |
b1950430 AK |
1994 | |
1995 | ||
e824b2cc AK |
1996 | pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
1997 | PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); | |
a19cbfb3 | 1998 | |
e824b2cc AK |
1999 | pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
2000 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); | |
a19cbfb3 | 2001 | |
e824b2cc AK |
2002 | pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
2003 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); | |
a19cbfb3 | 2004 | |
e824b2cc | 2005 | pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, |
6f2b175a GH |
2006 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); |
2007 | ||
2008 | if (qxl->vram32_size < qxl->vram_size) { | |
2009 | /* | |
2010 | * Make the 64bit vram bar show up only in case it is | |
2011 | * configured to be larger than the 32bit vram bar. | |
2012 | */ | |
2013 | pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, | |
2014 | PCI_BASE_ADDRESS_SPACE_MEMORY | | |
2015 | PCI_BASE_ADDRESS_MEM_TYPE_64 | | |
2016 | PCI_BASE_ADDRESS_MEM_PREFETCH, | |
2017 | &qxl->vram_bar); | |
2018 | } | |
2019 | ||
2020 | /* print pci bar details */ | |
2021 | dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", | |
2022 | qxl->id == 0 ? "pri" : "sec", | |
2023 | qxl->vga.vram_size / (1024*1024)); | |
2024 | dprint(qxl, 1, "vram/32: %d MB [region 1]\n", | |
2025 | qxl->vram32_size / (1024*1024)); | |
2026 | dprint(qxl, 1, "vram/64: %d MB %s\n", | |
2027 | qxl->vram_size / (1024*1024), | |
2028 | qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); | |
a19cbfb3 GH |
2029 | |
2030 | qxl->ssd.qxl.base.sif = &qxl_interface.base; | |
2031 | qxl->ssd.qxl.id = qxl->id; | |
e25a0651 AL |
2032 | if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) { |
2033 | error_report("qxl interface %d.%d not supported by spice-server\n", | |
2034 | SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); | |
2035 | return -1; | |
2036 | } | |
a19cbfb3 GH |
2037 | qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); |
2038 | ||
2039 | init_pipe_signaling(qxl); | |
2040 | qxl_reset_state(qxl); | |
2041 | ||
81fb6f15 AL |
2042 | qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); |
2043 | ||
a19cbfb3 GH |
2044 | return 0; |
2045 | } | |
2046 | ||
2047 | static int qxl_init_primary(PCIDevice *dev) | |
2048 | { | |
2049 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
2050 | VGACommonState *vga = &qxl->vga; | |
f67ab77a | 2051 | PortioList *qxl_vga_port_list = g_new(PortioList, 1); |
bdd4df33 | 2052 | int rc; |
a19cbfb3 GH |
2053 | |
2054 | qxl->id = 0; | |
13d1fd44 | 2055 | qxl_init_ramsize(qxl); |
4a1e244e GH |
2056 | vga->vram_size_mb = qxl->vga.vram_size >> 20; |
2057 | vga_common_init(vga); | |
0a039dc7 | 2058 | vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); |
f67ab77a GH |
2059 | portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); |
2060 | portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); | |
a19cbfb3 GH |
2061 | |
2062 | vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, | |
2063 | qxl_hw_screen_dump, qxl_hw_text_update, qxl); | |
a963f876 | 2064 | qemu_spice_display_init_common(&qxl->ssd, vga->ds); |
a19cbfb3 GH |
2065 | |
2066 | qxl0 = qxl; | |
a19cbfb3 | 2067 | |
bdd4df33 GH |
2068 | rc = qxl_init_common(qxl); |
2069 | if (rc != 0) { | |
2070 | return rc; | |
2071 | } | |
2072 | ||
2073 | register_displaychangelistener(vga->ds, &display_listener); | |
2074 | return rc; | |
a19cbfb3 GH |
2075 | } |
2076 | ||
2077 | static int qxl_init_secondary(PCIDevice *dev) | |
2078 | { | |
2079 | static int device_id = 1; | |
2080 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
a19cbfb3 GH |
2081 | |
2082 | qxl->id = device_id++; | |
13d1fd44 | 2083 | qxl_init_ramsize(qxl); |
c5705a77 AK |
2084 | memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); |
2085 | vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); | |
b1950430 | 2086 | qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); |
a19cbfb3 | 2087 | |
a19cbfb3 GH |
2088 | return qxl_init_common(qxl); |
2089 | } | |
2090 | ||
2091 | static void qxl_pre_save(void *opaque) | |
2092 | { | |
2093 | PCIQXLDevice* d = opaque; | |
2094 | uint8_t *ram_start = d->vga.vram_ptr; | |
2095 | ||
c480bb7d | 2096 | trace_qxl_pre_save(d->id); |
a19cbfb3 GH |
2097 | if (d->last_release == NULL) { |
2098 | d->last_release_offset = 0; | |
2099 | } else { | |
2100 | d->last_release_offset = (uint8_t *)d->last_release - ram_start; | |
2101 | } | |
2102 | assert(d->last_release_offset < d->vga.vram_size); | |
2103 | } | |
2104 | ||
2105 | static int qxl_pre_load(void *opaque) | |
2106 | { | |
2107 | PCIQXLDevice* d = opaque; | |
2108 | ||
c480bb7d | 2109 | trace_qxl_pre_load(d->id); |
a19cbfb3 GH |
2110 | qxl_hard_reset(d, 1); |
2111 | qxl_exit_vga_mode(d); | |
a19cbfb3 GH |
2112 | return 0; |
2113 | } | |
2114 | ||
54825d2e AL |
2115 | static void qxl_create_memslots(PCIQXLDevice *d) |
2116 | { | |
2117 | int i; | |
2118 | ||
2119 | for (i = 0; i < NUM_MEMSLOTS; i++) { | |
2120 | if (!d->guest_slots[i].active) { | |
2121 | continue; | |
2122 | } | |
54825d2e AL |
2123 | qxl_add_memslot(d, i, 0, QXL_SYNC); |
2124 | } | |
2125 | } | |
2126 | ||
a19cbfb3 GH |
2127 | static int qxl_post_load(void *opaque, int version) |
2128 | { | |
2129 | PCIQXLDevice* d = opaque; | |
2130 | uint8_t *ram_start = d->vga.vram_ptr; | |
2131 | QXLCommandExt *cmds; | |
54825d2e | 2132 | int in, out, newmode; |
a19cbfb3 | 2133 | |
a19cbfb3 GH |
2134 | assert(d->last_release_offset < d->vga.vram_size); |
2135 | if (d->last_release_offset == 0) { | |
2136 | d->last_release = NULL; | |
2137 | } else { | |
2138 | d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); | |
2139 | } | |
2140 | ||
2141 | d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); | |
2142 | ||
c480bb7d | 2143 | trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); |
a19cbfb3 GH |
2144 | newmode = d->mode; |
2145 | d->mode = QXL_MODE_UNDEFINED; | |
54825d2e | 2146 | |
a19cbfb3 GH |
2147 | switch (newmode) { |
2148 | case QXL_MODE_UNDEFINED: | |
fa98efe9 | 2149 | qxl_create_memslots(d); |
a19cbfb3 GH |
2150 | break; |
2151 | case QXL_MODE_VGA: | |
54825d2e | 2152 | qxl_create_memslots(d); |
a19cbfb3 GH |
2153 | qxl_enter_vga_mode(d); |
2154 | break; | |
2155 | case QXL_MODE_NATIVE: | |
54825d2e | 2156 | qxl_create_memslots(d); |
5ff4e36c | 2157 | qxl_create_guest_primary(d, 1, QXL_SYNC); |
a19cbfb3 GH |
2158 | |
2159 | /* replay surface-create and cursor-set commands */ | |
ddd8fdc7 GH |
2160 | cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); |
2161 | for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { | |
a19cbfb3 GH |
2162 | if (d->guest_surfaces.cmds[in] == 0) { |
2163 | continue; | |
2164 | } | |
2165 | cmds[out].cmd.data = d->guest_surfaces.cmds[in]; | |
2166 | cmds[out].cmd.type = QXL_CMD_SURFACE; | |
2167 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
2168 | out++; | |
2169 | } | |
30f6da66 YH |
2170 | if (d->guest_cursor) { |
2171 | cmds[out].cmd.data = d->guest_cursor; | |
2172 | cmds[out].cmd.type = QXL_CMD_CURSOR; | |
2173 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
2174 | out++; | |
2175 | } | |
aee32bf3 | 2176 | qxl_spice_loadvm_commands(d, cmds, out); |
7267c094 | 2177 | g_free(cmds); |
020af1c4 AL |
2178 | if (d->guest_monitors_config) { |
2179 | qxl_spice_monitors_config_async(d, 1); | |
2180 | } | |
a19cbfb3 GH |
2181 | break; |
2182 | case QXL_MODE_COMPAT: | |
54825d2e AL |
2183 | /* note: no need to call qxl_create_memslots, qxl_set_mode |
2184 | * creates the mem slot. */ | |
a19cbfb3 GH |
2185 | qxl_set_mode(d, d->shadow_rom.mode, 1); |
2186 | break; | |
2187 | } | |
a19cbfb3 GH |
2188 | return 0; |
2189 | } | |
2190 | ||
b67737a6 | 2191 | #define QXL_SAVE_VERSION 21 |
a19cbfb3 | 2192 | |
020af1c4 AL |
2193 | static bool qxl_monitors_config_needed(void *opaque) |
2194 | { | |
2195 | PCIQXLDevice *qxl = opaque; | |
2196 | ||
2197 | return qxl->guest_monitors_config != 0; | |
2198 | } | |
2199 | ||
2200 | ||
a19cbfb3 GH |
2201 | static VMStateDescription qxl_memslot = { |
2202 | .name = "qxl-memslot", | |
2203 | .version_id = QXL_SAVE_VERSION, | |
2204 | .minimum_version_id = QXL_SAVE_VERSION, | |
2205 | .fields = (VMStateField[]) { | |
2206 | VMSTATE_UINT64(slot.mem_start, struct guest_slots), | |
2207 | VMSTATE_UINT64(slot.mem_end, struct guest_slots), | |
2208 | VMSTATE_UINT32(active, struct guest_slots), | |
2209 | VMSTATE_END_OF_LIST() | |
2210 | } | |
2211 | }; | |
2212 | ||
2213 | static VMStateDescription qxl_surface = { | |
2214 | .name = "qxl-surface", | |
2215 | .version_id = QXL_SAVE_VERSION, | |
2216 | .minimum_version_id = QXL_SAVE_VERSION, | |
2217 | .fields = (VMStateField[]) { | |
2218 | VMSTATE_UINT32(width, QXLSurfaceCreate), | |
2219 | VMSTATE_UINT32(height, QXLSurfaceCreate), | |
2220 | VMSTATE_INT32(stride, QXLSurfaceCreate), | |
2221 | VMSTATE_UINT32(format, QXLSurfaceCreate), | |
2222 | VMSTATE_UINT32(position, QXLSurfaceCreate), | |
2223 | VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), | |
2224 | VMSTATE_UINT32(flags, QXLSurfaceCreate), | |
2225 | VMSTATE_UINT32(type, QXLSurfaceCreate), | |
2226 | VMSTATE_UINT64(mem, QXLSurfaceCreate), | |
2227 | VMSTATE_END_OF_LIST() | |
2228 | } | |
2229 | }; | |
2230 | ||
020af1c4 AL |
2231 | static VMStateDescription qxl_vmstate_monitors_config = { |
2232 | .name = "qxl/monitors-config", | |
2233 | .version_id = 1, | |
2234 | .minimum_version_id = 1, | |
2235 | .fields = (VMStateField[]) { | |
2236 | VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), | |
2237 | VMSTATE_END_OF_LIST() | |
2238 | }, | |
2239 | }; | |
2240 | ||
a19cbfb3 GH |
2241 | static VMStateDescription qxl_vmstate = { |
2242 | .name = "qxl", | |
2243 | .version_id = QXL_SAVE_VERSION, | |
2244 | .minimum_version_id = QXL_SAVE_VERSION, | |
2245 | .pre_save = qxl_pre_save, | |
2246 | .pre_load = qxl_pre_load, | |
2247 | .post_load = qxl_post_load, | |
020af1c4 | 2248 | .fields = (VMStateField[]) { |
a19cbfb3 GH |
2249 | VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), |
2250 | VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), | |
2251 | VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), | |
2252 | VMSTATE_UINT32(num_free_res, PCIQXLDevice), | |
2253 | VMSTATE_UINT32(last_release_offset, PCIQXLDevice), | |
2254 | VMSTATE_UINT32(mode, PCIQXLDevice), | |
2255 | VMSTATE_UINT32(ssd.unique, PCIQXLDevice), | |
b67737a6 GH |
2256 | VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
2257 | VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, | |
2258 | qxl_memslot, struct guest_slots), | |
2259 | VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, | |
2260 | qxl_surface, QXLSurfaceCreate), | |
ddd8fdc7 GH |
2261 | VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), |
2262 | VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, | |
2263 | ssd.num_surfaces, 0, | |
2264 | vmstate_info_uint64, uint64_t), | |
b67737a6 | 2265 | VMSTATE_UINT64(guest_cursor, PCIQXLDevice), |
a19cbfb3 GH |
2266 | VMSTATE_END_OF_LIST() |
2267 | }, | |
020af1c4 AL |
2268 | .subsections = (VMStateSubsection[]) { |
2269 | { | |
2270 | .vmsd = &qxl_vmstate_monitors_config, | |
2271 | .needed = qxl_monitors_config_needed, | |
2272 | }, { | |
2273 | /* empty */ | |
2274 | } | |
2275 | } | |
a19cbfb3 GH |
2276 | }; |
2277 | ||
78e60ba5 GH |
2278 | static Property qxl_properties[] = { |
2279 | DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, | |
2280 | 64 * 1024 * 1024), | |
6f2b175a | 2281 | DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, |
78e60ba5 GH |
2282 | 64 * 1024 * 1024), |
2283 | DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, | |
2284 | QXL_DEFAULT_REVISION), | |
2285 | DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), | |
2286 | DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), | |
2287 | DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), | |
017438ee | 2288 | DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), |
79ce3567 AL |
2289 | DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), |
2290 | DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), | |
9e56edcf | 2291 | DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), |
ddd8fdc7 | 2292 | DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), |
78e60ba5 GH |
2293 | DEFINE_PROP_END_OF_LIST(), |
2294 | }; | |
2295 | ||
40021f08 AL |
2296 | static void qxl_primary_class_init(ObjectClass *klass, void *data) |
2297 | { | |
39bffca2 | 2298 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2299 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2300 | ||
2301 | k->no_hotplug = 1; | |
2302 | k->init = qxl_init_primary; | |
2303 | k->romfile = "vgabios-qxl.bin"; | |
2304 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2305 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2306 | k->class_id = PCI_CLASS_DISPLAY_VGA; | |
39bffca2 AL |
2307 | dc->desc = "Spice QXL GPU (primary, vga compatible)"; |
2308 | dc->reset = qxl_reset_handler; | |
2309 | dc->vmsd = &qxl_vmstate; | |
2310 | dc->props = qxl_properties; | |
40021f08 AL |
2311 | } |
2312 | ||
39bffca2 AL |
2313 | static TypeInfo qxl_primary_info = { |
2314 | .name = "qxl-vga", | |
2315 | .parent = TYPE_PCI_DEVICE, | |
2316 | .instance_size = sizeof(PCIQXLDevice), | |
2317 | .class_init = qxl_primary_class_init, | |
a19cbfb3 GH |
2318 | }; |
2319 | ||
40021f08 AL |
2320 | static void qxl_secondary_class_init(ObjectClass *klass, void *data) |
2321 | { | |
39bffca2 | 2322 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2323 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2324 | ||
2325 | k->init = qxl_init_secondary; | |
2326 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2327 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2328 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
39bffca2 AL |
2329 | dc->desc = "Spice QXL GPU (secondary)"; |
2330 | dc->reset = qxl_reset_handler; | |
2331 | dc->vmsd = &qxl_vmstate; | |
2332 | dc->props = qxl_properties; | |
40021f08 AL |
2333 | } |
2334 | ||
39bffca2 AL |
2335 | static TypeInfo qxl_secondary_info = { |
2336 | .name = "qxl", | |
2337 | .parent = TYPE_PCI_DEVICE, | |
2338 | .instance_size = sizeof(PCIQXLDevice), | |
2339 | .class_init = qxl_secondary_class_init, | |
a19cbfb3 GH |
2340 | }; |
2341 | ||
83f7d43a | 2342 | static void qxl_register_types(void) |
a19cbfb3 | 2343 | { |
39bffca2 AL |
2344 | type_register_static(&qxl_primary_info); |
2345 | type_register_static(&qxl_secondary_info); | |
a19cbfb3 GH |
2346 | } |
2347 | ||
83f7d43a | 2348 | type_init(qxl_register_types) |