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0d78f544 TS |
1 | /* |
2 | * Renesas SH7751R R2D-PLUS emulation | |
3 | * | |
4 | * Copyright (c) 2007 Magnus Damm | |
b319feb7 | 5 | * Copyright (c) 2008 Paul Mundt |
0d78f544 TS |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
cf154394 | 26 | #include "sysbus.h" |
87ecb68b PB |
27 | #include "hw.h" |
28 | #include "sh.h" | |
ffd39257 | 29 | #include "devices.h" |
87ecb68b PB |
30 | #include "sysemu.h" |
31 | #include "boards.h" | |
c2f01775 AZ |
32 | #include "pci.h" |
33 | #include "net.h" | |
34 | #include "sh7750_regs.h" | |
3d2bf4a1 | 35 | #include "ide.h" |
ca20cf32 | 36 | #include "loader.h" |
9caa3ec1 | 37 | #include "usb.h" |
56839a19 | 38 | #include "flash.h" |
2446333c | 39 | #include "blockdev.h" |
27a9d2ea | 40 | #include "exec-memory.h" |
56839a19 AJ |
41 | |
42 | #define FLASH_BASE 0x00000000 | |
43 | #define FLASH_SIZE 0x02000000 | |
0d78f544 TS |
44 | |
45 | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ | |
46 | #define SDRAM_SIZE 0x04000000 | |
47 | ||
ffd39257 BS |
48 | #define SM501_VRAM_SIZE 0x800000 |
49 | ||
73f19035 | 50 | #define BOOT_PARAMS_OFFSET 0x0010000 |
e8afa065 | 51 | /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */ |
73f19035 AJ |
52 | #define LINUX_LOAD_OFFSET 0x0800000 |
53 | #define INITRD_LOAD_OFFSET 0x1800000 | |
e8afa065 | 54 | |
d47ede60 | 55 | #define PA_IRLMSK 0x00 |
b319feb7 AJ |
56 | #define PA_POWOFF 0x30 |
57 | #define PA_VERREG 0x32 | |
58 | #define PA_OUTPORT 0x36 | |
59 | ||
60 | typedef struct { | |
b319feb7 | 61 | uint16_t bcr; |
d47ede60 | 62 | uint16_t irlmsk; |
b319feb7 AJ |
63 | uint16_t irlmon; |
64 | uint16_t cfctl; | |
65 | uint16_t cfpow; | |
66 | uint16_t dispctl; | |
67 | uint16_t sdmpow; | |
68 | uint16_t rtcce; | |
69 | uint16_t pcicd; | |
70 | uint16_t voyagerrts; | |
71 | uint16_t cfrst; | |
72 | uint16_t admrts; | |
73 | uint16_t extrst; | |
74 | uint16_t cfcdintclr; | |
75 | uint16_t keyctlclr; | |
76 | uint16_t pad0; | |
77 | uint16_t pad1; | |
b319feb7 AJ |
78 | uint16_t verreg; |
79 | uint16_t inport; | |
80 | uint16_t outport; | |
81 | uint16_t bverreg; | |
d47ede60 AZ |
82 | |
83 | /* output pin */ | |
84 | qemu_irq irl; | |
c227f099 | 85 | } r2d_fpga_t; |
b319feb7 | 86 | |
d47ede60 AZ |
87 | enum r2d_fpga_irq { |
88 | PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, | |
89 | SDCARD, PCI_INTA, PCI_INTB, EXT, TP, | |
90 | NR_IRQS | |
91 | }; | |
92 | ||
93 | static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { | |
94 | [CF_IDE] = { 1, 1<<9 }, | |
95 | [CF_CD] = { 2, 1<<8 }, | |
96 | [PCI_INTA] = { 9, 1<<14 }, | |
97 | [PCI_INTB] = { 10, 1<<13 }, | |
98 | [PCI_INTC] = { 3, 1<<12 }, | |
99 | [PCI_INTD] = { 0, 1<<11 }, | |
100 | [SM501] = { 4, 1<<10 }, | |
101 | [KEY] = { 5, 1<<6 }, | |
102 | [RTC_A] = { 6, 1<<5 }, | |
103 | [RTC_T] = { 7, 1<<4 }, | |
104 | [SDCARD] = { 8, 1<<7 }, | |
105 | [EXT] = { 11, 1<<0 }, | |
106 | [TP] = { 12, 1<<15 }, | |
107 | }; | |
108 | ||
c227f099 | 109 | static void update_irl(r2d_fpga_t *fpga) |
d47ede60 AZ |
110 | { |
111 | int i, irl = 15; | |
112 | for (i = 0; i < NR_IRQS; i++) | |
113 | if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk) | |
114 | if (irqtab[i].irl < irl) | |
115 | irl = irqtab[i].irl; | |
116 | qemu_set_irq(fpga->irl, irl ^ 15); | |
117 | } | |
118 | ||
119 | static void r2d_fpga_irq_set(void *opaque, int n, int level) | |
120 | { | |
c227f099 | 121 | r2d_fpga_t *fpga = opaque; |
d47ede60 AZ |
122 | if (level) |
123 | fpga->irlmon |= irqtab[n].msk; | |
124 | else | |
125 | fpga->irlmon &= ~irqtab[n].msk; | |
126 | update_irl(fpga); | |
127 | } | |
128 | ||
c227f099 | 129 | static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
b319feb7 | 130 | { |
c227f099 | 131 | r2d_fpga_t *s = opaque; |
b319feb7 | 132 | |
b319feb7 | 133 | switch (addr) { |
d47ede60 AZ |
134 | case PA_IRLMSK: |
135 | return s->irlmsk; | |
b319feb7 AJ |
136 | case PA_OUTPORT: |
137 | return s->outport; | |
138 | case PA_POWOFF: | |
37cc0b44 | 139 | return 0x00; |
b319feb7 AJ |
140 | case PA_VERREG: |
141 | return 0x10; | |
142 | } | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static void | |
c227f099 | 148 | r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value) |
b319feb7 | 149 | { |
c227f099 | 150 | r2d_fpga_t *s = opaque; |
b319feb7 | 151 | |
b319feb7 | 152 | switch (addr) { |
d47ede60 AZ |
153 | case PA_IRLMSK: |
154 | s->irlmsk = value; | |
155 | update_irl(s); | |
156 | break; | |
b319feb7 AJ |
157 | case PA_OUTPORT: |
158 | s->outport = value; | |
159 | break; | |
160 | case PA_POWOFF: | |
37cc0b44 AJ |
161 | if (value & 1) { |
162 | qemu_system_shutdown_request(); | |
163 | } | |
164 | break; | |
b319feb7 AJ |
165 | case PA_VERREG: |
166 | /* Discard writes */ | |
167 | break; | |
168 | } | |
169 | } | |
170 | ||
d60efc6b | 171 | static CPUReadMemoryFunc * const r2d_fpga_readfn[] = { |
b319feb7 AJ |
172 | r2d_fpga_read, |
173 | r2d_fpga_read, | |
b2463a64 | 174 | NULL, |
b319feb7 AJ |
175 | }; |
176 | ||
d60efc6b | 177 | static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = { |
b319feb7 AJ |
178 | r2d_fpga_write, |
179 | r2d_fpga_write, | |
b2463a64 | 180 | NULL, |
b319feb7 AJ |
181 | }; |
182 | ||
c227f099 | 183 | static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl) |
b319feb7 AJ |
184 | { |
185 | int iomemtype; | |
c227f099 | 186 | r2d_fpga_t *s; |
b319feb7 | 187 | |
7267c094 | 188 | s = g_malloc0(sizeof(r2d_fpga_t)); |
d47ede60 AZ |
189 | |
190 | s->irl = irl; | |
b319feb7 | 191 | |
1eed09cb | 192 | iomemtype = cpu_register_io_memory(r2d_fpga_readfn, |
2507c12a AG |
193 | r2d_fpga_writefn, s, |
194 | DEVICE_NATIVE_ENDIAN); | |
b319feb7 | 195 | cpu_register_physical_memory(base, 0x40, iomemtype); |
d47ede60 | 196 | return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); |
b319feb7 AJ |
197 | } |
198 | ||
4f6493ff AJ |
199 | typedef struct ResetData { |
200 | CPUState *env; | |
201 | uint32_t vector; | |
202 | } ResetData; | |
203 | ||
204 | static void main_cpu_reset(void *opaque) | |
205 | { | |
206 | ResetData *s = (ResetData *)opaque; | |
207 | CPUState *env = s->env; | |
208 | ||
209 | cpu_reset(env); | |
210 | env->pc = s->vector; | |
211 | } | |
212 | ||
541dc0d4 | 213 | static struct QEMU_PACKED |
73f19035 AJ |
214 | { |
215 | int mount_root_rdonly; | |
216 | int ramdisk_flags; | |
217 | int orig_root_dev; | |
218 | int loader_type; | |
219 | int initrd_start; | |
220 | int initrd_size; | |
221 | ||
222 | char pad[232]; | |
223 | ||
224 | char kernel_cmdline[256]; | |
225 | } boot_params; | |
226 | ||
c227f099 | 227 | static void r2d_init(ram_addr_t ram_size, |
3023f332 | 228 | const char *boot_device, |
0d78f544 TS |
229 | const char *kernel_filename, const char *kernel_cmdline, |
230 | const char *initrd_filename, const char *cpu_model) | |
231 | { | |
0d78f544 | 232 | CPUState *env; |
4f6493ff | 233 | ResetData *reset_info; |
0d78f544 | 234 | struct SH7750State *s; |
c227f099 | 235 | ram_addr_t sdram_addr; |
d47ede60 | 236 | qemu_irq *irq; |
751c6a17 | 237 | DriveInfo *dinfo; |
c2f01775 | 238 | int i; |
27a9d2ea | 239 | MemoryRegion *address_space_mem = get_system_memory(); |
0d78f544 | 240 | |
aaed909a | 241 | if (!cpu_model) |
0fd3ca30 | 242 | cpu_model = "SH7751R"; |
aaed909a FB |
243 | |
244 | env = cpu_init(cpu_model); | |
245 | if (!env) { | |
246 | fprintf(stderr, "Unable to find CPU definition\n"); | |
247 | exit(1); | |
248 | } | |
7267c094 | 249 | reset_info = g_malloc0(sizeof(ResetData)); |
4f6493ff AJ |
250 | reset_info->env = env; |
251 | reset_info->vector = env->pc; | |
252 | qemu_register_reset(main_cpu_reset, reset_info); | |
0d78f544 TS |
253 | |
254 | /* Allocate memory space */ | |
1724f049 | 255 | sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE); |
ffd39257 | 256 | cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); |
0d78f544 TS |
257 | /* Register peripherals */ |
258 | s = sh7750_init(env); | |
d47ede60 | 259 | irq = r2d_fpga_init(0x04000000, sh7750_irl(s)); |
cf154394 AJ |
260 | sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB], |
261 | irq[PCI_INTC], irq[PCI_INTD], NULL); | |
d47ede60 | 262 | |
27a9d2ea RH |
263 | sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE, |
264 | irq[SM501], serial_hds[2]); | |
a4a771c0 AZ |
265 | |
266 | /* onboard CF (True IDE mode, Master only). */ | |
612b2bd0 AJ |
267 | dinfo = drive_get(IF_IDE, 0, 0); |
268 | mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, | |
269 | dinfo, NULL); | |
a4a771c0 | 270 | |
56839a19 | 271 | /* onboard flash memory */ |
45e7e4bc | 272 | dinfo = drive_get(IF_PFLASH, 0, 0); |
cfe5f011 | 273 | pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE, |
612b2bd0 AJ |
274 | dinfo ? dinfo->bdrv : NULL, (16 * 1024), |
275 | FLASH_SIZE >> 16, | |
276 | 1, 4, 0x0000, 0x0000, 0x0000, 0x0000, | |
01e0451a | 277 | 0x555, 0x2aa, 0); |
56839a19 | 278 | |
c2f01775 | 279 | /* NIC: rtl8139 on-board, and 2 slots. */ |
ab2da564 | 280 | for (i = 0; i < nb_nics; i++) |
07caea31 | 281 | pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL); |
c2f01775 | 282 | |
9caa3ec1 AJ |
283 | /* USB keyboard */ |
284 | usbdevice_create("keyboard"); | |
285 | ||
0d78f544 | 286 | /* Todo: register on board registers */ |
73f19035 AJ |
287 | memset(&boot_params, 0, sizeof(boot_params)); |
288 | ||
e8afa065 | 289 | if (kernel_filename) { |
73f19035 AJ |
290 | int kernel_size; |
291 | ||
292 | kernel_size = load_image_targphys(kernel_filename, | |
293 | SDRAM_BASE + LINUX_LOAD_OFFSET, | |
294 | INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); | |
295 | if (kernel_size < 0) { | |
296 | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); | |
297 | exit(1); | |
298 | } | |
299 | ||
300 | /* initialization which should be done by firmware */ | |
301 | stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */ | |
302 | stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */ | |
4f6493ff | 303 | reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ |
0d78f544 | 304 | } |
73f19035 AJ |
305 | |
306 | if (initrd_filename) { | |
307 | int initrd_size; | |
308 | ||
309 | initrd_size = load_image_targphys(initrd_filename, | |
310 | SDRAM_BASE + INITRD_LOAD_OFFSET, | |
311 | SDRAM_SIZE - INITRD_LOAD_OFFSET); | |
312 | ||
313 | if (initrd_size < 0) { | |
314 | fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); | |
315 | exit(1); | |
316 | } | |
317 | ||
318 | /* initialization which should be done by firmware */ | |
319 | boot_params.loader_type = 1; | |
320 | boot_params.initrd_start = INITRD_LOAD_OFFSET; | |
321 | boot_params.initrd_size = initrd_size; | |
322 | } | |
323 | ||
324 | if (kernel_cmdline) { | |
325 | strncpy(boot_params.kernel_cmdline, kernel_cmdline, | |
326 | sizeof(boot_params.kernel_cmdline)); | |
327 | } | |
328 | ||
329 | rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), | |
330 | SDRAM_BASE + BOOT_PARAMS_OFFSET); | |
0d78f544 TS |
331 | } |
332 | ||
f80f9ec9 | 333 | static QEMUMachine r2d_machine = { |
4b32e168 AL |
334 | .name = "r2d", |
335 | .desc = "r2d-plus board", | |
336 | .init = r2d_init, | |
0d78f544 | 337 | }; |
f80f9ec9 AL |
338 | |
339 | static void r2d_machine_init(void) | |
340 | { | |
341 | qemu_register_machine(&r2d_machine); | |
342 | } | |
343 | ||
344 | machine_init(r2d_machine_init); |